Lines Matching +full:chip +full:- +full:id
1 // SPDX-License-Identifier: GPL-2.0-or-later
6 * Author: Boris Brezillon <boris.brezillon@free-electrons.com>
20 * struct hynix_read_retry - read-retry data
21 * @nregs: number of register to set when applying a new read-retry mode
22 * @regs: register offsets (NAND chip dependent)
33 * struct hynix_nand - private Hynix NAND struct
35 * @read_retry: read-retry information
42 * struct hynix_read_retry_otp - structure describing how the read-retry OTP
49 * chip
50 * @size: size of the read-retry OTP section
60 static bool hynix_nand_has_valid_jedecid(struct nand_chip *chip) in hynix_nand_has_valid_jedecid() argument
65 ret = nand_readid_op(chip, 0x40, jedecid, sizeof(jedecid)); in hynix_nand_has_valid_jedecid()
72 static int hynix_nand_cmd_op(struct nand_chip *chip, u8 cmd) in hynix_nand_cmd_op() argument
74 if (nand_has_exec_op(chip)) { in hynix_nand_cmd_op()
78 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in hynix_nand_cmd_op()
80 return nand_exec_op(chip, &op); in hynix_nand_cmd_op()
83 chip->legacy.cmdfunc(chip, cmd, -1, -1); in hynix_nand_cmd_op()
88 static int hynix_nand_reg_write_op(struct nand_chip *chip, u8 addr, u8 val) in hynix_nand_reg_write_op() argument
92 if (nand_has_exec_op(chip)) { in hynix_nand_reg_write_op()
97 struct nand_operation op = NAND_OPERATION(chip->cur_cs, instrs); in hynix_nand_reg_write_op()
99 return nand_exec_op(chip, &op); in hynix_nand_reg_write_op()
102 chip->legacy.cmdfunc(chip, NAND_CMD_NONE, column, -1); in hynix_nand_reg_write_op()
103 chip->legacy.write_byte(chip, val); in hynix_nand_reg_write_op()
108 static int hynix_nand_setup_read_retry(struct nand_chip *chip, int retry_mode) in hynix_nand_setup_read_retry() argument
110 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); in hynix_nand_setup_read_retry()
114 values = hynix->read_retry->values + in hynix_nand_setup_read_retry()
115 (retry_mode * hynix->read_retry->nregs); in hynix_nand_setup_read_retry()
118 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); in hynix_nand_setup_read_retry()
123 * Configure the NAND in the requested read-retry mode. in hynix_nand_setup_read_retry()
124 * This is done by setting pre-defined values in internal NAND in hynix_nand_setup_read_retry()
131 for (i = 0; i < hynix->read_retry->nregs; i++) { in hynix_nand_setup_read_retry()
132 ret = hynix_nand_reg_write_op(chip, hynix->read_retry->regs[i], in hynix_nand_setup_read_retry()
139 return hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); in hynix_nand_setup_read_retry()
143 * hynix_get_majority - get the value that is occurring the most in a given
151 * the read-retry parameters.
156 * Let's hope this dummy algorithm prevents us from losing the read-retry
188 return -EIO; in hynix_get_majority()
191 static int hynix_read_rr_otp(struct nand_chip *chip, in hynix_read_rr_otp() argument
197 ret = nand_reset_op(chip); in hynix_read_rr_otp()
201 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); in hynix_read_rr_otp()
205 for (i = 0; i < info->nregs; i++) { in hynix_read_rr_otp()
206 ret = hynix_nand_reg_write_op(chip, info->regs[i], in hynix_read_rr_otp()
207 info->values[i]); in hynix_read_rr_otp()
212 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); in hynix_read_rr_otp()
217 ret = hynix_nand_cmd_op(chip, 0x17); in hynix_read_rr_otp()
221 ret = hynix_nand_cmd_op(chip, 0x4); in hynix_read_rr_otp()
225 ret = hynix_nand_cmd_op(chip, 0x19); in hynix_read_rr_otp()
230 ret = nand_read_page_op(chip, info->page, 0, buf, info->size); in hynix_read_rr_otp()
235 ret = nand_reset_op(chip); in hynix_read_rr_otp()
239 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_SET_PARAMS); in hynix_read_rr_otp()
243 ret = hynix_nand_reg_write_op(chip, 0x38, 0); in hynix_read_rr_otp()
247 ret = hynix_nand_cmd_op(chip, NAND_HYNIX_CMD_APPLY_PARAMS); in hynix_read_rr_otp()
251 return nand_read_page_op(chip, 0, 0, NULL, 0); in hynix_read_rr_otp()
287 static int hynix_mlc_1xnm_rr_init(struct nand_chip *chip, in hynix_mlc_1xnm_rr_init() argument
290 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); in hynix_mlc_1xnm_rr_init()
296 buf = kmalloc(info->size, GFP_KERNEL); in hynix_mlc_1xnm_rr_init()
298 return -ENOMEM; in hynix_mlc_1xnm_rr_init()
300 ret = hynix_read_rr_otp(chip, info, buf); in hynix_mlc_1xnm_rr_init()
317 ret = -ENOMEM; in hynix_mlc_1xnm_rr_init()
323 u8 *val = rr->values + (i * nregs); in hynix_mlc_1xnm_rr_init()
337 rr->nregs = nregs; in hynix_mlc_1xnm_rr_init()
338 rr->regs = hynix_1xnm_mlc_read_retry_regs; in hynix_mlc_1xnm_rr_init()
339 hynix->read_retry = rr; in hynix_mlc_1xnm_rr_init()
340 chip->ops.setup_read_retry = hynix_nand_setup_read_retry; in hynix_mlc_1xnm_rr_init()
341 chip->read_retries = nmodes; in hynix_mlc_1xnm_rr_init()
372 static int hynix_nand_rr_init(struct nand_chip *chip) in hynix_nand_rr_init() argument
377 valid_jedecid = hynix_nand_has_valid_jedecid(chip); in hynix_nand_rr_init()
380 * We only support read-retry for 1xnm NANDs, and those NANDs all in hynix_nand_rr_init()
381 * expose a valid JEDEC ID. in hynix_nand_rr_init()
384 u8 nand_tech = chip->id.data[5] >> 4; in hynix_nand_rr_init()
392 * read-retry OTP area into a normal page. in hynix_nand_rr_init()
394 ret = hynix_mlc_1xnm_rr_init(chip, in hynix_nand_rr_init()
403 pr_warn("failed to initialize read-retry infrastructure"); in hynix_nand_rr_init()
408 static void hynix_nand_extract_oobsize(struct nand_chip *chip, in hynix_nand_extract_oobsize() argument
411 struct mtd_info *mtd = nand_to_mtd(chip); in hynix_nand_extract_oobsize()
415 memorg = nanddev_get_memorg(&chip->base); in hynix_nand_extract_oobsize()
417 oobsize = ((chip->id.data[3] >> 2) & 0x3) | in hynix_nand_extract_oobsize()
418 ((chip->id.data[3] >> 4) & 0x4); in hynix_nand_extract_oobsize()
423 memorg->oobsize = 2048; in hynix_nand_extract_oobsize()
426 memorg->oobsize = 1664; in hynix_nand_extract_oobsize()
429 memorg->oobsize = 1024; in hynix_nand_extract_oobsize()
432 memorg->oobsize = 640; in hynix_nand_extract_oobsize()
438 * a different extended ID format, and we should find in hynix_nand_extract_oobsize()
447 memorg->oobsize = 128; in hynix_nand_extract_oobsize()
450 memorg->oobsize = 224; in hynix_nand_extract_oobsize()
453 memorg->oobsize = 448; in hynix_nand_extract_oobsize()
456 memorg->oobsize = 64; in hynix_nand_extract_oobsize()
459 memorg->oobsize = 32; in hynix_nand_extract_oobsize()
462 memorg->oobsize = 16; in hynix_nand_extract_oobsize()
465 memorg->oobsize = 640; in hynix_nand_extract_oobsize()
471 * a different extended ID format, and we should find in hynix_nand_extract_oobsize()
480 * Area Size" is encoded "per 8KB" (page size). This chip uses in hynix_nand_extract_oobsize()
482 * 1.280 bytes, but the OOB size encoded in the ID bytes (using in hynix_nand_extract_oobsize()
484 * Update the OOB size for this chip by taking the value in hynix_nand_extract_oobsize()
486 * the actual OOB size for this chip is: 640 * 16k / 8k). in hynix_nand_extract_oobsize()
488 if (chip->id.data[1] == 0xde) in hynix_nand_extract_oobsize()
489 memorg->oobsize *= memorg->pagesize / SZ_8K; in hynix_nand_extract_oobsize()
492 mtd->oobsize = memorg->oobsize; in hynix_nand_extract_oobsize()
495 static void hynix_nand_extract_ecc_requirements(struct nand_chip *chip, in hynix_nand_extract_ecc_requirements() argument
498 struct nand_device *base = &chip->base; in hynix_nand_extract_ecc_requirements()
500 u8 ecc_level = (chip->id.data[4] >> 4) & 0x7; in hynix_nand_extract_ecc_requirements()
533 * a different extended ID format, and we should find in hynix_nand_extract_ecc_requirements()
543 u8 nand_tech = chip->id.data[5] & 0x7; in hynix_nand_extract_ecc_requirements()
560 * to use a different extended ID format, and in hynix_nand_extract_ecc_requirements()
572 requirements.strength = 1 << (ecc_level - 1); in hynix_nand_extract_ecc_requirements()
576 (8 * (ecc_level - 5)); in hynix_nand_extract_ecc_requirements()
584 static void hynix_nand_extract_scrambling_requirements(struct nand_chip *chip, in hynix_nand_extract_scrambling_requirements() argument
590 if (nanddev_bits_per_cell(&chip->base) > 2) in hynix_nand_extract_scrambling_requirements()
591 chip->options |= NAND_NEED_SCRAMBLING; in hynix_nand_extract_scrambling_requirements()
593 /* And on MLC NANDs with sub-3xnm process */ in hynix_nand_extract_scrambling_requirements()
595 nand_tech = chip->id.data[5] >> 4; in hynix_nand_extract_scrambling_requirements()
599 chip->options |= NAND_NEED_SCRAMBLING; in hynix_nand_extract_scrambling_requirements()
601 nand_tech = chip->id.data[5] & 0x7; in hynix_nand_extract_scrambling_requirements()
605 chip->options |= NAND_NEED_SCRAMBLING; in hynix_nand_extract_scrambling_requirements()
609 static void hynix_nand_decode_id(struct nand_chip *chip) in hynix_nand_decode_id() argument
611 struct mtd_info *mtd = nand_to_mtd(chip); in hynix_nand_decode_id()
616 memorg = nanddev_get_memorg(&chip->base); in hynix_nand_decode_id()
621 * appear that even SLC NANDs could fall in this extended ID scheme. in hynix_nand_decode_id()
625 if (chip->id.len < 6 || nand_is_slc(chip)) { in hynix_nand_decode_id()
626 nand_decode_ext_id(chip); in hynix_nand_decode_id()
631 memorg->pagesize = 2048 << (chip->id.data[3] & 0x03); in hynix_nand_decode_id()
632 mtd->writesize = memorg->pagesize; in hynix_nand_decode_id()
634 tmp = (chip->id.data[3] >> 4) & 0x3; in hynix_nand_decode_id()
638 * ID[3][4:5]. in hynix_nand_decode_id()
639 * The only exception is when ID[3][4:5] == 3 and ID[3][7] == 0, in in hynix_nand_decode_id()
642 if (chip->id.data[3] & 0x80) { in hynix_nand_decode_id()
643 memorg->pages_per_eraseblock = (SZ_1M << tmp) / in hynix_nand_decode_id()
644 memorg->pagesize; in hynix_nand_decode_id()
645 mtd->erasesize = SZ_1M << tmp; in hynix_nand_decode_id()
647 memorg->pages_per_eraseblock = (SZ_512K + SZ_256K) / in hynix_nand_decode_id()
648 memorg->pagesize; in hynix_nand_decode_id()
649 mtd->erasesize = SZ_512K + SZ_256K; in hynix_nand_decode_id()
651 memorg->pages_per_eraseblock = (SZ_128K << tmp) / in hynix_nand_decode_id()
652 memorg->pagesize; in hynix_nand_decode_id()
653 mtd->erasesize = SZ_128K << tmp; in hynix_nand_decode_id()
659 * These NANDs use a different NAND ID scheme. in hynix_nand_decode_id()
661 valid_jedecid = hynix_nand_has_valid_jedecid(chip); in hynix_nand_decode_id()
663 hynix_nand_extract_oobsize(chip, valid_jedecid); in hynix_nand_decode_id()
664 hynix_nand_extract_ecc_requirements(chip, valid_jedecid); in hynix_nand_decode_id()
665 hynix_nand_extract_scrambling_requirements(chip, valid_jedecid); in hynix_nand_decode_id()
668 static void hynix_nand_cleanup(struct nand_chip *chip) in hynix_nand_cleanup() argument
670 struct hynix_nand *hynix = nand_get_manufacturer_data(chip); in hynix_nand_cleanup()
675 kfree(hynix->read_retry); in hynix_nand_cleanup()
677 nand_set_manufacturer_data(chip, NULL); in hynix_nand_cleanup()
681 h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip, in h27ucg8t2atrbc_choose_interface_config() argument
684 onfi_fill_interface_config(chip, iface, NAND_SDR_IFACE, 4); in h27ucg8t2atrbc_choose_interface_config()
686 return nand_choose_best_sdr_timings(chip, iface, NULL); in h27ucg8t2atrbc_choose_interface_config()
689 static int h27ucg8t2etrbc_init(struct nand_chip *chip) in h27ucg8t2etrbc_init() argument
691 struct mtd_info *mtd = nand_to_mtd(chip); in h27ucg8t2etrbc_init()
693 chip->options |= NAND_NEED_SCRAMBLING; in h27ucg8t2etrbc_init()
699 static int hynix_nand_init(struct nand_chip *chip) in hynix_nand_init() argument
704 if (!nand_is_slc(chip)) in hynix_nand_init()
705 chip->options |= NAND_BBM_LASTPAGE; in hynix_nand_init()
707 chip->options |= NAND_BBM_FIRSTPAGE | NAND_BBM_SECONDPAGE; in hynix_nand_init()
711 return -ENOMEM; in hynix_nand_init()
713 nand_set_manufacturer_data(chip, hynix); in hynix_nand_init()
715 if (!strncmp("H27UCG8T2ATR-BC", chip->parameters.model, in hynix_nand_init()
716 sizeof("H27UCG8T2ATR-BC") - 1)) in hynix_nand_init()
717 chip->ops.choose_interface_config = in hynix_nand_init()
720 if (!strncmp("H27UCG8T2ETR-BC", chip->parameters.model, in hynix_nand_init()
721 sizeof("H27UCG8T2ETR-BC") - 1)) in hynix_nand_init()
722 h27ucg8t2etrbc_init(chip); in hynix_nand_init()
724 ret = hynix_nand_rr_init(chip); in hynix_nand_init()
726 hynix_nand_cleanup(chip); in hynix_nand_init()
731 static void hynix_fixup_onfi_param_page(struct nand_chip *chip, in hynix_fixup_onfi_param_page() argument
736 * (bytes 129-130). This has been seen on H27U4G8F2GDA-BI. in hynix_fixup_onfi_param_page()
740 p->sdr_timing_modes |= cpu_to_le16(BIT(0)); in hynix_fixup_onfi_param_page()