Lines Matching full:ecc

22  *	if we have HW ECC support.
38 #include <linux/mtd/nand-ecc-sw-hamming.h>
39 #include <linux/mtd/nand-ecc-sw-bch.h>
262 res = chip->ecc.read_oob(chip, first_page + page_offset); in nand_block_bad()
479 status = chip->ecc.write_oob_raw(chip, page & chip->pagemask); in nand_do_write_oob()
481 status = chip->ecc.write_oob(chip, page & chip->pagemask); in nand_do_write_oob()
2820 * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
2824 * @ecc: ECC buffer
2825 * @ecclen: ECC length
2830 * Check if a data buffer and its associated ECC and OOB data contains only
2837 * 1/ ECC algorithms are working on pre-defined block sizes which are usually
2838 * different from the NAND page size. When fixing bitflips, ECC engines will
2845 * the payload data but also their associated ECC data, because a user might
2847 * shouldn't consider the chunk as erased, and checking ECC bytes prevent
2850 * data are protected by the ECC engine.
2852 * extra OOB data to an ECC chunk.
2859 void *ecc, int ecclen, in nand_check_erased_ecc_chunk() argument
2872 ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold); in nand_check_erased_ecc_chunk()
2887 memset(ecc, 0xff, ecclen); in nand_check_erased_ecc_chunk()
2912 * nand_read_page_raw - [INTERN] read raw page data without ecc
2918 * Not for syndrome calculating ECC controllers, which use a special oob layout.
2983 * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
2995 int eccsize = chip->ecc.size; in nand_read_page_raw_syndrome()
2996 int eccbytes = chip->ecc.bytes; in nand_read_page_raw_syndrome()
3004 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_read_page_raw_syndrome()
3011 if (chip->ecc.prepad) { in nand_read_page_raw_syndrome()
3012 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, in nand_read_page_raw_syndrome()
3017 oob += chip->ecc.prepad; in nand_read_page_raw_syndrome()
3026 if (chip->ecc.postpad) { in nand_read_page_raw_syndrome()
3027 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, in nand_read_page_raw_syndrome()
3032 oob += chip->ecc.postpad; in nand_read_page_raw_syndrome()
3047 * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
3057 int i, eccsize = chip->ecc.size, ret; in nand_read_page_swecc()
3058 int eccbytes = chip->ecc.bytes; in nand_read_page_swecc()
3059 int eccsteps = chip->ecc.steps; in nand_read_page_swecc()
3061 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_read_page_swecc()
3062 uint8_t *ecc_code = chip->ecc.code_buf; in nand_read_page_swecc()
3065 chip->ecc.read_page_raw(chip, buf, 1, page); in nand_read_page_swecc()
3068 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_read_page_swecc()
3071 chip->ecc.total); in nand_read_page_swecc()
3075 eccsteps = chip->ecc.steps; in nand_read_page_swecc()
3081 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); in nand_read_page_swecc()
3093 * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
3113 /* Column address within the page aligned to ECC size (256bytes) */ in nand_read_subpage()
3114 start_step = data_offs / chip->ecc.size; in nand_read_subpage()
3115 end_step = (data_offs + readlen - 1) / chip->ecc.size; in nand_read_subpage()
3117 index = start_step * chip->ecc.bytes; in nand_read_subpage()
3119 /* Data size aligned to ECC ecc.size */ in nand_read_subpage()
3120 datafrag_len = num_steps * chip->ecc.size; in nand_read_subpage()
3121 eccfrag_len = num_steps * chip->ecc.bytes; in nand_read_subpage()
3123 data_col_addr = start_step * chip->ecc.size; in nand_read_subpage()
3130 /* Calculate ECC */ in nand_read_subpage()
3131 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) in nand_read_subpage()
3132 chip->ecc.calculate(chip, p, &chip->ecc.calc_buf[i]); in nand_read_subpage()
3136 * ecc.pos. Let's make sure that there are no gaps in ECC positions. in nand_read_subpage()
3153 * Send the command to read the particular ECC bytes take care in nand_read_subpage()
3160 if ((oobregion.offset + (num_steps * chip->ecc.bytes)) & in nand_read_subpage()
3172 ret = mtd_ooblayout_get_eccbytes(mtd, chip->ecc.code_buf, in nand_read_subpage()
3178 for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) { in nand_read_subpage()
3181 stat = chip->ecc.correct(chip, p, &chip->ecc.code_buf[i], in nand_read_subpage()
3182 &chip->ecc.calc_buf[i]); in nand_read_subpage()
3184 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_subpage()
3186 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, in nand_read_subpage()
3187 &chip->ecc.code_buf[i], in nand_read_subpage()
3188 chip->ecc.bytes, in nand_read_subpage()
3190 chip->ecc.strength); in nand_read_subpage()
3204 * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
3210 * Not for syndrome calculating ECC controllers which need a special oob layout.
3216 int i, eccsize = chip->ecc.size, ret; in nand_read_page_hwecc()
3217 int eccbytes = chip->ecc.bytes; in nand_read_page_hwecc()
3218 int eccsteps = chip->ecc.steps; in nand_read_page_hwecc()
3220 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_read_page_hwecc()
3221 uint8_t *ecc_code = chip->ecc.code_buf; in nand_read_page_hwecc()
3229 chip->ecc.hwctl(chip, NAND_ECC_READ); in nand_read_page_hwecc()
3235 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_read_page_hwecc()
3244 chip->ecc.total); in nand_read_page_hwecc()
3248 eccsteps = chip->ecc.steps; in nand_read_page_hwecc()
3254 stat = chip->ecc.correct(chip, p, &ecc_code[i], &ecc_calc[i]); in nand_read_page_hwecc()
3256 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_page_hwecc()
3261 chip->ecc.strength); in nand_read_page_hwecc()
3275 * nand_read_page_hwecc_oob_first - Hardware ECC page read with ECC
3282 * Hardware ECC for large page chips, which requires the ECC data to be
3289 int i, eccsize = chip->ecc.size, ret; in nand_read_page_hwecc_oob_first()
3290 int eccbytes = chip->ecc.bytes; in nand_read_page_hwecc_oob_first()
3291 int eccsteps = chip->ecc.steps; in nand_read_page_hwecc_oob_first()
3293 uint8_t *ecc_code = chip->ecc.code_buf; in nand_read_page_hwecc_oob_first()
3307 chip->ecc.total); in nand_read_page_hwecc_oob_first()
3314 chip->ecc.hwctl(chip, NAND_ECC_READ); in nand_read_page_hwecc_oob_first()
3320 stat = chip->ecc.correct(chip, p, &ecc_code[i], NULL); in nand_read_page_hwecc_oob_first()
3322 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_page_hwecc_oob_first()
3327 chip->ecc.strength); in nand_read_page_hwecc_oob_first()
3342 * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
3355 int ret, i, eccsize = chip->ecc.size; in nand_read_page_syndrome()
3356 int eccbytes = chip->ecc.bytes; in nand_read_page_syndrome()
3357 int eccsteps = chip->ecc.steps; in nand_read_page_syndrome()
3358 int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad; in nand_read_page_syndrome()
3370 chip->ecc.hwctl(chip, NAND_ECC_READ); in nand_read_page_syndrome()
3376 if (chip->ecc.prepad) { in nand_read_page_syndrome()
3377 ret = nand_read_data_op(chip, oob, chip->ecc.prepad, in nand_read_page_syndrome()
3382 oob += chip->ecc.prepad; in nand_read_page_syndrome()
3385 chip->ecc.hwctl(chip, NAND_ECC_READSYN); in nand_read_page_syndrome()
3391 stat = chip->ecc.correct(chip, p, oob, NULL); in nand_read_page_syndrome()
3395 if (chip->ecc.postpad) { in nand_read_page_syndrome()
3396 ret = nand_read_data_op(chip, oob, chip->ecc.postpad, in nand_read_page_syndrome()
3401 oob += chip->ecc.postpad; in nand_read_page_syndrome()
3405 (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) { in nand_read_page_syndrome()
3407 stat = nand_check_erased_ecc_chunk(p, chip->ecc.size, in nand_read_page_syndrome()
3411 chip->ecc.strength); in nand_read_page_syndrome()
3513 * when there are too many bitflips in a page (i.e., ECC error). After setting
3541 * nand_do_read_ops - [INTERN] Read data with ECC
3608 * the read methods return max bitflips per ecc step. in nand_do_read_ops()
3611 ret = chip->ecc.read_page_raw(chip, bufpoi, in nand_do_read_ops()
3616 ret = chip->ecc.read_subpage(chip, col, bytes, in nand_do_read_ops()
3619 ret = chip->ecc.read_page(chip, bufpoi, in nand_do_read_ops()
3740 * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
3749 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; in nand_read_oob_syndrome()
3750 int eccsize = chip->ecc.size; in nand_read_oob_syndrome()
3754 ret = nand_read_page_op(chip, page, chip->ecc.size, NULL, 0); in nand_read_oob_syndrome()
3758 for (i = 0; i < chip->ecc.steps; i++) { in nand_read_oob_syndrome()
3808 * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
3816 int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad; in nand_write_oob_syndrome()
3817 int eccsize = chip->ecc.size, length = mtd->oobsize; in nand_write_oob_syndrome()
3818 int ret, i, len, pos, sndcmd = 0, steps = chip->ecc.steps; in nand_write_oob_syndrome()
3822 * data-ecc-data-ecc ... ecc-oob in nand_write_oob_syndrome()
3824 * data-pad-ecc-pad-data-pad .... ecc-pad-oob in nand_write_oob_syndrome()
3826 if (!chip->ecc.prepad && !chip->ecc.postpad) { in nand_write_oob_syndrome()
3920 ret = chip->ecc.read_oob_raw(chip, page); in nand_do_read_oob()
3922 ret = chip->ecc.read_oob(chip, page); in nand_do_read_oob()
4026 * Not for syndrome calculating ECC controllers, which use a special oob layout.
4092 * We need a special oob layout and handling even when ECC isn't checked.
4099 int eccsize = chip->ecc.size; in nand_write_page_raw_syndrome()
4100 int eccbytes = chip->ecc.bytes; in nand_write_page_raw_syndrome()
4108 for (steps = chip->ecc.steps; steps > 0; steps--) { in nand_write_page_raw_syndrome()
4115 if (chip->ecc.prepad) { in nand_write_page_raw_syndrome()
4116 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, in nand_write_page_raw_syndrome()
4121 oob += chip->ecc.prepad; in nand_write_page_raw_syndrome()
4130 if (chip->ecc.postpad) { in nand_write_page_raw_syndrome()
4131 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, in nand_write_page_raw_syndrome()
4136 oob += chip->ecc.postpad; in nand_write_page_raw_syndrome()
4150 * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
4160 int i, eccsize = chip->ecc.size, ret; in nand_write_page_swecc()
4161 int eccbytes = chip->ecc.bytes; in nand_write_page_swecc()
4162 int eccsteps = chip->ecc.steps; in nand_write_page_swecc()
4163 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_page_swecc()
4166 /* Software ECC calculation */ in nand_write_page_swecc()
4168 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_write_page_swecc()
4171 chip->ecc.total); in nand_write_page_swecc()
4175 return chip->ecc.write_page_raw(chip, buf, 1, page); in nand_write_page_swecc()
4179 * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
4189 int i, eccsize = chip->ecc.size, ret; in nand_write_page_hwecc()
4190 int eccbytes = chip->ecc.bytes; in nand_write_page_hwecc()
4191 int eccsteps = chip->ecc.steps; in nand_write_page_hwecc()
4192 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_page_hwecc()
4200 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_page_hwecc()
4206 chip->ecc.calculate(chip, p, &ecc_calc[i]); in nand_write_page_hwecc()
4210 chip->ecc.total); in nand_write_page_hwecc()
4223 * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
4237 uint8_t *ecc_calc = chip->ecc.calc_buf; in nand_write_subpage_hwecc()
4238 int ecc_size = chip->ecc.size; in nand_write_subpage_hwecc()
4239 int ecc_bytes = chip->ecc.bytes; in nand_write_subpage_hwecc()
4240 int ecc_steps = chip->ecc.steps; in nand_write_subpage_hwecc()
4252 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_subpage_hwecc()
4259 /* mask ECC of un-touched subpages by padding 0xFF */ in nand_write_subpage_hwecc()
4263 chip->ecc.calculate(chip, buf, ecc_calc); in nand_write_subpage_hwecc()
4275 /* copy calculated ECC for whole page to chip->buffer->oob */ in nand_write_subpage_hwecc()
4277 ecc_calc = chip->ecc.calc_buf; in nand_write_subpage_hwecc()
4279 chip->ecc.total); in nand_write_subpage_hwecc()
4293 * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
4306 int i, eccsize = chip->ecc.size; in nand_write_page_syndrome()
4307 int eccbytes = chip->ecc.bytes; in nand_write_page_syndrome()
4308 int eccsteps = chip->ecc.steps; in nand_write_page_syndrome()
4318 chip->ecc.hwctl(chip, NAND_ECC_WRITE); in nand_write_page_syndrome()
4324 if (chip->ecc.prepad) { in nand_write_page_syndrome()
4325 ret = nand_write_data_op(chip, oob, chip->ecc.prepad, in nand_write_page_syndrome()
4330 oob += chip->ecc.prepad; in nand_write_page_syndrome()
4333 chip->ecc.calculate(chip, p, oob); in nand_write_page_syndrome()
4341 if (chip->ecc.postpad) { in nand_write_page_syndrome()
4342 ret = nand_write_data_op(chip, oob, chip->ecc.postpad, in nand_write_page_syndrome()
4347 oob += chip->ecc.postpad; in nand_write_page_syndrome()
4380 chip->ecc.write_subpage) in nand_write_page()
4386 status = chip->ecc.write_page_raw(chip, buf, oob_required, in nand_write_page()
4389 status = chip->ecc.write_subpage(chip, offset, data_len, buf, in nand_write_page()
4392 status = chip->ecc.write_page(chip, buf, oob_required, page); in nand_write_page()
4403 * nand_do_write_ops - [INTERN] NAND write with ECC
4408 * NAND write with ECC.
4536 * panic_nand_write - [MTD Interface] NAND write with ECC
4543 * NAND write with ECC. Used when performing writes in interrupt context, this
5189 * ECC correction enabled, so in this case refuse to perform the in rawnand_late_check_supported_ops()
5192 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_ON_DIE) in rawnand_late_check_supported_ops()
5417 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_engine_type_legacy()
5450 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_placement_legacy()
5464 err = of_property_read_string(np, "nand-ecc-mode", &pm); in of_get_rawnand_ecc_algo_legacy()
5478 struct nand_ecc_props *user_conf = &chip->base.ecc.user_conf; in of_get_nand_ecc_legacy_user_config()
5602 * ECC engine type, we will default to NAND_ECC_ENGINE_TYPE_ON_HOST. in rawnand_dt_init()
5604 nand->ecc.defaults.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in rawnand_dt_init()
5611 if (nand->ecc.user_conf.engine_type != NAND_ECC_ENGINE_TYPE_INVALID) in rawnand_dt_init()
5612 chip->ecc.engine_type = nand->ecc.user_conf.engine_type; in rawnand_dt_init()
5613 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_INVALID) in rawnand_dt_init()
5614 chip->ecc.engine_type = nand->ecc.defaults.engine_type; in rawnand_dt_init()
5616 chip->ecc.placement = nand->ecc.user_conf.placement; in rawnand_dt_init()
5617 chip->ecc.algo = nand->ecc.user_conf.algo; in rawnand_dt_init()
5618 chip->ecc.strength = nand->ecc.user_conf.strength; in rawnand_dt_init()
5619 chip->ecc.size = nand->ecc.user_conf.step_size; in rawnand_dt_init()
5634 * to tweak some ECC-related parameters before nand_scan_tail(). This separation
5731 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in rawnand_sw_hamming_init()
5732 base->ecc.user_conf.algo = NAND_ECC_ALGO_HAMMING; in rawnand_sw_hamming_init()
5733 base->ecc.user_conf.strength = chip->ecc.strength; in rawnand_sw_hamming_init()
5734 base->ecc.user_conf.step_size = chip->ecc.size; in rawnand_sw_hamming_init()
5740 engine_conf = base->ecc.ctx.priv; in rawnand_sw_hamming_init()
5742 if (chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER) in rawnand_sw_hamming_init()
5745 chip->ecc.size = base->ecc.ctx.conf.step_size; in rawnand_sw_hamming_init()
5746 chip->ecc.strength = base->ecc.ctx.conf.strength; in rawnand_sw_hamming_init()
5747 chip->ecc.total = base->ecc.ctx.total; in rawnand_sw_hamming_init()
5748 chip->ecc.steps = nanddev_get_ecc_nsteps(base); in rawnand_sw_hamming_init()
5749 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); in rawnand_sw_hamming_init()
5790 base->ecc.user_conf.engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in rawnand_sw_bch_init()
5791 base->ecc.user_conf.algo = NAND_ECC_ALGO_BCH; in rawnand_sw_bch_init()
5792 base->ecc.user_conf.step_size = chip->ecc.size; in rawnand_sw_bch_init()
5793 base->ecc.user_conf.strength = chip->ecc.strength; in rawnand_sw_bch_init()
5799 chip->ecc.size = ecc_conf->step_size; in rawnand_sw_bch_init()
5800 chip->ecc.strength = ecc_conf->strength; in rawnand_sw_bch_init()
5801 chip->ecc.total = base->ecc.ctx.total; in rawnand_sw_bch_init()
5802 chip->ecc.steps = nanddev_get_ecc_nsteps(base); in rawnand_sw_bch_init()
5803 chip->ecc.bytes = base->ecc.ctx.total / nanddev_get_ecc_nsteps(base); in rawnand_sw_bch_init()
5837 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_set_ecc_on_host_ops() local
5839 switch (ecc->placement) { in nand_set_ecc_on_host_ops()
5843 if (!ecc->read_page) in nand_set_ecc_on_host_ops()
5844 ecc->read_page = nand_read_page_hwecc; in nand_set_ecc_on_host_ops()
5845 if (!ecc->write_page) in nand_set_ecc_on_host_ops()
5846 ecc->write_page = nand_write_page_hwecc; in nand_set_ecc_on_host_ops()
5847 if (!ecc->read_page_raw) in nand_set_ecc_on_host_ops()
5848 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_on_host_ops()
5849 if (!ecc->write_page_raw) in nand_set_ecc_on_host_ops()
5850 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_on_host_ops()
5851 if (!ecc->read_oob) in nand_set_ecc_on_host_ops()
5852 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_on_host_ops()
5853 if (!ecc->write_oob) in nand_set_ecc_on_host_ops()
5854 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_on_host_ops()
5855 if (!ecc->read_subpage) in nand_set_ecc_on_host_ops()
5856 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_on_host_ops()
5857 if (!ecc->write_subpage && ecc->hwctl && ecc->calculate) in nand_set_ecc_on_host_ops()
5858 ecc->write_subpage = nand_write_subpage_hwecc; in nand_set_ecc_on_host_ops()
5862 if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) && in nand_set_ecc_on_host_ops()
5863 (!ecc->read_page || in nand_set_ecc_on_host_ops()
5864 ecc->read_page == nand_read_page_hwecc || in nand_set_ecc_on_host_ops()
5865 !ecc->write_page || in nand_set_ecc_on_host_ops()
5866 ecc->write_page == nand_write_page_hwecc)) { in nand_set_ecc_on_host_ops()
5867 WARN(1, "No ECC functions supplied; hardware ECC not possible\n"); in nand_set_ecc_on_host_ops()
5871 if (!ecc->read_page) in nand_set_ecc_on_host_ops()
5872 ecc->read_page = nand_read_page_syndrome; in nand_set_ecc_on_host_ops()
5873 if (!ecc->write_page) in nand_set_ecc_on_host_ops()
5874 ecc->write_page = nand_write_page_syndrome; in nand_set_ecc_on_host_ops()
5875 if (!ecc->read_page_raw) in nand_set_ecc_on_host_ops()
5876 ecc->read_page_raw = nand_read_page_raw_syndrome; in nand_set_ecc_on_host_ops()
5877 if (!ecc->write_page_raw) in nand_set_ecc_on_host_ops()
5878 ecc->write_page_raw = nand_write_page_raw_syndrome; in nand_set_ecc_on_host_ops()
5879 if (!ecc->read_oob) in nand_set_ecc_on_host_ops()
5880 ecc->read_oob = nand_read_oob_syndrome; in nand_set_ecc_on_host_ops()
5881 if (!ecc->write_oob) in nand_set_ecc_on_host_ops()
5882 ecc->write_oob = nand_write_oob_syndrome; in nand_set_ecc_on_host_ops()
5887 ecc->placement); in nand_set_ecc_on_host_ops()
5898 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_set_ecc_soft_ops() local
5901 if (WARN_ON(ecc->engine_type != NAND_ECC_ENGINE_TYPE_SOFT)) in nand_set_ecc_soft_ops()
5904 switch (ecc->algo) { in nand_set_ecc_soft_ops()
5906 ecc->calculate = rawnand_sw_hamming_calculate; in nand_set_ecc_soft_ops()
5907 ecc->correct = rawnand_sw_hamming_correct; in nand_set_ecc_soft_ops()
5908 ecc->read_page = nand_read_page_swecc; in nand_set_ecc_soft_ops()
5909 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_soft_ops()
5910 ecc->write_page = nand_write_page_swecc; in nand_set_ecc_soft_ops()
5911 if (!ecc->read_page_raw) in nand_set_ecc_soft_ops()
5912 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_soft_ops()
5913 if (!ecc->write_page_raw) in nand_set_ecc_soft_ops()
5914 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_soft_ops()
5915 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_soft_ops()
5916 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_soft_ops()
5917 if (!ecc->size) in nand_set_ecc_soft_ops()
5918 ecc->size = 256; in nand_set_ecc_soft_ops()
5919 ecc->bytes = 3; in nand_set_ecc_soft_ops()
5920 ecc->strength = 1; in nand_set_ecc_soft_ops()
5923 ecc->options |= NAND_ECC_SOFT_HAMMING_SM_ORDER; in nand_set_ecc_soft_ops()
5927 WARN(1, "Hamming ECC initialization failed!\n"); in nand_set_ecc_soft_ops()
5937 ecc->calculate = rawnand_sw_bch_calculate; in nand_set_ecc_soft_ops()
5938 ecc->correct = rawnand_sw_bch_correct; in nand_set_ecc_soft_ops()
5939 ecc->read_page = nand_read_page_swecc; in nand_set_ecc_soft_ops()
5940 ecc->read_subpage = nand_read_subpage; in nand_set_ecc_soft_ops()
5941 ecc->write_page = nand_write_page_swecc; in nand_set_ecc_soft_ops()
5942 if (!ecc->read_page_raw) in nand_set_ecc_soft_ops()
5943 ecc->read_page_raw = nand_read_page_raw; in nand_set_ecc_soft_ops()
5944 if (!ecc->write_page_raw) in nand_set_ecc_soft_ops()
5945 ecc->write_page_raw = nand_write_page_raw; in nand_set_ecc_soft_ops()
5946 ecc->read_oob = nand_read_oob_std; in nand_set_ecc_soft_ops()
5947 ecc->write_oob = nand_write_oob_std; in nand_set_ecc_soft_ops()
5950 * We can only maximize ECC config when the default layout is in nand_set_ecc_soft_ops()
5954 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH && in nand_set_ecc_soft_ops()
5956 nanddev->ecc.user_conf.flags &= ~NAND_ECC_MAXIMIZE_STRENGTH; in nand_set_ecc_soft_ops()
5960 WARN(1, "BCH ECC initialization failed!\n"); in nand_set_ecc_soft_ops()
5966 WARN(1, "Unsupported ECC algorithm!\n"); in nand_set_ecc_soft_ops()
5972 * nand_check_ecc_caps - check the sanity of preset ECC settings
5974 * @caps: ECC caps info structure
5975 * @oobavail: OOB size that the ECC engine can use
5977 * When ECC step size and strength are already set, check if they are supported
5978 * by the controller and the calculated ECC bytes fit within the chip's OOB.
5979 * On success, the calculated ECC bytes is set.
5987 int preset_step = chip->ecc.size; in nand_check_ecc_caps()
5988 int preset_strength = chip->ecc.strength; in nand_check_ecc_caps()
6008 pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB", in nand_check_ecc_caps()
6013 chip->ecc.bytes = ecc_bytes; in nand_check_ecc_caps()
6019 pr_err("ECC (step, strength) = (%d, %d) not supported on this controller", in nand_check_ecc_caps()
6026 * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
6028 * @caps: ECC engine caps info structure
6029 * @oobavail: OOB size that the ECC engine can use
6031 * If a chip's ECC requirement is provided, try to meet it with the least
6032 * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
6033 * On success, the chosen ECC settings are set.
6088 * with the least number of ECC bytes. in nand_match_ecc_req()
6102 chip->ecc.size = best_step; in nand_match_ecc_req()
6103 chip->ecc.strength = best_strength; in nand_match_ecc_req()
6104 chip->ecc.bytes = best_ecc_bytes; in nand_match_ecc_req()
6110 * nand_maximize_ecc - choose the max ECC strength available
6112 * @caps: ECC engine caps info structure
6113 * @oobavail: OOB size that the ECC engine can use
6115 * Choose the max ECC strength that is supported on the controller, and can fit
6116 * within the chip's OOB. On success, the chosen ECC settings are set.
6134 /* If chip->ecc.size is already set, respect it */ in nand_maximize_ecc()
6135 if (chip->ecc.size && step_size != chip->ecc.size) in nand_maximize_ecc()
6172 chip->ecc.size = best_step; in nand_maximize_ecc()
6173 chip->ecc.strength = best_strength; in nand_maximize_ecc()
6174 chip->ecc.bytes = best_ecc_bytes; in nand_maximize_ecc()
6180 * nand_ecc_choose_conf - Set the ECC strength and ECC step size
6182 * @caps: ECC engine caps info structure
6183 * @oobavail: OOB size that the ECC engine can use
6185 * Choose the ECC configuration according to following logic.
6187 * 1. If both ECC step size and ECC strength are already set (usually by DT)
6189 * 2. If the user provided the nand-ecc-maximize property, then select maximum
6190 * ECC strength.
6191 * 3. Otherwise, try to match the ECC step size and ECC strength closest
6193 * requirement then fallback to the maximum ECC step size and ECC strength.
6195 * On success, the chosen ECC settings are set.
6206 if (chip->ecc.size && chip->ecc.strength) in nand_ecc_choose_conf()
6209 if (nanddev->ecc.user_conf.flags & NAND_ECC_MAXIMIZE_STRENGTH) in nand_ecc_choose_conf()
6274 struct nand_ecc_ctrl *ecc = &chip->ecc; in nand_scan_tail() local
6306 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in nand_scan_tail()
6307 ecc->algo == NAND_ECC_ALGO_BCH) && in nand_scan_tail()
6308 !(ecc->engine_type == NAND_ECC_ENGINE_TYPE_SOFT && in nand_scan_tail()
6309 ecc->algo == NAND_ECC_ALGO_HAMMING)) { in nand_scan_tail()
6325 * page with ECC layout when ->oobsize <= 128 for in nand_scan_tail()
6328 if (ecc->engine_type == NAND_ECC_ENGINE_TYPE_NONE) { in nand_scan_tail()
6342 * Check ECC mode, default to software if 3byte/512byte hardware ECC is in nand_scan_tail()
6343 * selected and we have 256 byte pagesize fallback to software ECC in nand_scan_tail()
6346 switch (ecc->engine_type) { in nand_scan_tail()
6352 if (mtd->writesize >= ecc->size) { in nand_scan_tail()
6353 if (!ecc->strength) { in nand_scan_tail()
6354 WARN(1, "Driver must set ecc.strength when using hardware ECC\n"); in nand_scan_tail()
6360 pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n", in nand_scan_tail()
6361 ecc->size, mtd->writesize); in nand_scan_tail()
6362 ecc->engine_type = NAND_ECC_ENGINE_TYPE_SOFT; in nand_scan_tail()
6363 ecc->algo = NAND_ECC_ALGO_HAMMING; in nand_scan_tail()
6373 if (!ecc->read_page || !ecc->write_page) { in nand_scan_tail()
6374 WARN(1, "No ECC functions supplied; on-die ECC not possible\n"); in nand_scan_tail()
6378 if (!ecc->read_oob) in nand_scan_tail()
6379 ecc->read_oob = nand_read_oob_std; in nand_scan_tail()
6380 if (!ecc->write_oob) in nand_scan_tail()
6381 ecc->write_oob = nand_write_oob_std; in nand_scan_tail()
6386 ecc->read_page = nand_read_page_raw; in nand_scan_tail()
6387 ecc->write_page = nand_write_page_raw; in nand_scan_tail()
6388 ecc->read_oob = nand_read_oob_std; in nand_scan_tail()
6389 ecc->read_page_raw = nand_read_page_raw; in nand_scan_tail()
6390 ecc->write_page_raw = nand_write_page_raw; in nand_scan_tail()
6391 ecc->write_oob = nand_write_oob_std; in nand_scan_tail()
6392 ecc->size = mtd->writesize; in nand_scan_tail()
6393 ecc->bytes = 0; in nand_scan_tail()
6394 ecc->strength = 0; in nand_scan_tail()
6398 WARN(1, "Invalid NAND_ECC_MODE %d\n", ecc->engine_type); in nand_scan_tail()
6403 if (ecc->correct || ecc->calculate) { in nand_scan_tail()
6404 ecc->calc_buf = kmalloc(mtd->oobsize, GFP_KERNEL); in nand_scan_tail()
6405 ecc->code_buf = kmalloc(mtd->oobsize, GFP_KERNEL); in nand_scan_tail()
6406 if (!ecc->calc_buf || !ecc->code_buf) { in nand_scan_tail()
6413 if (!ecc->read_oob_raw) in nand_scan_tail()
6414 ecc->read_oob_raw = ecc->read_oob; in nand_scan_tail()
6415 if (!ecc->write_oob_raw) in nand_scan_tail()
6416 ecc->write_oob_raw = ecc->write_oob; in nand_scan_tail()
6418 /* propagate ecc info to mtd_info */ in nand_scan_tail()
6419 mtd->ecc_strength = ecc->strength; in nand_scan_tail()
6420 mtd->ecc_step_size = ecc->size; in nand_scan_tail()
6423 * Set the number of read / write steps for one page depending on ECC in nand_scan_tail()
6426 if (!ecc->steps) in nand_scan_tail()
6427 ecc->steps = mtd->writesize / ecc->size; in nand_scan_tail()
6428 if (ecc->steps * ecc->size != mtd->writesize) { in nand_scan_tail()
6429 WARN(1, "Invalid ECC parameters\n"); in nand_scan_tail()
6434 if (!ecc->total) { in nand_scan_tail()
6435 ecc->total = ecc->steps * ecc->bytes; in nand_scan_tail()
6436 chip->base.ecc.ctx.total = ecc->total; in nand_scan_tail()
6439 if (ecc->total > mtd->oobsize) { in nand_scan_tail()
6440 WARN(1, "Total number of ECC bytes exceeded oobsize\n"); in nand_scan_tail()
6455 /* ECC sanity check: warn if it's too weak */ in nand_scan_tail()
6457 …pr_warn("WARNING: %s: the ECC used on your system (%db/%dB) is too weak compared to the one requir… in nand_scan_tail()
6458 mtd->name, chip->ecc.strength, chip->ecc.size, in nand_scan_tail()
6462 /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */ in nand_scan_tail()
6464 switch (ecc->steps) { in nand_scan_tail()
6481 switch (ecc->engine_type) { in nand_scan_tail()
6574 kfree(ecc->code_buf); in nand_scan_tail()
6575 kfree(ecc->calc_buf); in nand_scan_tail()
6641 if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT) { in nand_cleanup()
6642 if (chip->ecc.algo == NAND_ECC_ALGO_HAMMING) in nand_cleanup()
6644 else if (chip->ecc.algo == NAND_ECC_ALGO_BCH) in nand_cleanup()
6656 kfree(chip->ecc.code_buf); in nand_cleanup()
6657 kfree(chip->ecc.calc_buf); in nand_cleanup()