Lines Matching +full:nand +full:- +full:is +full:- +full:boot +full:- +full:medium
1 // SPDX-License-Identifier: GPL-2.0+
3 * Freescale GPMI NAND Flash Driver
5 * Copyright (C) 2010-2015 Freescale Semiconductor, Inc.
18 #include <linux/dma/mxs-dma.h>
19 #include "gpmi-nand.h"
20 #include "gpmi-regs.h"
21 #include "bch-regs.h"
23 /* Resource names for the GPMI NAND driver. */
24 #define GPMI_NAND_GPMI_REGS_ADDR_RES_NAME "gpmi-nand"
34 * Clear the bit and poll it cleared. This is usually called with
52 while ((readl(addr) & mask) && --timeout) in clear_poll_bit()
66 * But in MX23, there is a hardware bug in the BCH block (see erratum #2847).
68 * the next hard reset. This case occurs in the NAND boot mode. When the board
69 * boots by NAND, the ROM of the chip will initialize the BCH blocks itself.
96 while ((!(readl(reset_addr) & MODULE_CLKGATE)) && --timeout) in gpmi_reset_block()
116 return -ETIMEDOUT; in gpmi_reset_block()
126 clk = this->resources.clock[i]; in __gpmi_enable_clk()
141 for (; i > 0; i--) in __gpmi_enable_clk()
142 clk_disable_unprepare(this->resources.clock[i - 1]); in __gpmi_enable_clk()
148 struct resources *r = &this->resources; in gpmi_init()
151 ret = pm_runtime_resume_and_get(this->dev); in gpmi_init()
155 ret = gpmi_reset_block(r->gpmi_regs, false); in gpmi_init()
163 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this)); in gpmi_init()
167 /* Choose NAND mode. */ in gpmi_init()
168 writel(BM_GPMI_CTRL1_GPMI_MODE, r->gpmi_regs + HW_GPMI_CTRL1_CLR); in gpmi_init()
172 r->gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_init()
174 /* Disable Write-Protection. */ in gpmi_init()
175 writel(BM_GPMI_CTRL1_DEV_RESET, r->gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_init()
178 writel(BM_GPMI_CTRL1_BCH_MODE, r->gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_init()
182 * the chips, force all NAND RDY_BUSY inputs to be sourced from in gpmi_init()
186 r->gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_init()
189 pm_runtime_mark_last_busy(this->dev); in gpmi_init()
190 pm_runtime_put_autosuspend(this->dev); in gpmi_init()
194 /* This function is very useful. It is called only when the bug occur. */
197 struct resources *r = &this->resources; in gpmi_dump_info()
198 struct bch_geometry *geo = &this->bch_geometry; in gpmi_dump_info()
202 dev_err(this->dev, "Show GPMI registers :\n"); in gpmi_dump_info()
204 reg = readl(r->gpmi_regs + i * 0x10); in gpmi_dump_info()
205 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg); in gpmi_dump_info()
209 dev_err(this->dev, "Show BCH registers :\n"); in gpmi_dump_info()
211 reg = readl(r->bch_regs + i * 0x10); in gpmi_dump_info()
212 dev_err(this->dev, "offset 0x%.3x : 0x%.8x\n", i * 0x10, reg); in gpmi_dump_info()
214 dev_err(this->dev, "BCH Geometry :\n" in gpmi_dump_info()
227 geo->gf_len, in gpmi_dump_info()
228 geo->ecc_strength, in gpmi_dump_info()
229 geo->page_size, in gpmi_dump_info()
230 geo->metadata_size, in gpmi_dump_info()
231 geo->ecc0_chunk_size, in gpmi_dump_info()
232 geo->eccn_chunk_size, in gpmi_dump_info()
233 geo->ecc_chunk_count, in gpmi_dump_info()
234 geo->payload_size, in gpmi_dump_info()
235 geo->auxiliary_size, in gpmi_dump_info()
236 geo->auxiliary_status_offset, in gpmi_dump_info()
237 geo->block_mark_byte_offset, in gpmi_dump_info()
238 geo->block_mark_bit_offset); in gpmi_dump_info()
243 struct nand_chip *chip = &this->nand; in gpmi_check_ecc()
244 struct bch_geometry *geo = &this->bch_geometry; in gpmi_check_ecc()
245 struct nand_device *nand = &chip->base; in gpmi_check_ecc() local
246 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; in gpmi_check_ecc()
248 conf->step_size = geo->eccn_chunk_size; in gpmi_check_ecc()
249 conf->strength = geo->ecc_strength; in gpmi_check_ecc()
254 if (geo->gf_len == 14) in gpmi_check_ecc()
258 if (geo->ecc_strength > this->devdata->bch_max_ecc_strength) in gpmi_check_ecc()
261 if (!nand_ecc_is_strong_enough(nand)) in gpmi_check_ecc()
271 struct bch_geometry *geo = &this->bch_geometry; in bbm_in_data_chunk()
272 struct nand_chip *chip = &this->nand; in bbm_in_data_chunk()
276 if (geo->ecc0_chunk_size != geo->eccn_chunk_size) { in bbm_in_data_chunk()
277 dev_err(this->dev, in bbm_in_data_chunk()
282 i = (mtd->writesize * 8 - geo->metadata_size * 8) / in bbm_in_data_chunk()
283 (geo->gf_len * geo->ecc_strength + in bbm_in_data_chunk()
284 geo->eccn_chunk_size * 8); in bbm_in_data_chunk()
286 j = (mtd->writesize * 8 - geo->metadata_size * 8) - in bbm_in_data_chunk()
287 (geo->gf_len * geo->ecc_strength + in bbm_in_data_chunk()
288 geo->eccn_chunk_size * 8) * i; in bbm_in_data_chunk()
290 if (j < geo->eccn_chunk_size * 8) { in bbm_in_data_chunk()
292 dev_dbg(this->dev, "Set ecc to %d and bbm in chunk %d\n", in bbm_in_data_chunk()
293 geo->ecc_strength, *chunk_num); in bbm_in_data_chunk()
301 * If we can get the ECC information from the nand chip, we do not
310 struct bch_geometry *geo = &this->bch_geometry; in set_geometry_by_ecc_info()
311 struct nand_chip *chip = &this->nand; in set_geometry_by_ecc_info()
317 geo->gf_len = 13; in set_geometry_by_ecc_info()
320 geo->gf_len = 14; in set_geometry_by_ecc_info()
323 dev_err(this->dev, in set_geometry_by_ecc_info()
324 "unsupported nand chip. ecc bits : %d, ecc size : %d\n", in set_geometry_by_ecc_info()
325 nanddev_get_ecc_requirements(&chip->base)->strength, in set_geometry_by_ecc_info()
326 nanddev_get_ecc_requirements(&chip->base)->step_size); in set_geometry_by_ecc_info()
327 return -EINVAL; in set_geometry_by_ecc_info()
329 geo->ecc0_chunk_size = ecc_step; in set_geometry_by_ecc_info()
330 geo->eccn_chunk_size = ecc_step; in set_geometry_by_ecc_info()
331 geo->ecc_strength = round_up(ecc_strength, 2); in set_geometry_by_ecc_info()
333 return -EINVAL; in set_geometry_by_ecc_info()
336 if (geo->eccn_chunk_size < mtd->oobsize) { in set_geometry_by_ecc_info()
337 dev_err(this->dev, in set_geometry_by_ecc_info()
338 "unsupported nand chip. ecc size: %d, oob size : %d\n", in set_geometry_by_ecc_info()
339 ecc_step, mtd->oobsize); in set_geometry_by_ecc_info()
340 return -EINVAL; in set_geometry_by_ecc_info()
344 geo->metadata_size = 10; in set_geometry_by_ecc_info()
346 geo->ecc_chunk_count = mtd->writesize / geo->eccn_chunk_size; in set_geometry_by_ecc_info()
349 * Now, the NAND chip with 2K page(data chunk is 512byte) shows below: in set_geometry_by_ecc_info()
352 * |<----------------------------------------------------->| in set_geometry_by_ecc_info()
356 * |<-------------------------------------------->| D | | O' | in set_geometry_by_ecc_info()
357 * | |<---->| |<--->| in set_geometry_by_ecc_info()
359 * +---+----------+-+----------+-+----------+-+----------+-+-----+ in set_geometry_by_ecc_info()
361 * +---+----------+-+----------+-+----------+-+----------+-+-----+ in set_geometry_by_ecc_info()
364 * |<------------>| in set_geometry_by_ecc_info()
373 * P': the nand chip's page size. in set_geometry_by_ecc_info()
374 * O : the nand chip's oob size. in set_geometry_by_ecc_info()
377 * The formula for P is : in set_geometry_by_ecc_info()
380 * P = ------------ + P' + M in set_geometry_by_ecc_info()
383 * The position of block mark moves forward in the ECC-based view in set_geometry_by_ecc_info()
384 * of page, and the delta is: in set_geometry_by_ecc_info()
386 * E * G * (N - 1) in set_geometry_by_ecc_info()
387 * D = (---------------- + M) in set_geometry_by_ecc_info()
392 * So the bit position of the physical block mark within the ECC-based in set_geometry_by_ecc_info()
393 * view of the page is : in set_geometry_by_ecc_info()
394 * (P' - D) * 8 in set_geometry_by_ecc_info()
396 geo->page_size = mtd->writesize + geo->metadata_size + in set_geometry_by_ecc_info()
397 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8; in set_geometry_by_ecc_info()
399 geo->payload_size = mtd->writesize; in set_geometry_by_ecc_info()
401 geo->auxiliary_status_offset = ALIGN(geo->metadata_size, 4); in set_geometry_by_ecc_info()
402 geo->auxiliary_size = ALIGN(geo->metadata_size, 4) in set_geometry_by_ecc_info()
403 + ALIGN(geo->ecc_chunk_count, 4); in set_geometry_by_ecc_info()
405 if (!this->swap_block_mark) in set_geometry_by_ecc_info()
409 block_mark_bit_offset = mtd->writesize * 8 - in set_geometry_by_ecc_info()
410 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1) in set_geometry_by_ecc_info()
411 + geo->metadata_size * 8); in set_geometry_by_ecc_info()
413 geo->block_mark_byte_offset = block_mark_bit_offset / 8; in set_geometry_by_ecc_info()
414 geo->block_mark_bit_offset = block_mark_bit_offset % 8; in set_geometry_by_ecc_info()
423 * O : the oobsize of the NAND chip.
426 * The formula is :
428 * ------------ <= (O - M)
432 * (O - M) * 8
433 * E <= -------------
438 struct bch_geometry *geo = &this->bch_geometry; in get_ecc_strength()
439 struct mtd_info *mtd = nand_to_mtd(&this->nand); in get_ecc_strength()
442 ecc_strength = ((mtd->oobsize - geo->metadata_size) * 8) in get_ecc_strength()
443 / (geo->gf_len * geo->ecc_chunk_count); in get_ecc_strength()
451 struct bch_geometry *geo = &this->bch_geometry; in set_geometry_for_large_oob()
452 struct nand_chip *chip = &this->nand; in set_geometry_for_large_oob()
455 nanddev_get_ecc_requirements(&chip->base); in set_geometry_for_large_oob()
461 /* sanity check for the minimum ecc nand required */ in set_geometry_for_large_oob()
462 if (!(requirements->strength > 0 && in set_geometry_for_large_oob()
463 requirements->step_size > 0)) in set_geometry_for_large_oob()
464 return -EINVAL; in set_geometry_for_large_oob()
465 geo->ecc_strength = requirements->strength; in set_geometry_for_large_oob()
467 /* check if platform can support this nand */ in set_geometry_for_large_oob()
469 dev_err(this->dev, in set_geometry_for_large_oob()
470 "unsupported NAND chip, minimum ecc required %d\n", in set_geometry_for_large_oob()
471 geo->ecc_strength); in set_geometry_for_large_oob()
472 return -EINVAL; in set_geometry_for_large_oob()
476 geo->metadata_size = 10; in set_geometry_for_large_oob()
477 geo->gf_len = 14; in set_geometry_for_large_oob()
478 geo->ecc0_chunk_size = 1024; in set_geometry_for_large_oob()
479 geo->eccn_chunk_size = 1024; in set_geometry_for_large_oob()
480 geo->ecc_chunk_count = mtd->writesize / geo->eccn_chunk_size; in set_geometry_for_large_oob()
482 this->devdata->bch_max_ecc_strength); in set_geometry_for_large_oob()
488 geo->ecc_strength = max_ecc; in set_geometry_for_large_oob()
489 while (!(geo->ecc_strength < requirements->strength)) { in set_geometry_for_large_oob()
492 geo->ecc_strength -= 2; in set_geometry_for_large_oob()
496 /* nand required but changing ecc page layout */ in set_geometry_for_large_oob()
497 geo->ecc_strength = requirements->strength; in set_geometry_for_large_oob()
499 geo->ecc0_chunk_size = 0; in set_geometry_for_large_oob()
500 geo->ecc_chunk_count = (mtd->writesize / geo->eccn_chunk_size) + 1; in set_geometry_for_large_oob()
501 geo->ecc_for_meta = 1; in set_geometry_for_large_oob()
503 if (mtd->oobsize * 8 < geo->metadata_size * 8 + in set_geometry_for_large_oob()
504 geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) { in set_geometry_for_large_oob()
505 dev_err(this->dev, "unsupported NAND chip with new layout\n"); in set_geometry_for_large_oob()
506 return -EINVAL; in set_geometry_for_large_oob()
510 bbm_chunk = (mtd->writesize * 8 - geo->metadata_size * 8 - in set_geometry_for_large_oob()
511 geo->gf_len * geo->ecc_strength) / in set_geometry_for_large_oob()
512 (geo->gf_len * geo->ecc_strength + in set_geometry_for_large_oob()
513 geo->eccn_chunk_size * 8) + 1; in set_geometry_for_large_oob()
517 geo->page_size = mtd->writesize + geo->metadata_size + in set_geometry_for_large_oob()
518 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8; in set_geometry_for_large_oob()
519 geo->payload_size = mtd->writesize; in set_geometry_for_large_oob()
523 * metadata is padded to the nearest 32-bit boundary. The ECC status in set_geometry_for_large_oob()
524 * contains one byte for every ECC chunk, and is also padded to the in set_geometry_for_large_oob()
525 * nearest 32-bit boundary. in set_geometry_for_large_oob()
527 geo->auxiliary_status_offset = ALIGN(geo->metadata_size, 4); in set_geometry_for_large_oob()
528 geo->auxiliary_size = ALIGN(geo->metadata_size, 4) in set_geometry_for_large_oob()
529 + ALIGN(geo->ecc_chunk_count, 4); in set_geometry_for_large_oob()
531 if (!this->swap_block_mark) in set_geometry_for_large_oob()
535 i = (mtd->writesize / geo->eccn_chunk_size) - bbm_chunk + 1; in set_geometry_for_large_oob()
537 block_mark_bit_offset = mtd->writesize * 8 - in set_geometry_for_large_oob()
538 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - i) in set_geometry_for_large_oob()
539 + geo->metadata_size * 8); in set_geometry_for_large_oob()
541 geo->block_mark_byte_offset = block_mark_bit_offset / 8; in set_geometry_for_large_oob()
542 geo->block_mark_bit_offset = block_mark_bit_offset % 8; in set_geometry_for_large_oob()
544 dev_dbg(this->dev, "BCH Geometry :\n" in set_geometry_for_large_oob()
559 geo->gf_len, in set_geometry_for_large_oob()
560 geo->ecc_strength, in set_geometry_for_large_oob()
561 geo->page_size, in set_geometry_for_large_oob()
562 geo->metadata_size, in set_geometry_for_large_oob()
563 geo->ecc0_chunk_size, in set_geometry_for_large_oob()
564 geo->eccn_chunk_size, in set_geometry_for_large_oob()
565 geo->ecc_chunk_count, in set_geometry_for_large_oob()
566 geo->payload_size, in set_geometry_for_large_oob()
567 geo->auxiliary_size, in set_geometry_for_large_oob()
568 geo->auxiliary_status_offset, in set_geometry_for_large_oob()
569 geo->block_mark_byte_offset, in set_geometry_for_large_oob()
570 geo->block_mark_bit_offset, in set_geometry_for_large_oob()
572 geo->ecc_for_meta); in set_geometry_for_large_oob()
579 struct bch_geometry *geo = &this->bch_geometry; in legacy_set_geometry()
580 struct mtd_info *mtd = nand_to_mtd(&this->nand); in legacy_set_geometry()
590 geo->metadata_size = 10; in legacy_set_geometry()
593 geo->gf_len = 13; in legacy_set_geometry()
596 geo->ecc0_chunk_size = 512; in legacy_set_geometry()
597 geo->eccn_chunk_size = 512; in legacy_set_geometry()
598 while (geo->eccn_chunk_size < mtd->oobsize) { in legacy_set_geometry()
599 geo->ecc0_chunk_size *= 2; /* keep C >= O */ in legacy_set_geometry()
600 geo->eccn_chunk_size *= 2; /* keep C >= O */ in legacy_set_geometry()
601 geo->gf_len = 14; in legacy_set_geometry()
604 geo->ecc_chunk_count = mtd->writesize / geo->eccn_chunk_size; in legacy_set_geometry()
607 geo->ecc_strength = get_ecc_strength(this); in legacy_set_geometry()
609 dev_err(this->dev, in legacy_set_geometry()
611 "try to use minimum ecc strength that NAND chip required\n", in legacy_set_geometry()
612 geo->ecc_strength, in legacy_set_geometry()
613 this->devdata->bch_max_ecc_strength); in legacy_set_geometry()
614 return -EINVAL; in legacy_set_geometry()
617 geo->page_size = mtd->writesize + geo->metadata_size + in legacy_set_geometry()
618 (geo->gf_len * geo->ecc_strength * geo->ecc_chunk_count) / 8; in legacy_set_geometry()
619 geo->payload_size = mtd->writesize; in legacy_set_geometry()
623 * metadata is padded to the nearest 32-bit boundary. The ECC status in legacy_set_geometry()
624 * contains one byte for every ECC chunk, and is also padded to the in legacy_set_geometry()
625 * nearest 32-bit boundary. in legacy_set_geometry()
627 metadata_size = ALIGN(geo->metadata_size, 4); in legacy_set_geometry()
628 status_size = ALIGN(geo->ecc_chunk_count, 4); in legacy_set_geometry()
630 geo->auxiliary_size = metadata_size + status_size; in legacy_set_geometry()
631 geo->auxiliary_status_offset = metadata_size; in legacy_set_geometry()
633 if (!this->swap_block_mark) in legacy_set_geometry()
638 * the physical block mark within the ECC-based view of the page. in legacy_set_geometry()
640 * NAND chip with 2K page shows below: in legacy_set_geometry()
644 * |<---->| in legacy_set_geometry()
646 * +---+----------+-+----------+-+----------+-+----------+-+ in legacy_set_geometry()
648 * +---+----------+-+----------+-+----------+-+----------+-+ in legacy_set_geometry()
650 * The position of block mark moves forward in the ECC-based view in legacy_set_geometry()
651 * of page, and the delta is: in legacy_set_geometry()
653 * E * G * (N - 1) in legacy_set_geometry()
654 * D = (---------------- + M) in legacy_set_geometry()
658 * : C >= O (C is the ecc chunk size) in legacy_set_geometry()
662 * E * G (O - M) C - M C - M in legacy_set_geometry()
663 * ----------- <= ------- <= -------- < --------- in legacy_set_geometry()
664 * 8 N N (N - 1) in legacy_set_geometry()
668 * E * G * (N - 1) in legacy_set_geometry()
669 * D = (---------------- + M) < C in legacy_set_geometry()
673 * within the ECC-based view of the page is still in the data chunk, in legacy_set_geometry()
677 * physical block mark within the ECC-based view of the page: in legacy_set_geometry()
678 * (page_size - D) * 8 in legacy_set_geometry()
680 * --Huang Shijie in legacy_set_geometry()
682 block_mark_bit_offset = mtd->writesize * 8 - in legacy_set_geometry()
683 (geo->ecc_strength * geo->gf_len * (geo->ecc_chunk_count - 1) in legacy_set_geometry()
684 + geo->metadata_size * 8); in legacy_set_geometry()
686 geo->block_mark_byte_offset = block_mark_bit_offset / 8; in legacy_set_geometry()
687 geo->block_mark_bit_offset = block_mark_bit_offset % 8; in legacy_set_geometry()
693 struct nand_chip *chip = &this->nand; in common_nfc_set_geometry()
694 struct mtd_info *mtd = nand_to_mtd(&this->nand); in common_nfc_set_geometry()
696 nanddev_get_ecc_requirements(&chip->base); in common_nfc_set_geometry()
700 use_minimun_ecc = of_property_read_bool(this->dev->of_node, in common_nfc_set_geometry()
701 "fsl,use-minimum-ecc"); in common_nfc_set_geometry()
704 if ((!use_minimun_ecc && mtd->oobsize < 1024) || in common_nfc_set_geometry()
705 !(requirements->strength > 0 && requirements->step_size > 0)) { in common_nfc_set_geometry()
706 dev_dbg(this->dev, "use legacy bch geometry\n"); in common_nfc_set_geometry()
712 /* for large oob nand */ in common_nfc_set_geometry()
713 if (mtd->oobsize > 1024) { in common_nfc_set_geometry()
714 dev_dbg(this->dev, "use large oob bch geometry\n"); in common_nfc_set_geometry()
720 /* otherwise use the minimum ecc nand chip required */ in common_nfc_set_geometry()
721 dev_dbg(this->dev, "use minimum ecc bch geometry\n"); in common_nfc_set_geometry()
722 err = set_geometry_by_ecc_info(this, requirements->strength, in common_nfc_set_geometry()
723 requirements->step_size); in common_nfc_set_geometry()
725 dev_err(this->dev, "none of the bch geometry setting works\n"); in common_nfc_set_geometry()
733 struct resources *r = &this->resources; in bch_set_geometry()
740 ret = pm_runtime_get_sync(this->dev); in bch_set_geometry()
742 pm_runtime_put_autosuspend(this->dev); in bch_set_geometry()
751 ret = gpmi_reset_block(r->bch_regs, GPMI_IS_MXS(this)); in bch_set_geometry()
756 writel(0, r->bch_regs + HW_BCH_LAYOUTSELECT); in bch_set_geometry()
760 pm_runtime_mark_last_busy(this->dev); in bch_set_geometry()
761 pm_runtime_put_autosuspend(this->dev); in bch_set_geometry()
767 * <1> Firstly, we should know what's the GPMI-clock means.
768 * The GPMI-clock is the internal clock in the gpmi nand controller.
769 * If you set 100MHz to gpmi nand controller, the GPMI-clock's period
770 * is 10ns. Mark the GPMI-clock's period as GPMI-clock-period.
772 * <2> Secondly, we should know what's the frequency on the nand chip pins.
773 * The frequency on the nand chip pins is derived from the GPMI-clock.
778 * F : the frequency on the nand chip pins.
783 * <3> Thirdly, when the frequency on the nand chip pins is above 33MHz,
784 * the nand EDO(extended Data Out) timing could be applied.
786 * The feedback read strobe can be delayed to support the nand EDO timing
787 * where the read strobe may deasserts before the read data is valid, and
788 * read data is valid for some time after read strobe.
790 * The following figure illustrates some aspects of a NAND Flash read:
792 * |<---tREA---->|
795 * |<--tRP-->| |
800 * /---------\
801 * Read Data --------------< >---------
802 * \---------/
804 * |<-D->|
813 * 4.1) From the aspect of the nand chip pins:
814 * Delay = (tREA + C - tRP) {1}
817 * C : a constant to adjust the delay. default is 4000ps.
818 * tRP : the read pulse width, which is exactly:
819 * tRP = (GPMI-clock-period) * DATA_SETUP
821 * 4.2) From the aspect of the GPMI nand controller:
825 * if (GPMI-clock-period > DLL_THRETHOLD)
826 * RP = GPMI-clock-period / 2;
828 * RP = GPMI-clock-period;
830 * Set the HW_GPMI_CTRL1:HALF_PERIOD if GPMI-clock-period
831 * is greater DLL_THRETHOLD. In other SOCs, the DLL_THRETHOLD
832 * is 16000ps, but in mx6q, we use 12000ps.
836 * (tREA + 4000 - tRP) * 8
837 * RDN_DELAY = ----------------------- {3}
843 struct gpmi_nfc_hardware_timing *hw = &this->hw; in gpmi_nfc_compute_timings()
844 struct resources *r = &this->resources; in gpmi_nfc_compute_timings()
845 unsigned int dll_threshold_ps = this->devdata->max_chain_delay; in gpmi_nfc_compute_timings()
856 if (sdr->tRC_min >= 30000) { in gpmi_nfc_compute_timings()
857 /* ONFI non-EDO modes [0-3] */ in gpmi_nfc_compute_timings()
858 hw->clk_rate = 22000000; in gpmi_nfc_compute_timings()
861 } else if (sdr->tRC_min >= 25000) { in gpmi_nfc_compute_timings()
863 hw->clk_rate = 80000000; in gpmi_nfc_compute_timings()
868 hw->clk_rate = 100000000; in gpmi_nfc_compute_timings()
873 clk_rate = clk_round_rate(r->clock[0], hw->clk_rate); in gpmi_nfc_compute_timings()
875 dev_err(this->dev, "clock setting: expected %ld, got %ld\n", in gpmi_nfc_compute_timings()
876 hw->clk_rate, clk_rate); in gpmi_nfc_compute_timings()
877 return -ENOTSUPP; in gpmi_nfc_compute_timings()
880 hw->clk_rate = clk_rate; in gpmi_nfc_compute_timings()
882 period_ps = div_u64((u64)NSEC_PER_SEC * 1000, hw->clk_rate); in gpmi_nfc_compute_timings()
884 addr_setup_cycles = TO_CYCLES(sdr->tALS_min, period_ps); in gpmi_nfc_compute_timings()
885 data_setup_cycles = TO_CYCLES(sdr->tDS_min, period_ps); in gpmi_nfc_compute_timings()
886 data_hold_cycles = TO_CYCLES(sdr->tDH_min, period_ps); in gpmi_nfc_compute_timings()
887 busy_timeout_ps = max(sdr->tBERS_max, sdr->tPROG_max); in gpmi_nfc_compute_timings()
890 hw->timing0 = BF_GPMI_TIMING0_ADDRESS_SETUP(addr_setup_cycles) | in gpmi_nfc_compute_timings()
893 hw->timing1 = BF_GPMI_TIMING1_BUSY_TIMEOUT(DIV_ROUND_UP(busy_timeout_cycles, 4096)); in gpmi_nfc_compute_timings()
898 * (tREA + 4000 - tRP) * 8 in gpmi_nfc_compute_timings()
899 * RDN_DELAY = ----------------------- in gpmi_nfc_compute_timings()
911 sample_delay_ps = (sdr->tREA_max + 4000 - tRP_ps) * 8; in gpmi_nfc_compute_timings()
917 hw->ctrl1n = BF_GPMI_CTRL1_WRN_DLY_SEL(wrn_dly_sel); in gpmi_nfc_compute_timings()
919 hw->ctrl1n |= BF_GPMI_CTRL1_RDN_DELAY(sample_delay_factor) | in gpmi_nfc_compute_timings()
927 struct gpmi_nfc_hardware_timing *hw = &this->hw; in gpmi_nfc_apply_timings()
928 struct resources *r = &this->resources; in gpmi_nfc_apply_timings()
929 void __iomem *gpmi_regs = r->gpmi_regs; in gpmi_nfc_apply_timings()
938 clk_disable_unprepare(r->clock[0]); in gpmi_nfc_apply_timings()
940 ret = clk_set_rate(r->clock[0], hw->clk_rate); in gpmi_nfc_apply_timings()
942 dev_err(this->dev, "cannot set clock rate to %lu Hz: %d\n", hw->clk_rate, ret); in gpmi_nfc_apply_timings()
947 ret = clk_prepare_enable(r->clock[0]); in gpmi_nfc_apply_timings()
952 writel(hw->timing0, gpmi_regs + HW_GPMI_TIMING0); in gpmi_nfc_apply_timings()
953 writel(hw->timing1, gpmi_regs + HW_GPMI_TIMING1); in gpmi_nfc_apply_timings()
960 writel(hw->ctrl1n, gpmi_regs + HW_GPMI_CTRL1_SET); in gpmi_nfc_apply_timings()
963 dll_wait_time_us = USEC_PER_SEC / hw->clk_rate * 64; in gpmi_nfc_apply_timings()
980 /* Retrieve required NAND timings */ in gpmi_setup_interface()
986 if (sdr->tRC_min <= 25000 && !GPMI_IS_MX28(this) && !GPMI_IS_MX6(this)) in gpmi_setup_interface()
987 return -ENOTSUPP; in gpmi_setup_interface()
998 this->hw.must_apply_timings = true; in gpmi_setup_interface()
1006 struct resources *r = &this->resources; in gpmi_clear_bch()
1007 writel(BM_BCH_CTRL_COMPLETE_IRQ, r->bch_regs + HW_BCH_CTRL_CLR); in gpmi_clear_bch()
1012 /* We use the DMA channel 0 to access all the nand chips. */ in get_dma_chan()
1013 return this->dma_chans[0]; in get_dma_chan()
1016 /* This will be called after the DMA operation is finished. */
1020 struct completion *dma_c = &this->dma_done; in dma_irq_callback()
1030 complete(&this->bch_done); in bch_irq()
1037 * raw_len is the length to read/write including bch data which in gpmi_raw_len_to_len()
1040 if (this->bch) in gpmi_raw_len_to_len()
1041 return ALIGN_DOWN(raw_len, this->bch_geometry.eccn_chunk_size); in gpmi_raw_len_to_len()
1057 ret = dma_map_sg(this->dev, sgl, 1, dr); in prepare_data_dma()
1066 sg_init_one(sgl, this->data_buffer_dma, len); in prepare_data_dma()
1068 if (dr == DMA_TO_DEVICE && buf != this->data_buffer_dma) in prepare_data_dma()
1069 memcpy(this->data_buffer_dma, buf, len); in prepare_data_dma()
1071 dma_map_sg(this->dev, sgl, 1, dr); in prepare_data_dma()
1094 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ooblayout_ecc()
1097 return -ERANGE; in gpmi_ooblayout_ecc()
1099 oobregion->offset = 0; in gpmi_ooblayout_ecc()
1100 oobregion->length = geo->page_size - mtd->writesize; in gpmi_ooblayout_ecc()
1110 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ooblayout_free()
1113 return -ERANGE; in gpmi_ooblayout_free()
1116 if (geo->page_size < mtd->writesize + mtd->oobsize) { in gpmi_ooblayout_free()
1117 oobregion->offset = geo->page_size - mtd->writesize; in gpmi_ooblayout_free()
1118 oobregion->length = mtd->oobsize - oobregion->offset; in gpmi_ooblayout_free()
1184 struct platform_device *pdev = this->pdev; in acquire_register_block()
1185 struct resources *res = &this->resources; in acquire_register_block()
1193 res->gpmi_regs = p; in acquire_register_block()
1195 res->bch_regs = p; in acquire_register_block()
1197 dev_err(this->dev, "unknown resource name : %s\n", res_name); in acquire_register_block()
1204 struct platform_device *pdev = this->pdev; in acquire_bch_irq()
1212 err = devm_request_irq(this->dev, err, irq_h, 0, res_name, this); in acquire_bch_irq()
1214 dev_err(this->dev, "error requesting BCH IRQ\n"); in acquire_bch_irq()
1223 if (this->dma_chans[i]) { in release_dma_channels()
1224 dma_release_channel(this->dma_chans[i]); in release_dma_channels()
1225 this->dma_chans[i] = NULL; in release_dma_channels()
1231 struct platform_device *pdev = this->pdev; in acquire_dma_channels()
1236 dma_chan = dma_request_chan(&pdev->dev, "rx-tx"); in acquire_dma_channels()
1238 ret = dev_err_probe(this->dev, PTR_ERR(dma_chan), in acquire_dma_channels()
1242 this->dma_chans[0] = dma_chan; in acquire_dma_channels()
1250 struct resources *r = &this->resources; in gpmi_get_clks()
1254 for (i = 0; i < this->devdata->clks_count; i++) { in gpmi_get_clks()
1255 clk = devm_clk_get(this->dev, this->devdata->clks[i]); in gpmi_get_clks()
1261 r->clock[i] = clk; in gpmi_get_clks()
1267 dev_dbg(this->dev, "failed in finding the clocks.\n"); in gpmi_get_clks()
1309 struct device *dev = this->dev; in gpmi_free_dma_buffer()
1310 struct bch_geometry *geo = &this->bch_geometry; in gpmi_free_dma_buffer()
1312 if (this->auxiliary_virt && virt_addr_valid(this->auxiliary_virt)) in gpmi_free_dma_buffer()
1313 dma_free_coherent(dev, geo->auxiliary_size, in gpmi_free_dma_buffer()
1314 this->auxiliary_virt, in gpmi_free_dma_buffer()
1315 this->auxiliary_phys); in gpmi_free_dma_buffer()
1316 kfree(this->data_buffer_dma); in gpmi_free_dma_buffer()
1317 kfree(this->raw_buffer); in gpmi_free_dma_buffer()
1319 this->data_buffer_dma = NULL; in gpmi_free_dma_buffer()
1320 this->raw_buffer = NULL; in gpmi_free_dma_buffer()
1326 struct bch_geometry *geo = &this->bch_geometry; in gpmi_alloc_dma_buffer()
1327 struct device *dev = this->dev; in gpmi_alloc_dma_buffer()
1328 struct mtd_info *mtd = nand_to_mtd(&this->nand); in gpmi_alloc_dma_buffer()
1334 * is called before the NAND identification; and we allocate a in gpmi_alloc_dma_buffer()
1335 * buffer of the real NAND page size when the gpmi_alloc_dma_buffer in gpmi_alloc_dma_buffer()
1336 * is called after. in gpmi_alloc_dma_buffer()
1338 this->data_buffer_dma = kzalloc(mtd->writesize ?: PAGE_SIZE, in gpmi_alloc_dma_buffer()
1340 if (this->data_buffer_dma == NULL) in gpmi_alloc_dma_buffer()
1343 this->auxiliary_virt = dma_alloc_coherent(dev, geo->auxiliary_size, in gpmi_alloc_dma_buffer()
1344 &this->auxiliary_phys, GFP_DMA); in gpmi_alloc_dma_buffer()
1345 if (!this->auxiliary_virt) in gpmi_alloc_dma_buffer()
1348 this->raw_buffer = kzalloc((mtd->writesize ?: PAGE_SIZE) + mtd->oobsize, GFP_KERNEL); in gpmi_alloc_dma_buffer()
1349 if (!this->raw_buffer) in gpmi_alloc_dma_buffer()
1356 return -ENOMEM; in gpmi_alloc_dma_buffer()
1367 struct bch_geometry *nfc_geo = &this->bch_geometry; in block_mark_swapping()
1375 if (!this->swap_block_mark) in block_mark_swapping()
1382 bit = nfc_geo->block_mark_bit_offset; in block_mark_swapping()
1383 p = payload + nfc_geo->block_mark_byte_offset; in block_mark_swapping()
1392 from_data = (p[0] >> bit) | (p[1] << (8 - bit)); in block_mark_swapping()
1400 mask = (0x1 << bit) - 1; in block_mark_swapping()
1404 p[1] = (p[1] & mask) | (from_oob >> (8 - bit)); in block_mark_swapping()
1411 struct bch_geometry *nfc_geo = &this->bch_geometry; in gpmi_count_bitflips()
1418 status = this->auxiliary_virt + ALIGN(meta, 4); in gpmi_count_bitflips()
1425 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len; in gpmi_count_bitflips()
1426 u8 *eccbuf = this->raw_buffer; in gpmi_count_bitflips()
1432 offset = nfc_geo->metadata_size * 8; in gpmi_count_bitflips()
1433 offset += ((8 * nfc_geo->eccn_chunk_size) + eccbits) * (i + 1); in gpmi_count_bitflips()
1434 offset -= eccbits; in gpmi_count_bitflips()
1438 eccbytes -= offset; in gpmi_count_bitflips()
1444 * in-band data in the first and last byte of in gpmi_count_bitflips()
1445 * eccbuf. Set non-eccbits to one so that in gpmi_count_bitflips()
1450 eccbuf[0] |= GENMASK(bitoffset - 1, 0); in gpmi_count_bitflips()
1454 eccbuf[eccbytes - 1] |= GENMASK(7, bitoffset); in gpmi_count_bitflips()
1459 * nothing was written into this subpage the ECC is in gpmi_count_bitflips()
1463 * ecc_strength bitflips. If this is a page with random in gpmi_count_bitflips()
1470 buf + i * nfc_geo->eccn_chunk_size, in gpmi_count_bitflips()
1471 nfc_geo->eccn_chunk_size, in gpmi_count_bitflips()
1473 this->auxiliary_virt, in gpmi_count_bitflips()
1474 nfc_geo->metadata_size, in gpmi_count_bitflips()
1475 nfc_geo->ecc_strength); in gpmi_count_bitflips()
1478 buf + i * nfc_geo->eccn_chunk_size, in gpmi_count_bitflips()
1479 nfc_geo->eccn_chunk_size, in gpmi_count_bitflips()
1482 nfc_geo->ecc_strength); in gpmi_count_bitflips()
1488 mtd->ecc_stats.corrected += flips; in gpmi_count_bitflips()
1492 mtd->ecc_stats.failed++; in gpmi_count_bitflips()
1496 mtd->ecc_stats.corrected += *status; in gpmi_count_bitflips()
1505 struct bch_geometry *geo = &this->bch_geometry; in gpmi_bch_layout_std()
1506 unsigned int ecc_strength = geo->ecc_strength >> 1; in gpmi_bch_layout_std()
1507 unsigned int gf_len = geo->gf_len; in gpmi_bch_layout_std()
1508 unsigned int block0_size = geo->ecc0_chunk_size; in gpmi_bch_layout_std()
1509 unsigned int blockn_size = geo->eccn_chunk_size; in gpmi_bch_layout_std()
1511 this->bch_flashlayout0 = in gpmi_bch_layout_std()
1512 BF_BCH_FLASH0LAYOUT0_NBLOCKS(geo->ecc_chunk_count - 1) | in gpmi_bch_layout_std()
1513 BF_BCH_FLASH0LAYOUT0_META_SIZE(geo->metadata_size) | in gpmi_bch_layout_std()
1518 this->bch_flashlayout1 = in gpmi_bch_layout_std()
1519 BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(geo->page_size) | in gpmi_bch_layout_std()
1530 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ecc_read_page()
1535 this->bch = true; in gpmi_ecc_read_page()
1537 ret = nand_read_page_op(chip, page, 0, buf, geo->page_size); in gpmi_ecc_read_page()
1542 geo->ecc_chunk_count, in gpmi_ecc_read_page()
1543 geo->auxiliary_status_offset); in gpmi_ecc_read_page()
1546 block_mark_swapping(this, buf, this->auxiliary_virt); in gpmi_ecc_read_page()
1559 memset(chip->oob_poi, ~0, mtd->oobsize); in gpmi_ecc_read_page()
1560 chip->oob_poi[0] = ((uint8_t *)this->auxiliary_virt)[0]; in gpmi_ecc_read_page()
1571 struct bch_geometry *geo = &this->bch_geometry; in gpmi_ecc_read_subpage()
1572 int size = chip->ecc.size; /* ECC chunk size */ in gpmi_ecc_read_subpage()
1582 ecc_parity_size = geo->gf_len * geo->ecc_strength / 8; in gpmi_ecc_read_subpage()
1586 last = (offs + len - 1) / size; in gpmi_ecc_read_subpage()
1588 if (this->swap_block_mark) { in gpmi_ecc_read_subpage()
1591 * If this chunk is in the range of [first, last], in gpmi_ecc_read_subpage()
1594 * Marker to the metadata which is bound with the chunk 0. in gpmi_ecc_read_subpage()
1596 marker_pos = geo->block_mark_byte_offset / size; in gpmi_ecc_read_subpage()
1598 dev_dbg(this->dev, in gpmi_ecc_read_subpage()
1606 * if there is an ECC dedicate for meta: in gpmi_ecc_read_subpage()
1607 * - need to add an extra ECC size when calculating col and page_size, in gpmi_ecc_read_subpage()
1608 * if the meta size is NOT zero. in gpmi_ecc_read_subpage()
1609 * - ecc0_chunk size need to set to the same size as other chunks, in gpmi_ecc_read_subpage()
1610 * if the meta size is zero. in gpmi_ecc_read_subpage()
1613 meta = geo->metadata_size; in gpmi_ecc_read_subpage()
1615 if (geo->ecc_for_meta) in gpmi_ecc_read_subpage()
1625 ecc_parity_size = geo->gf_len * geo->ecc_strength / 8; in gpmi_ecc_read_subpage()
1626 n = last - first + 1; in gpmi_ecc_read_subpage()
1628 if (geo->ecc_for_meta && meta) in gpmi_ecc_read_subpage()
1634 ecc_strength = geo->ecc_strength >> 1; in gpmi_ecc_read_subpage()
1636 this->bch_flashlayout0 = BF_BCH_FLASH0LAYOUT0_NBLOCKS( in gpmi_ecc_read_subpage()
1637 (geo->ecc_for_meta ? n : n - 1)) | in gpmi_ecc_read_subpage()
1640 BF_BCH_FLASH0LAYOUT0_GF(geo->gf_len, this) | in gpmi_ecc_read_subpage()
1641 BF_BCH_FLASH0LAYOUT0_DATA0_SIZE((geo->ecc_for_meta ? in gpmi_ecc_read_subpage()
1642 0 : geo->ecc0_chunk_size), this); in gpmi_ecc_read_subpage()
1644 this->bch_flashlayout1 = BF_BCH_FLASH0LAYOUT1_PAGE_SIZE(page_size) | in gpmi_ecc_read_subpage()
1646 BF_BCH_FLASH0LAYOUT1_GF(geo->gf_len, this) | in gpmi_ecc_read_subpage()
1647 BF_BCH_FLASH0LAYOUT1_DATAN_SIZE(geo->eccn_chunk_size, this); in gpmi_ecc_read_subpage()
1649 this->bch = true; in gpmi_ecc_read_subpage()
1655 dev_dbg(this->dev, "page:%d(%d:%d)%d, chunk:(%d:%d), BCH PG size:%d\n", in gpmi_ecc_read_subpage()
1668 struct bch_geometry *nfc_geo = &this->bch_geometry; in gpmi_ecc_write_page()
1670 dev_dbg(this->dev, "ecc write page.\n"); in gpmi_ecc_write_page()
1673 this->bch = true; in gpmi_ecc_write_page()
1675 memcpy(this->auxiliary_virt, chip->oob_poi, nfc_geo->auxiliary_size); in gpmi_ecc_write_page()
1677 if (this->swap_block_mark) { in gpmi_ecc_write_page()
1682 memcpy(this->data_buffer_dma, buf, mtd->writesize); in gpmi_ecc_write_page()
1683 buf = this->data_buffer_dma; in gpmi_ecc_write_page()
1684 block_mark_swapping(this, this->data_buffer_dma, in gpmi_ecc_write_page()
1685 this->auxiliary_virt); in gpmi_ecc_write_page()
1688 return nand_prog_page_op(chip, page, 0, buf, nfc_geo->page_size); in gpmi_ecc_write_page()
1693 * block marks. This is the function where things are the most complicated, so
1694 * this is where we try to explain it all. All the other places refer back to
1705 * 3) ECC-based read operations return an OOB full of set bits (since we never
1706 * allow ECC-based writes to the OOB, it doesn't matter what ECC-based reads
1717 * 1) Are we doing a "raw" read, or an ECC-based read?
1723 * | Raw | ECC-based |
1724 * -------------+-------------------------+-------------------------+
1730 * -------------+-------------------------+ return it in a buffer |
1738 * -------------+-------------------------+-------------------------+
1745 * It turns out that knowing whether we want an "ECC-based" or "raw" read is not
1746 * easy. When reading a page, for example, the NAND Flash MTD code calls our
1748 * ECC-based or raw view of the page is implicit in which function it calls
1749 * (there is a similar pair of ECC-based/raw functions for writing).
1758 memset(chip->oob_poi, ~0, mtd->oobsize); in gpmi_ecc_read_oob()
1761 ret = nand_read_page_op(chip, page, mtd->writesize, chip->oob_poi, in gpmi_ecc_read_oob()
1762 mtd->oobsize); in gpmi_ecc_read_oob()
1767 * Now, we want to make sure the block mark is correct. In the in gpmi_ecc_read_oob()
1768 * non-transcribing case (!GPMI_IS_MX23()), we already have it. in gpmi_ecc_read_oob()
1773 ret = nand_read_page_op(chip, page, 0, chip->oob_poi, 1); in gpmi_ecc_read_oob()
1789 return -EPERM; in gpmi_ecc_write_oob()
1792 return -EPERM; in gpmi_ecc_write_oob()
1794 return nand_prog_page_op(chip, page, mtd->writesize + of.offset, in gpmi_ecc_write_oob()
1795 chip->oob_poi + of.offset, of.length); in gpmi_ecc_write_oob()
1799 * This function reads a NAND page without involving the ECC engine (no HW
1801 * The tricky part in the GPMI/BCH controller is that it stores ECC bits
1805 * page into the provided buffers, which is why we're using nand_extract_bits().
1815 struct bch_geometry *nfc_geo = &this->bch_geometry; in gpmi_ecc_read_page_raw()
1816 int eccsize = nfc_geo->eccn_chunk_size; in gpmi_ecc_read_page_raw()
1817 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len; in gpmi_ecc_read_page_raw()
1818 u8 *tmp_buf = this->raw_buffer; in gpmi_ecc_read_page_raw()
1822 uint8_t *oob = chip->oob_poi; in gpmi_ecc_read_page_raw()
1827 mtd->writesize + mtd->oobsize); in gpmi_ecc_read_page_raw()
1836 * is needed. in gpmi_ecc_read_page_raw()
1838 if (this->swap_block_mark) in gpmi_ecc_read_page_raw()
1839 swap(tmp_buf[0], tmp_buf[mtd->writesize]); in gpmi_ecc_read_page_raw()
1842 * Copy the metadata section into the oob buffer (this section is in gpmi_ecc_read_page_raw()
1846 memcpy(oob, tmp_buf, nfc_geo->metadata_size); in gpmi_ecc_read_page_raw()
1848 oob_bit_off = nfc_geo->metadata_size * 8; in gpmi_ecc_read_page_raw()
1852 for (step = 0; step < nfc_geo->ecc_chunk_count; step++) { in gpmi_ecc_read_page_raw()
1859 if (step == nfc_geo->ecc_chunk_count - 1 && in gpmi_ecc_read_page_raw()
1861 eccbits += 8 - ((oob_bit_off + eccbits) % 8); in gpmi_ecc_read_page_raw()
1874 if (oob_byte_off < mtd->oobsize) in gpmi_ecc_read_page_raw()
1876 tmp_buf + mtd->writesize + oob_byte_off, in gpmi_ecc_read_page_raw()
1877 mtd->oobsize - oob_byte_off); in gpmi_ecc_read_page_raw()
1884 * This function writes a NAND page without involving the ECC engine (no HW
1886 * The tricky part in the GPMI/BCH controller is that it stores ECC bits
1890 * final page, which is why we're using nand_extract_bits().
1900 struct bch_geometry *nfc_geo = &this->bch_geometry; in gpmi_ecc_write_page_raw()
1901 int eccsize = nfc_geo->eccn_chunk_size; in gpmi_ecc_write_page_raw()
1902 int eccbits = nfc_geo->ecc_strength * nfc_geo->gf_len; in gpmi_ecc_write_page_raw()
1903 u8 *tmp_buf = this->raw_buffer; in gpmi_ecc_write_page_raw()
1904 uint8_t *oob = chip->oob_poi; in gpmi_ecc_write_page_raw()
1916 memset(tmp_buf, 0xff, mtd->writesize + mtd->oobsize); in gpmi_ecc_write_page_raw()
1922 memcpy(tmp_buf, oob, nfc_geo->metadata_size); in gpmi_ecc_write_page_raw()
1923 oob_bit_off = nfc_geo->metadata_size * 8; in gpmi_ecc_write_page_raw()
1927 for (step = 0; step < nfc_geo->ecc_chunk_count; step++) { in gpmi_ecc_write_page_raw()
1934 if (step == nfc_geo->ecc_chunk_count - 1 && in gpmi_ecc_write_page_raw()
1936 eccbits += 8 - ((oob_bit_off + eccbits) % 8); in gpmi_ecc_write_page_raw()
1948 if (oob_required && oob_byte_off < mtd->oobsize) in gpmi_ecc_write_page_raw()
1949 memcpy(tmp_buf + mtd->writesize + oob_byte_off, in gpmi_ecc_write_page_raw()
1950 oob + oob_byte_off, mtd->oobsize - oob_byte_off); in gpmi_ecc_write_page_raw()
1957 * is needed. in gpmi_ecc_write_page_raw()
1959 if (this->swap_block_mark) in gpmi_ecc_write_page_raw()
1960 swap(tmp_buf[0], tmp_buf[mtd->writesize]); in gpmi_ecc_write_page_raw()
1963 mtd->writesize + mtd->oobsize); in gpmi_ecc_write_page_raw()
1984 chipnr = (int)(ofs >> chip->chip_shift); in gpmi_block_markbad()
1987 column = !GPMI_IS_MX23(this) ? mtd->writesize : 0; in gpmi_block_markbad()
1990 block_mark = this->data_buffer_dma; in gpmi_block_markbad()
1994 page = (int)(ofs >> chip->page_shift); in gpmi_block_markbad()
2005 struct boot_rom_geometry *geometry = &this->rom_geometry; in nand_boot_set_geometry()
2008 * Set the boot block stride size. in nand_boot_set_geometry()
2011 * that's where the ROM is going to get it. In fact, we don't have any in nand_boot_set_geometry()
2015 geometry->stride_size_in_pages = 64; in nand_boot_set_geometry()
2021 * that's where the ROM is going to get it. In fact, we don't have any in nand_boot_set_geometry()
2025 geometry->search_area_stride_exponent = 2; in nand_boot_set_geometry()
2032 struct boot_rom_geometry *rom_geo = &this->rom_geometry; in mx23_check_transcription_stamp()
2033 struct device *dev = this->dev; in mx23_check_transcription_stamp()
2034 struct nand_chip *chip = &this->nand; in mx23_check_transcription_stamp()
2043 search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent; in mx23_check_transcription_stamp()
2054 page = stride * rom_geo->stride_size_in_pages; in mx23_check_transcription_stamp()
2059 * Read the NCB fingerprint. The fingerprint is four bytes long in mx23_check_transcription_stamp()
2087 struct device *dev = this->dev; in mx23_write_transcription_stamp()
2088 struct boot_rom_geometry *rom_geo = &this->rom_geometry; in mx23_write_transcription_stamp()
2089 struct nand_chip *chip = &this->nand; in mx23_write_transcription_stamp()
2102 block_size_in_pages = mtd->erasesize / mtd->writesize; in mx23_write_transcription_stamp()
2103 search_area_size_in_strides = 1 << rom_geo->search_area_stride_exponent; in mx23_write_transcription_stamp()
2105 rom_geo->stride_size_in_pages; in mx23_write_transcription_stamp()
2107 (search_area_size_in_pages + (block_size_in_pages - 1)) / in mx23_write_transcription_stamp()
2129 memset(buffer, ~0, mtd->writesize); in mx23_write_transcription_stamp()
2136 page = stride * rom_geo->stride_size_in_pages; in mx23_write_transcription_stamp()
2141 status = chip->ecc.write_page_raw(chip, buffer, 0, page); in mx23_write_transcription_stamp()
2153 struct device *dev = this->dev; in mx23_boot_init()
2154 struct nand_chip *chip = &this->nand; in mx23_boot_init()
2168 * anything -- the block marks are already transcribed. in mx23_boot_init()
2179 /* Compute the number of blocks in the entire medium. */ in mx23_boot_init()
2180 block_count = nanddev_eraseblocks_per_target(&chip->base); in mx23_boot_init()
2183 * Loop over all the blocks in the medium, transcribing block marks as in mx23_boot_init()
2191 chipnr = block >> (chip->chip_shift - chip->phys_erase_shift); in mx23_boot_init()
2192 page = block << (chip->phys_erase_shift - chip->page_shift); in mx23_boot_init()
2193 byte = block << chip->phys_erase_shift; in mx23_boot_init()
2197 ret = nand_read_page_op(chip, page, mtd->writesize, &block_mark, in mx23_boot_init()
2205 * Check if the block is marked bad. If so, we need to mark it in mx23_boot_init()
2211 ret = chip->legacy.block_markbad(chip, byte); in mx23_boot_init()
2228 /* This is ROM arch-specific initilization before the BBT scanning. */ in nand_boot_init()
2241 /* Set up the NFC geometry which is used by BCH. */ in gpmi_set_geometry()
2244 dev_err(this->dev, "Error setting BCH geometry : %d\n", ret); in gpmi_set_geometry()
2254 struct nand_chip *chip = &this->nand; in gpmi_init_last()
2256 struct nand_ecc_ctrl *ecc = &chip->ecc; in gpmi_init_last()
2257 struct bch_geometry *bch_geo = &this->bch_geometry; in gpmi_init_last()
2260 /* Set up the medium geometry */ in gpmi_init_last()
2266 ecc->read_page = gpmi_ecc_read_page; in gpmi_init_last()
2267 ecc->write_page = gpmi_ecc_write_page; in gpmi_init_last()
2268 ecc->read_oob = gpmi_ecc_read_oob; in gpmi_init_last()
2269 ecc->write_oob = gpmi_ecc_write_oob; in gpmi_init_last()
2270 ecc->read_page_raw = gpmi_ecc_read_page_raw; in gpmi_init_last()
2271 ecc->write_page_raw = gpmi_ecc_write_page_raw; in gpmi_init_last()
2272 ecc->read_oob_raw = gpmi_ecc_read_oob_raw; in gpmi_init_last()
2273 ecc->write_oob_raw = gpmi_ecc_write_oob_raw; in gpmi_init_last()
2274 ecc->engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST; in gpmi_init_last()
2275 ecc->size = bch_geo->eccn_chunk_size; in gpmi_init_last()
2276 ecc->strength = bch_geo->ecc_strength; in gpmi_init_last()
2281 * (1) the chip is imx6, and in gpmi_init_last()
2282 * (2) the size of the ECC parity is byte aligned. in gpmi_init_last()
2285 ((bch_geo->gf_len * bch_geo->ecc_strength) % 8) == 0) { in gpmi_init_last()
2286 ecc->read_subpage = gpmi_ecc_read_subpage; in gpmi_init_last()
2287 chip->options |= NAND_SUBPAGE_READ; in gpmi_init_last()
2298 if (chip->bbt_options & NAND_BBT_USE_FLASH) { in gpmi_nand_attach_chip()
2299 chip->bbt_options |= NAND_BBT_NO_OOB; in gpmi_nand_attach_chip()
2301 if (of_property_read_bool(this->dev->of_node, in gpmi_nand_attach_chip()
2302 "fsl,no-blockmark-swap")) in gpmi_nand_attach_chip()
2303 this->swap_block_mark = false; in gpmi_nand_attach_chip()
2305 dev_dbg(this->dev, "Blockmark swapping %sabled\n", in gpmi_nand_attach_chip()
2306 this->swap_block_mark ? "en" : "dis"); in gpmi_nand_attach_chip()
2312 chip->options |= NAND_SKIP_BBTSCAN; in gpmi_nand_attach_chip()
2319 struct gpmi_transfer *transfer = &this->transfers[this->ntransfers]; in get_next_transfer()
2321 this->ntransfers++; in get_next_transfer()
2323 if (this->ntransfers == GPMI_MAX_TRANSFERS) in get_next_transfer()
2335 int chip = this->nand.cur_cs; in gpmi_chain_command()
2357 transfer->cmdbuf[0] = cmd; in gpmi_chain_command()
2359 memcpy(&transfer->cmdbuf[1], addr, naddr); in gpmi_chain_command()
2361 sg_init_one(&transfer->sgl, transfer->cmdbuf, naddr + 1); in gpmi_chain_command()
2362 dma_map_sg(this->dev, &transfer->sgl, 1, DMA_TO_DEVICE); in gpmi_chain_command()
2364 transfer->direction = DMA_TO_DEVICE; in gpmi_chain_command()
2366 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1, DMA_MEM_TO_DEV, in gpmi_chain_command()
2379 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this) in gpmi_chain_wait_ready()
2401 transfer->direction = DMA_FROM_DEVICE; in gpmi_chain_data_read()
2403 *direct = prepare_data_dma(this, buf, raw_len, &transfer->sgl, in gpmi_chain_data_read()
2408 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this) in gpmi_chain_data_read()
2413 if (this->bch) { in gpmi_chain_data_read()
2419 pio[4] = transfer->sgl.dma_address; in gpmi_chain_data_read()
2420 pio[5] = this->auxiliary_phys; in gpmi_chain_data_read()
2428 if (!this->bch) in gpmi_chain_data_read()
2429 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1, in gpmi_chain_data_read()
2448 transfer->direction = DMA_TO_DEVICE; in gpmi_chain_data_write()
2450 prepare_data_dma(this, buf, raw_len, &transfer->sgl, DMA_TO_DEVICE); in gpmi_chain_data_write()
2454 | BF_GPMI_CTRL0_CS(this->nand.cur_cs, this) in gpmi_chain_data_write()
2459 if (this->bch) { in gpmi_chain_data_write()
2465 pio[4] = transfer->sgl.dma_address; in gpmi_chain_data_write()
2466 pio[5] = this->auxiliary_phys; in gpmi_chain_data_write()
2471 (this->bch ? MXS_DMA_CTRL_WAIT4END : 0)); in gpmi_chain_data_write()
2475 if (!this->bch) in gpmi_chain_data_write()
2476 desc = dmaengine_prep_slave_sg(channel, &transfer->sgl, 1, in gpmi_chain_data_write()
2501 this->ntransfers = 0; in gpmi_nfc_exec_op()
2503 this->transfers[i].direction = DMA_NONE; in gpmi_nfc_exec_op()
2505 ret = pm_runtime_resume_and_get(this->dev); in gpmi_nfc_exec_op()
2510 * This driver currently supports only one NAND chip. Plus, dies share in gpmi_nfc_exec_op()
2515 if (this->hw.must_apply_timings) { in gpmi_nfc_exec_op()
2516 this->hw.must_apply_timings = false; in gpmi_nfc_exec_op()
2522 dev_dbg(this->dev, "%s: %d instructions\n", __func__, op->ninstrs); in gpmi_nfc_exec_op()
2524 for (i = 0; i < op->ninstrs; i++) { in gpmi_nfc_exec_op()
2525 instr = &op->instrs[i]; in gpmi_nfc_exec_op()
2529 switch (instr->type) { in gpmi_nfc_exec_op()
2534 cmd = instr->ctx.cmd.opcode; in gpmi_nfc_exec_op()
2540 if (i + 1 != op->ninstrs && in gpmi_nfc_exec_op()
2541 op->instrs[i + 1].type == NAND_OP_ADDR_INSTR) in gpmi_nfc_exec_op()
2548 desc = gpmi_chain_command(this, cmd, instr->ctx.addr.addrs, in gpmi_nfc_exec_op()
2549 instr->ctx.addr.naddrs); in gpmi_nfc_exec_op()
2552 buf_write = instr->ctx.data.buf.out; in gpmi_nfc_exec_op()
2553 buf_len = instr->ctx.data.len; in gpmi_nfc_exec_op()
2560 if (!instr->ctx.data.len) in gpmi_nfc_exec_op()
2562 buf_read = instr->ctx.data.buf.in; in gpmi_nfc_exec_op()
2563 buf_len = instr->ctx.data.len; in gpmi_nfc_exec_op()
2572 ret = -ENXIO; in gpmi_nfc_exec_op()
2577 dev_dbg(this->dev, "%s setup done\n", __func__); in gpmi_nfc_exec_op()
2580 dev_err(this->dev, "Multiple data instructions not supported\n"); in gpmi_nfc_exec_op()
2581 ret = -EINVAL; in gpmi_nfc_exec_op()
2585 if (this->bch) { in gpmi_nfc_exec_op()
2586 writel(this->bch_flashlayout0, in gpmi_nfc_exec_op()
2587 this->resources.bch_regs + HW_BCH_FLASH0LAYOUT0); in gpmi_nfc_exec_op()
2588 writel(this->bch_flashlayout1, in gpmi_nfc_exec_op()
2589 this->resources.bch_regs + HW_BCH_FLASH0LAYOUT1); in gpmi_nfc_exec_op()
2592 desc->callback = dma_irq_callback; in gpmi_nfc_exec_op()
2593 desc->callback_param = this; in gpmi_nfc_exec_op()
2594 dma_completion = &this->dma_done; in gpmi_nfc_exec_op()
2599 if (this->bch && buf_read) { in gpmi_nfc_exec_op()
2601 this->resources.bch_regs + HW_BCH_CTRL_SET); in gpmi_nfc_exec_op()
2602 bch_completion = &this->bch_done; in gpmi_nfc_exec_op()
2611 dev_err(this->dev, "DMA timeout, last DMA\n"); in gpmi_nfc_exec_op()
2613 ret = -ETIMEDOUT; in gpmi_nfc_exec_op()
2617 if (this->bch && buf_read) { in gpmi_nfc_exec_op()
2620 dev_err(this->dev, "BCH timeout, last DMA\n"); in gpmi_nfc_exec_op()
2622 ret = -ETIMEDOUT; in gpmi_nfc_exec_op()
2628 this->resources.bch_regs + HW_BCH_CTRL_CLR); in gpmi_nfc_exec_op()
2634 for (i = 0; i < this->ntransfers; i++) { in gpmi_nfc_exec_op()
2635 struct gpmi_transfer *transfer = &this->transfers[i]; in gpmi_nfc_exec_op()
2637 if (transfer->direction != DMA_NONE) in gpmi_nfc_exec_op()
2638 dma_unmap_sg(this->dev, &transfer->sgl, 1, in gpmi_nfc_exec_op()
2639 transfer->direction); in gpmi_nfc_exec_op()
2643 memcpy(buf_read, this->data_buffer_dma, in gpmi_nfc_exec_op()
2646 this->bch = false; in gpmi_nfc_exec_op()
2649 pm_runtime_mark_last_busy(this->dev); in gpmi_nfc_exec_op()
2650 pm_runtime_put_autosuspend(this->dev); in gpmi_nfc_exec_op()
2663 struct nand_chip *chip = &this->nand; in gpmi_nand_init()
2668 mtd->name = "gpmi-nand"; in gpmi_nand_init()
2669 mtd->dev.parent = this->dev; in gpmi_nand_init()
2671 /* init the nand_chip{}, we don't support a 16-bit NAND Flash bus. */ in gpmi_nand_init()
2673 nand_set_flash_node(chip, this->pdev->dev.of_node); in gpmi_nand_init()
2674 chip->legacy.block_markbad = gpmi_block_markbad; in gpmi_nand_init()
2675 chip->badblock_pattern = &gpmi_bbt_descr; in gpmi_nand_init()
2676 chip->options |= NAND_NO_SUBPAGE_WRITE; in gpmi_nand_init()
2679 this->swap_block_mark = !GPMI_IS_MX23(this); in gpmi_nand_init()
2685 this->bch_geometry.payload_size = 1024; in gpmi_nand_init()
2686 this->bch_geometry.auxiliary_size = 128; in gpmi_nand_init()
2691 nand_controller_init(&this->base); in gpmi_nand_init()
2692 this->base.ops = &gpmi_nand_controller_ops; in gpmi_nand_init()
2693 chip->controller = &this->base; in gpmi_nand_init()
2719 { .compatible = "fsl,imx23-gpmi-nand", .data = &gpmi_devdata_imx23, },
2720 { .compatible = "fsl,imx28-gpmi-nand", .data = &gpmi_devdata_imx28, },
2721 { .compatible = "fsl,imx6q-gpmi-nand", .data = &gpmi_devdata_imx6q, },
2722 { .compatible = "fsl,imx6sx-gpmi-nand", .data = &gpmi_devdata_imx6sx, },
2723 { .compatible = "fsl,imx7d-gpmi-nand", .data = &gpmi_devdata_imx7d,},
2733 this = devm_kzalloc(&pdev->dev, sizeof(*this), GFP_KERNEL); in gpmi_nand_probe()
2735 return -ENOMEM; in gpmi_nand_probe()
2737 this->devdata = of_device_get_match_data(&pdev->dev); in gpmi_nand_probe()
2739 this->pdev = pdev; in gpmi_nand_probe()
2740 this->dev = &pdev->dev; in gpmi_nand_probe()
2750 pm_runtime_set_autosuspend_delay(&pdev->dev, 500); in gpmi_nand_probe()
2751 pm_runtime_use_autosuspend(&pdev->dev); in gpmi_nand_probe()
2752 pm_runtime_set_active(&pdev->dev); in gpmi_nand_probe()
2753 pm_runtime_enable(&pdev->dev); in gpmi_nand_probe()
2754 pm_runtime_get_sync(&pdev->dev); in gpmi_nand_probe()
2764 pm_runtime_mark_last_busy(&pdev->dev); in gpmi_nand_probe()
2765 pm_runtime_put_autosuspend(&pdev->dev); in gpmi_nand_probe()
2767 dev_info(this->dev, "driver registered.\n"); in gpmi_nand_probe()
2772 pm_runtime_put(&pdev->dev); in gpmi_nand_probe()
2773 pm_runtime_disable(&pdev->dev); in gpmi_nand_probe()
2783 struct nand_chip *chip = &this->nand; in gpmi_nand_remove()
2786 pm_runtime_put_sync(&pdev->dev); in gpmi_nand_remove()
2787 pm_runtime_disable(&pdev->dev); in gpmi_nand_remove()
2814 /* re-init the GPMI registers */ in gpmi_pm_resume()
2817 dev_err(this->dev, "Error setting GPMI : %d\n", ret); in gpmi_pm_resume()
2822 if (this->hw.clk_rate) in gpmi_pm_resume()
2823 this->hw.must_apply_timings = true; in gpmi_pm_resume()
2825 /* re-init the BCH registers */ in gpmi_pm_resume()
2828 dev_err(this->dev, "Error setting BCH : %d\n", ret); in gpmi_pm_resume()
2857 .name = "gpmi-nand",
2867 MODULE_DESCRIPTION("i.MX GPMI NAND Flash Controller Driver");