Lines Matching full:ecc

32  * The 1-bit ECC hardware is supported, as well as the newer 4-bit ECC
84 * 1-bit hardware ECC ... context maintained for each core chipselect
103 /* Reset ECC hardware */ in nand_davinci_hwctl_1bit()
108 /* Restart ECC hardware */ in nand_davinci_hwctl_1bit()
117 * Read hardware ECC value and pack into three bytes
125 /* invert so that erased block ecc is correct */ in nand_davinci_calculate_1bit()
146 if ((diff >> (12 + 3)) < chip->ecc.size) { in nand_davinci_correct_1bit()
153 /* Single bit ECC error in the ECC itself, in nand_davinci_correct_1bit()
168 * 4-bit hardware ECC ... context maintained over entire AEMIF
173 * Also, and specific to this hardware, it ECC-protects the "prepad"
174 * in the OOB ... while having ECC protection for parts of OOB would
176 * OOB without recomputing ECC.
185 /* Reset ECC hardware */ in nand_davinci_hwctl_4bit()
190 /* Start 4-bit ECC calculation for read/write */ in nand_davinci_hwctl_4bit()
201 /* Read raw ECC code after writing to NAND. */
213 /* Terminate read ECC; or return ECC (as bytes) of data written to NAND. */
221 /* After a read, terminate ECC calculation by a dummy read in nand_davinci_calculate_4bit()
222 * of some 4-bit ECC register. ECC covers everything that in nand_davinci_calculate_4bit()
231 /* Pack eight raw 10-bit ecc values into ten bytes, making in nand_davinci_calculate_4bit()
279 /* Tell ECC controller about the expected ECC codes. */ in nand_davinci_correct_4bit()
310 * long as ECC_STATE reads less than 4. After that, ECC HW has entered in nand_davinci_correct_4bit()
375 /* An ECC layout for using 4-bit ECC with small-page flash, storing
376 * ten ECC bytes plus the manufacturer's bad block marker byte, and
417 .ecc = hwecc4_ooblayout_small_ecc,
459 "ti,davinci-ecc-mode", &mode)) { in nand_davinci_get_pdata()
468 "ti,davinci-ecc-bits", &prop)) in nand_davinci_get_pdata()
481 * use of 4-bit hardware ECC with subpages and verified on in nand_davinci_get_pdata()
516 /* Use board-specific ECC config */ in davinci_nand_attach_chip()
517 chip->ecc.engine_type = pdata->engine_type; in davinci_nand_attach_chip()
518 chip->ecc.placement = pdata->ecc_placement; in davinci_nand_attach_chip()
520 switch (chip->ecc.engine_type) { in davinci_nand_attach_chip()
527 * This driver expects Hamming based ECC when engine_type is set in davinci_nand_attach_chip()
528 * to NAND_ECC_ENGINE_TYPE_SOFT. Force ecc.algo to in davinci_nand_attach_chip()
532 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in davinci_nand_attach_chip()
559 chip->ecc.calculate = nand_davinci_calculate_4bit; in davinci_nand_attach_chip()
560 chip->ecc.correct = nand_davinci_correct_4bit; in davinci_nand_attach_chip()
561 chip->ecc.hwctl = nand_davinci_hwctl_4bit; in davinci_nand_attach_chip()
562 chip->ecc.bytes = 10; in davinci_nand_attach_chip()
563 chip->ecc.options = NAND_ECC_GENERIC_ERASED_CHECK; in davinci_nand_attach_chip()
564 chip->ecc.algo = NAND_ECC_ALGO_BCH; in davinci_nand_attach_chip()
567 * Update ECC layout if needed ... for 1-bit HW ECC, the in davinci_nand_attach_chip()
569 * are needed (for each 512 bytes). For 4-bit HW ECC, in davinci_nand_attach_chip()
582 chip->ecc.read_page = nand_read_page_hwecc_oob_first; in davinci_nand_attach_chip()
587 /* 1bit ecc hamming */ in davinci_nand_attach_chip()
588 chip->ecc.calculate = nand_davinci_calculate_1bit; in davinci_nand_attach_chip()
589 chip->ecc.correct = nand_davinci_correct_1bit; in davinci_nand_attach_chip()
590 chip->ecc.hwctl = nand_davinci_hwctl_1bit; in davinci_nand_attach_chip()
591 chip->ecc.bytes = 3; in davinci_nand_attach_chip()
592 chip->ecc.algo = NAND_ECC_ALGO_HAMMING; in davinci_nand_attach_chip()
594 chip->ecc.size = 512; in davinci_nand_attach_chip()
595 chip->ecc.strength = pdata->ecc_bits; in davinci_nand_attach_chip()
830 if (chip->ecc.placement == NAND_ECC_PLACEMENT_INTERLEAVED) in nand_davinci_remove()