Lines Matching +full:phy +full:- +full:dll +full:- +full:delay +full:- +full:strobe
1 // SPDX-License-Identifier: GPL-2.0
3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs
5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com
18 #include "sdhci-cqhci.h"
19 #include "sdhci-pltfm.h"
29 /* PHY Registers */
88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1
107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy",
108 "ti,itap-del-sel-legacy",
110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs",
111 "ti,itap-del-sel-mmc-hs",
113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs",
114 "ti,itap-del-sel-sd-hs",
116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12",
117 "ti,itap-del-sel-sdr12",
119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25",
120 "ti,itap-del-sel-sdr25",
122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50",
125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104",
128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50",
131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52",
132 "ti,itap-del-sel-ddr52",
134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200",
137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400",
174 /* Disable delay chain mode */ in sdhci_am654_setup_dll()
175 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, in sdhci_am654_setup_dll()
178 if (sdhci_am654->flags & FREQSEL_2_BIT) { in sdhci_am654_setup_dll()
193 /* Configure PHY DLL frequency */ in sdhci_am654_setup_dll()
196 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); in sdhci_am654_setup_dll()
207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, in sdhci_am654_setup_dll()
210 /* Configure DLL TRIM */ in sdhci_am654_setup_dll()
212 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; in sdhci_am654_setup_dll()
214 /* Configure DLL driver strength */ in sdhci_am654_setup_dll()
216 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; in sdhci_am654_setup_dll()
217 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); in sdhci_am654_setup_dll()
219 /* Enable DLL */ in sdhci_am654_setup_dll()
220 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, in sdhci_am654_setup_dll()
223 * Poll for DLL ready. Use a one second timeout. in sdhci_am654_setup_dll()
226 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, in sdhci_am654_setup_dll()
229 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); in sdhci_am654_setup_dll()
238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, in sdhci_am654_write_itapdly()
240 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, in sdhci_am654_write_itapdly()
242 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); in sdhci_am654_write_itapdly()
250 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); in sdhci_am654_setup_delay_chain()
254 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); in sdhci_am654_setup_delay_chain()
257 sdhci_am654->itap_del_sel[timing]); in sdhci_am654_setup_delay_chain()
264 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_set_clock()
269 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); in sdhci_am654_set_clock()
273 /* Setup DLL Output TAP delay */ in sdhci_am654_set_clock()
274 otap_del_sel = sdhci_am654->otap_del_sel[timing]; in sdhci_am654_set_clock()
283 if (sdhci_am654->flags & STRBSEL_4_BIT) in sdhci_am654_set_clock()
288 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; in sdhci_am654_set_clock()
291 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); in sdhci_am654_set_clock()
298 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, in sdhci_am654_set_clock()
299 sdhci_am654->clkbuf_sel); in sdhci_am654_set_clock()
307 unsigned char timing = host->mmc->ios.timing; in sdhci_j721e_4bit_set_clock()
311 /* Setup DLL Output TAP delay */ in sdhci_j721e_4bit_set_clock()
312 otap_del_sel = sdhci_am654->otap_del_sel[timing]; in sdhci_j721e_4bit_set_clock()
317 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); in sdhci_j721e_4bit_set_clock()
319 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, in sdhci_j721e_4bit_set_clock()
320 sdhci_am654->clkbuf_sel); in sdhci_j721e_4bit_set_clock()
327 writeb(val, host->ioaddr + reg); in sdhci_am654_write_power_on()
329 return readb(host->ioaddr + reg); in sdhci_am654_write_power_on()
335 unsigned char timing = host->mmc->ios.timing; in sdhci_am654_write_b()
351 writeb(val, host->ioaddr + reg); in sdhci_am654_write_b()
363 dev_info(mmc_dev(host->mmc), "Power on failed\n"); in sdhci_am654_write_b()
375 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { in sdhci_am654_reset()
406 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_am654_cqhci_irq()
421 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, in sdhci_am654_platform_execute_tuning()
427 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); in sdhci_am654_platform_execute_tuning()
442 pass_len = ITAP_MAX - fail_len; in sdhci_am654_platform_execute_tuning()
550 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), in sdhci_am654_cqe_add_host()
553 return -ENOMEM; in sdhci_am654_cqe_add_host()
555 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; in sdhci_am654_cqe_add_host()
556 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; in sdhci_am654_cqe_add_host()
557 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_am654_cqe_add_host()
558 cq_host->ops = &sdhci_am654_cqhci_ops; in sdhci_am654_cqe_add_host()
560 host->mmc->caps2 |= MMC_CAP2_CQE; in sdhci_am654_cqe_add_host()
562 return cqhci_init(cq_host, host->mmc, 1); in sdhci_am654_cqe_add_host()
568 struct device *dev = mmc_dev(host->mmc); in sdhci_am654_get_otap_delay()
575 &sdhci_am654->otap_del_sel[i]); in sdhci_am654_get_otap_delay()
578 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n"); in sdhci_am654_get_otap_delay()
585 * if an otap-del-sel value is not found in sdhci_am654_get_otap_delay()
588 host->mmc->caps &= ~td[i].capability; in sdhci_am654_get_otap_delay()
590 host->mmc->caps2 &= ~td[i].capability; in sdhci_am654_get_otap_delay()
595 &sdhci_am654->itap_del_sel[i]); in sdhci_am654_get_otap_delay()
612 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); in sdhci_am654_init()
614 if (sdhci_am654->flags & DLL_CALIB) { in sdhci_am654_init()
615 regmap_read(sdhci_am654->base, PHY_STAT1, &val); in sdhci_am654_init()
618 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_init()
620 ret = regmap_read_poll_timeout(sdhci_am654->base, in sdhci_am654_init()
630 if (sdhci_am654->flags & IOMUX_PRESENT) in sdhci_am654_init()
631 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_init()
635 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_am654_init()
638 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, in sdhci_am654_init()
642 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, in sdhci_am654_init()
671 struct device *dev = &pdev->dev; in sdhci_am654_get_of_property()
675 if (sdhci_am654->flags & DLL_PRESENT) { in sdhci_am654_get_of_property()
676 ret = device_property_read_u32(dev, "ti,trm-icp", in sdhci_am654_get_of_property()
677 &sdhci_am654->trm_icp); in sdhci_am654_get_of_property()
681 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", in sdhci_am654_get_of_property()
688 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; in sdhci_am654_get_of_property()
691 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; in sdhci_am654_get_of_property()
694 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; in sdhci_am654_get_of_property()
697 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; in sdhci_am654_get_of_property()
700 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; in sdhci_am654_get_of_property()
704 return -EINVAL; in sdhci_am654_get_of_property()
708 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); in sdhci_am654_get_of_property()
709 device_property_read_u32(dev, "ti,clkbuf-sel", in sdhci_am654_get_of_property()
710 &sdhci_am654->clkbuf_sel); in sdhci_am654_get_of_property()
712 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) in sdhci_am654_get_of_property()
713 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; in sdhci_am654_get_of_property()
722 .compatible = "ti,am654-sdhci-5.1",
726 .compatible = "ti,j721e-sdhci-8bit",
730 .compatible = "ti,j721e-sdhci-4bit",
734 .compatible = "ti,am64-sdhci-8bit",
738 .compatible = "ti,am64-sdhci-4bit",
742 .compatible = "ti,am62-sdhci",
758 struct device *dev = &pdev->dev; in sdhci_am654_probe()
762 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); in sdhci_am654_probe()
763 drvdata = match->data; in sdhci_am654_probe()
767 if (soc && soc->data) in sdhci_am654_probe()
768 drvdata = soc->data; in sdhci_am654_probe()
770 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); in sdhci_am654_probe()
776 sdhci_am654->flags = drvdata->flags; in sdhci_am654_probe()
785 pltfm_host->clk = clk_xin; in sdhci_am654_probe()
793 sdhci_am654->base = devm_regmap_init_mmio(dev, base, in sdhci_am654_probe()
795 if (IS_ERR(sdhci_am654->base)) { in sdhci_am654_probe()
797 ret = PTR_ERR(sdhci_am654->base); in sdhci_am654_probe()
805 ret = mmc_of_parse(host->mmc); in sdhci_am654_probe()
811 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; in sdhci_am654_probe()
818 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_am654_probe()
834 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_probe()
848 struct device *dev = &pdev->dev; in sdhci_am654_remove()
856 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_remove()
871 if (sdhci_am654->flags & DLL_CALIB) { in sdhci_am654_restore()
872 regmap_read(sdhci_am654->base, PHY_STAT1, &val); in sdhci_am654_restore()
875 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_restore()
877 ret = regmap_read_poll_timeout(sdhci_am654->base, in sdhci_am654_restore()
887 if (sdhci_am654->flags & IOMUX_PRESENT) in sdhci_am654_restore()
888 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, in sdhci_am654_restore()
892 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) in sdhci_am654_restore()
895 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, in sdhci_am654_restore()
898 regmap_read(sdhci_am654->base, CTL_CFG_3, &val); in sdhci_am654_restore()
901 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, in sdhci_am654_restore()
913 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_am654_runtime_suspend()
914 mmc_retune_needed(host->mmc); in sdhci_am654_runtime_suspend()
916 ret = cqhci_suspend(host->mmc); in sdhci_am654_runtime_suspend()
925 clk_disable_unprepare(pltfm_host->clk); in sdhci_am654_runtime_suspend()
936 ret = clk_prepare_enable(pltfm_host->clk); in sdhci_am654_runtime_resume()
948 ret = cqhci_resume(host->mmc); in sdhci_am654_runtime_resume()
965 .name = "sdhci-am654",