Lines Matching +full:hs200 +full:- +full:cmd +full:- +full:int +full:- +full:delay
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * linux/drivers/mmc/host/sdhci.h - Secure Digital Host Controller Interface driver
7 * Copyright (C) 2005-2008 Pierre Ossman, All Rights Reserved.
103 * VDD2 - UHS2 or PCIe/NVMe
173 #define SDHCI_INT_ALL_MASK ((unsigned int)-1)
195 #define SDHCI_CTRL_HS400 0x0005 /* Non-standard */
242 #define SDHCI_SUPPORT_HS400 0x80000000 /* Non-standard */
251 /* 4C-4F reserved for more max current */
258 /* 55-57 reserved */
263 /* 60-FB reserved */
271 #define SDHCI_PRESET_FOR_HS400 0x74 /* Non-standard */
301 #define SDHCI_DEFAULT_BOUNDARY_ARG (ilog2(SDHCI_DEFAULT_BOUNDARY_SIZE) - 12)
303 /* ADMA2 32-bit DMA descriptor size */
306 /* ADMA2 32-bit descriptor */
308 __le16 cmd; member
315 #define SDHCI_ADMA2_MASK (SDHCI_ADMA2_ALIGN - 1)
319 * alignment for the descriptor table even in 32-bit DMA mode. Memory
325 * ADMA2 64-bit DMA descriptor size
327 * descriptors for 64-bit addressing mode: 96-bit Descriptor and 128-bit
329 * register, 128-bit Descriptor will be selected.
331 #define SDHCI_ADMA2_64_DESC_SZ(host) ((host)->v4_mode ? 16 : 12)
334 * ADMA2 64-bit descriptor. Note 12-byte descriptor can't always be 8-byte
338 __le16 cmd; member
367 mmc_debugfs_err_stats_inc((host)->mmc, MMC_ERR_##err_name)
379 unsigned int quirks; /* Deviations from spec. */
393 /* Controller can only DMA from 32-bit aligned addresses */
407 /* Controller does not provide transfer-complete interrupt when not busy */
411 /* Controller reports inverted write-protect state */
421 /* Controller cannot do multi-block transfers */
423 /* Controller can only handle 1-bit data transfers */
425 /* Controller needs 10ms delay between applying power and clock */
435 /* Controller doesn't have HISPD bit field in HI-SPEED SD card */
439 /* The read-only detection via SDHCI_PRESENT_STATE register is unstable */
442 unsigned int quirks2; /* More deviations from spec. */
450 /* Controller has a non-standard host control register */
452 /* Controller does not support HS200 */
458 /* Controller does not support 64-bit DMA */
460 /* need clear transfer mode register before send cmd */
462 /* Capability register bit-63 indicates HS400 support */
480 * 32-bit block count may not support eMMC where upper bits of CMD23 are used
481 * for other purposes. Consequently we support 16-bit block count by default.
482 * Otherwise, SDHCI_QUIRK2_USE_32BIT_BLK_CNT can be selected to use 32-bit
486 /* Issue CMD and DATA reset together */
489 int irq; /* Device IRQ */
494 unsigned int bounce_buffer_size;
510 int flags; /* Host attributes */
519 #define SDHCI_USE_64_BIT_DMA (1<<12) /* Use 64-bit DMA */
525 unsigned int version; /* SDHCI spec. version */
527 unsigned int max_clk; /* Max possible freq (MHz) */
528 unsigned int timeout_clk; /* Timeout freq (KHz) */
530 unsigned int clk_mul; /* Clock Muliplier value */
532 unsigned int clock; /* Current clock (MHz) */
534 u8 drv_type; /* Current UHS-I driver type */
535 bool reinit_uhs; /* Force UHS-related re-initialization */
540 bool pending_reset; /* Cmd/data reset is pending */
547 struct mmc_command *cmd; /* Current command */ member
551 unsigned int data_early:1; /* Data finished before cmd */
554 unsigned int blocks; /* remaining PIO blocks */
556 int sg_count; /* Mapped sg entries */
557 int max_adma; /* Max. length in ADMA descriptor */
568 unsigned int desc_sz; /* ADMA current descriptor size */
569 unsigned int alloc_desc_sz; /* ADMA descr. max size host supports */
587 unsigned int ocr_avail_sdio; /* OCR bit masks */
588 unsigned int ocr_avail_sd;
589 unsigned int ocr_avail_mmc;
604 unsigned int tuning_done; /* Condition flag set when CMD19 succeeds */
606 unsigned int tuning_count; /* Timer count for re-tuning */
607 unsigned int tuning_mode; /* Re-tuning mode supported by host */
608 unsigned int tuning_err; /* Error code for re-tuning */
612 /* Delay (ms) between tuning commands */
613 int tuning_delay;
614 int tuning_loop_count;
629 u32 (*read_l)(struct sdhci_host *host, int reg);
630 u16 (*read_w)(struct sdhci_host *host, int reg);
631 u8 (*read_b)(struct sdhci_host *host, int reg);
632 void (*write_l)(struct sdhci_host *host, u32 val, int reg);
633 void (*write_w)(struct sdhci_host *host, u16 val, int reg);
634 void (*write_b)(struct sdhci_host *host, u8 val, int reg);
637 void (*set_clock)(struct sdhci_host *host, unsigned int clock);
643 int (*set_dma_mask)(struct sdhci_host *host);
644 int (*enable_dma)(struct sdhci_host *host);
645 unsigned int (*get_max_clock)(struct sdhci_host *host);
646 unsigned int (*get_min_clock)(struct sdhci_host *host);
648 unsigned int (*get_timeout_clock)(struct sdhci_host *host);
649 unsigned int (*get_max_timeout_count)(struct sdhci_host *host);
651 struct mmc_command *cmd);
652 void (*set_bus_width)(struct sdhci_host *host, int width);
655 unsigned int (*get_ro)(struct sdhci_host *host);
657 int (*platform_execute_tuning)(struct sdhci_host *host, u32 opcode);
658 void (*set_uhs_signaling)(struct sdhci_host *host, unsigned int uhs);
664 dma_addr_t addr, int len, unsigned int cmd);
667 unsigned int length);
675 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel()
677 if (unlikely(host->ops->write_l)) in sdhci_writel()
678 host->ops->write_l(host, val, reg); in sdhci_writel()
680 writel(val, host->ioaddr + reg); in sdhci_writel()
683 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew()
685 if (unlikely(host->ops->write_w)) in sdhci_writew()
686 host->ops->write_w(host, val, reg); in sdhci_writew()
688 writew(val, host->ioaddr + reg); in sdhci_writew()
691 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb()
693 if (unlikely(host->ops->write_b)) in sdhci_writeb()
694 host->ops->write_b(host, val, reg); in sdhci_writeb()
696 writeb(val, host->ioaddr + reg); in sdhci_writeb()
699 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl()
701 if (unlikely(host->ops->read_l)) in sdhci_readl()
702 return host->ops->read_l(host, reg); in sdhci_readl()
704 return readl(host->ioaddr + reg); in sdhci_readl()
707 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw()
709 if (unlikely(host->ops->read_w)) in sdhci_readw()
710 return host->ops->read_w(host, reg); in sdhci_readw()
712 return readw(host->ioaddr + reg); in sdhci_readw()
715 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb()
717 if (unlikely(host->ops->read_b)) in sdhci_readb()
718 return host->ops->read_b(host, reg); in sdhci_readb()
720 return readb(host->ioaddr + reg); in sdhci_readb()
725 static inline void sdhci_writel(struct sdhci_host *host, u32 val, int reg) in sdhci_writel()
727 writel(val, host->ioaddr + reg); in sdhci_writel()
730 static inline void sdhci_writew(struct sdhci_host *host, u16 val, int reg) in sdhci_writew()
732 writew(val, host->ioaddr + reg); in sdhci_writew()
735 static inline void sdhci_writeb(struct sdhci_host *host, u8 val, int reg) in sdhci_writeb()
737 writeb(val, host->ioaddr + reg); in sdhci_writeb()
740 static inline u32 sdhci_readl(struct sdhci_host *host, int reg) in sdhci_readl()
742 return readl(host->ioaddr + reg); in sdhci_readl()
745 static inline u16 sdhci_readw(struct sdhci_host *host, int reg) in sdhci_readw()
747 return readw(host->ioaddr + reg); in sdhci_readw()
750 static inline u8 sdhci_readb(struct sdhci_host *host, int reg) in sdhci_readb()
752 return readb(host->ioaddr + reg); in sdhci_readb()
762 return host->private; in sdhci_priv()
767 int sdhci_setup_host(struct sdhci_host *host);
769 int __sdhci_add_host(struct sdhci_host *host);
770 int sdhci_add_host(struct sdhci_host *host);
771 void sdhci_remove_host(struct sdhci_host *host, int dead);
778 u16 sdhci_calc_clk(struct sdhci_host *host, unsigned int clock,
779 unsigned int *actual_clock);
780 void sdhci_set_clock(struct sdhci_host *host, unsigned int clock);
789 int sdhci_get_cd_nogpio(struct mmc_host *mmc);
791 int sdhci_request_atomic(struct mmc_host *mmc, struct mmc_request *mrq);
792 void sdhci_set_bus_width(struct sdhci_host *host, int width);
795 int sdhci_execute_tuning(struct mmc_host *mmc, u32 opcode);
796 int __sdhci_execute_tuning(struct sdhci_host *host, u32 opcode);
798 int sdhci_start_signal_voltage_switch(struct mmc_host *mmc,
800 void sdhci_enable_sdio_irq(struct mmc_host *mmc, int enable);
802 dma_addr_t addr, int len, unsigned int cmd);
805 int sdhci_suspend_host(struct sdhci_host *host);
806 int sdhci_resume_host(struct sdhci_host *host);
807 int sdhci_runtime_suspend_host(struct sdhci_host *host);
808 int sdhci_runtime_resume_host(struct sdhci_host *host, int soft_reset);
813 bool sdhci_cqe_irq(struct sdhci_host *host, u32 intmask, int *cmd_error,
814 int *data_error);
826 void __sdhci_set_timeout(struct sdhci_host *host, struct mmc_command *cmd);