477 	u32 ssc;  in gl9750_set_ssc()  local
481 	ssc = sdhci_readl(host, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
484 	ssc &= ~SDHCI_GLI_9750_PLLSSC_PPM;  in gl9750_set_ssc()
487 	ssc |= FIELD_PREP(SDHCI_GLI_9750_PLLSSC_PPM, ppm);  in gl9750_set_ssc()
488 	sdhci_writel(host, ssc, SDHCI_GLI_9750_PLLSSC);  in gl9750_set_ssc()
497 	/* set pll to 205MHz and ssc */  in gl9750_set_ssc_pll_205mhz()
506 	/* set pll to 100MHz and ssc */  in gl9750_set_ssc_pll_100mhz()
515 	/* set pll to 50MHz and ssc */  in gl9750_set_ssc_pll_50mhz()
673 	u32 ssc;  in gl9755_set_ssc()  local
677 	pci_read_config_dword(pdev, PCI_GLI_9755_PLLSSC, &ssc);  in gl9755_set_ssc()
680 	ssc &= ~PCI_GLI_9755_PLLSSC_PPM;  in gl9755_set_ssc()
683 	ssc |= FIELD_PREP(PCI_GLI_9755_PLLSSC_PPM, ppm);  in gl9755_set_ssc()
684 	pci_write_config_dword(pdev, PCI_GLI_9755_PLLSSC, ssc);  in gl9755_set_ssc()
693 	/* set pll to 205MHz and ssc */  in gl9755_set_ssc_pll_205mhz()
702 	/* set pll to 100MHz and ssc */  in gl9755_set_ssc_pll_100mhz()
711 	/* set pll to 50MHz and ssc */  in gl9755_set_ssc_pll_50mhz()
844 	u32 ssc;  in gl9767_set_ssc()  local
849 	pci_read_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, &ssc);  in gl9767_set_ssc()
852 	ssc &= ~PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM;  in gl9767_set_ssc()
855 	ssc |= FIELD_PREP(PCIE_GLI_9767_SD_PLL_CTL2_PLLSSC_PPM, ppm);  in gl9767_set_ssc()
856 	pci_write_config_dword(pdev, PCIE_GLI_9767_SD_PLL_CTL2, ssc);  in gl9767_set_ssc()
887 	/* set pll to 205MHz and ssc */  in gl9767_set_ssc_pll_205mhz()