Lines Matching +full:mmc +full:- +full:host
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (c) 2014-2015, 2022 MediaTek Inc.
11 #include <linux/dma-mapping.h>
28 #include <linux/mmc/card.h>
29 #include <linux/mmc/core.h>
30 #include <linux/mmc/host.h>
31 #include <linux/mmc/mmc.h>
32 #include <linux/mmc/sd.h>
33 #include <linux/mmc/sdio.h>
34 #include <linux/mmc/slot-gpio.h>
41 /*--------------------------------------------------------------------------*/
43 /*--------------------------------------------------------------------------*/
50 /*--------------------------------------------------------------------------*/
52 /*--------------------------------------------------------------------------*/
89 /*--------------------------------------------------------------------------*/
91 /*--------------------------------------------------------------------------*/
96 /*--------------------------------------------------------------------------*/
98 /*--------------------------------------------------------------------------*/
335 /*--------------------------------------------------------------------------*/
337 /*--------------------------------------------------------------------------*/
436 void __iomem *base; /* host base address */
437 void __iomem *top_base; /* host top register base address */
450 int irq; /* host interrupt */
461 u32 mclk; /* mmc subsystem clock frequency */
475 bool internal_cd; /* Use internal card-detect logic */
626 { .compatible = "mediatek,mt2701-mmc", .data = &mt2701_compat},
627 { .compatible = "mediatek,mt2712-mmc", .data = &mt2712_compat},
628 { .compatible = "mediatek,mt6779-mmc", .data = &mt6779_compat},
629 { .compatible = "mediatek,mt6795-mmc", .data = &mt6795_compat},
630 { .compatible = "mediatek,mt7620-mmc", .data = &mt7620_compat},
631 { .compatible = "mediatek,mt7622-mmc", .data = &mt7622_compat},
632 { .compatible = "mediatek,mt7986-mmc", .data = &mt7986_compat},
633 { .compatible = "mediatek,mt8135-mmc", .data = &mt8135_compat},
634 { .compatible = "mediatek,mt8173-mmc", .data = &mt8173_compat},
635 { .compatible = "mediatek,mt8183-mmc", .data = &mt8183_compat},
636 { .compatible = "mediatek,mt8516-mmc", .data = &mt8516_compat},
663 tv |= ((val) << (ffs((unsigned int)field) - 1)); in sdr_set_field()
671 *val = ((tv & field) >> (ffs((unsigned int)field) - 1)); in sdr_get_field()
674 static void msdc_reset_hw(struct msdc_host *host) in msdc_reset_hw() argument
678 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_RST); in msdc_reset_hw()
679 readl_poll_timeout_atomic(host->base + MSDC_CFG, val, !(val & MSDC_CFG_RST), 0, 0); in msdc_reset_hw()
681 sdr_set_bits(host->base + MSDC_FIFOCS, MSDC_FIFOCS_CLR); in msdc_reset_hw()
682 readl_poll_timeout_atomic(host->base + MSDC_FIFOCS, val, in msdc_reset_hw()
685 val = readl(host->base + MSDC_INT); in msdc_reset_hw()
686 writel(val, host->base + MSDC_INT); in msdc_reset_hw()
689 static void msdc_cmd_next(struct msdc_host *host,
691 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb);
706 return 0xff - (u8) sum; in msdc_dma_calcs()
709 static inline void msdc_dma_setup(struct msdc_host *host, struct msdc_dma *dma, in msdc_dma_setup() argument
719 sg = data->sg; in msdc_dma_setup()
721 gpd = dma->gpd; in msdc_dma_setup()
722 bd = dma->bd; in msdc_dma_setup()
725 gpd->gpd_info |= GPDMA_DESC_HWO; in msdc_dma_setup()
726 gpd->gpd_info |= GPDMA_DESC_BDP; in msdc_dma_setup()
728 gpd->gpd_info &= ~GPDMA_DESC_CHECKSUM; in msdc_dma_setup()
729 gpd->gpd_info |= msdc_dma_calcs((u8 *) gpd, 16) << 8; in msdc_dma_setup()
732 for_each_sg(data->sg, sg, data->sg_count, j) { in msdc_dma_setup()
740 if (host->dev_comp->support_64g) { in msdc_dma_setup()
746 if (host->dev_comp->support_64g) { in msdc_dma_setup()
754 if (j == data->sg_count - 1) /* the last bd */ in msdc_dma_setup()
764 sdr_set_field(host->base + MSDC_DMA_CFG, MSDC_DMA_CFG_DECSEN, 1); in msdc_dma_setup()
765 dma_ctrl = readl_relaxed(host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
768 writel_relaxed(dma_ctrl, host->base + MSDC_DMA_CTRL); in msdc_dma_setup()
769 if (host->dev_comp->support_64g) in msdc_dma_setup()
770 sdr_set_field(host->base + DMA_SA_H4BIT, DMA_ADDR_HIGH_4BIT, in msdc_dma_setup()
771 upper_32_bits(dma->gpd_addr) & 0xf); in msdc_dma_setup()
772 writel(lower_32_bits(dma->gpd_addr), host->base + MSDC_DMA_SA); in msdc_dma_setup()
775 static void msdc_prepare_data(struct msdc_host *host, struct mmc_data *data) in msdc_prepare_data() argument
777 if (!(data->host_cookie & MSDC_PREPARE_FLAG)) { in msdc_prepare_data()
778 data->host_cookie |= MSDC_PREPARE_FLAG; in msdc_prepare_data()
779 data->sg_count = dma_map_sg(host->dev, data->sg, data->sg_len, in msdc_prepare_data()
784 static void msdc_unprepare_data(struct msdc_host *host, struct mmc_data *data) in msdc_unprepare_data() argument
786 if (data->host_cookie & MSDC_ASYNC_FLAG) in msdc_unprepare_data()
789 if (data->host_cookie & MSDC_PREPARE_FLAG) { in msdc_unprepare_data()
790 dma_unmap_sg(host->dev, data->sg, data->sg_len, in msdc_unprepare_data()
792 data->host_cookie &= ~MSDC_PREPARE_FLAG; in msdc_unprepare_data()
796 static u64 msdc_timeout_cal(struct msdc_host *host, u64 ns, u64 clks) in msdc_timeout_cal() argument
798 struct mmc_host *mmc = mmc_from_priv(host); in msdc_timeout_cal() local
802 if (mmc->actual_clock == 0) { in msdc_timeout_cal()
806 do_div(clk_ns, mmc->actual_clock); in msdc_timeout_cal()
807 timeout = ns + clk_ns - 1; in msdc_timeout_cal()
812 if (host->dev_comp->clk_div_bits == 8) in msdc_timeout_cal()
813 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
816 sdr_get_field(host->base + MSDC_CFG, in msdc_timeout_cal()
820 timeout = timeout > 1 ? timeout - 1 : 0; in msdc_timeout_cal()
826 static void msdc_set_timeout(struct msdc_host *host, u64 ns, u64 clks) in msdc_set_timeout() argument
830 host->timeout_ns = ns; in msdc_set_timeout()
831 host->timeout_clks = clks; in msdc_set_timeout()
833 timeout = msdc_timeout_cal(host, ns, clks); in msdc_set_timeout()
834 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, in msdc_set_timeout()
838 static void msdc_set_busy_timeout(struct msdc_host *host, u64 ns, u64 clks) in msdc_set_busy_timeout() argument
842 timeout = msdc_timeout_cal(host, ns, clks); in msdc_set_busy_timeout()
843 sdr_set_field(host->base + SDC_CFG, SDC_CFG_WRDTOC, in msdc_set_busy_timeout()
847 static void msdc_gate_clock(struct msdc_host *host) in msdc_gate_clock() argument
849 clk_bulk_disable_unprepare(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_gate_clock()
850 clk_disable_unprepare(host->crypto_clk); in msdc_gate_clock()
851 clk_disable_unprepare(host->src_clk_cg); in msdc_gate_clock()
852 clk_disable_unprepare(host->src_clk); in msdc_gate_clock()
853 clk_disable_unprepare(host->bus_clk); in msdc_gate_clock()
854 clk_disable_unprepare(host->h_clk); in msdc_gate_clock()
857 static int msdc_ungate_clock(struct msdc_host *host) in msdc_ungate_clock() argument
862 clk_prepare_enable(host->h_clk); in msdc_ungate_clock()
863 clk_prepare_enable(host->bus_clk); in msdc_ungate_clock()
864 clk_prepare_enable(host->src_clk); in msdc_ungate_clock()
865 clk_prepare_enable(host->src_clk_cg); in msdc_ungate_clock()
866 clk_prepare_enable(host->crypto_clk); in msdc_ungate_clock()
867 ret = clk_bulk_prepare_enable(MSDC_NR_CLOCKS, host->bulk_clks); in msdc_ungate_clock()
869 dev_err(host->dev, "Cannot enable pclk/axi/ahb clock gates\n"); in msdc_ungate_clock()
873 return readl_poll_timeout(host->base + MSDC_CFG, val, in msdc_ungate_clock()
877 static void msdc_set_mclk(struct msdc_host *host, unsigned char timing, u32 hz) in msdc_set_mclk() argument
879 struct mmc_host *mmc = mmc_from_priv(host); in msdc_set_mclk() local
884 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_mclk()
888 dev_dbg(host->dev, "set mclk to 0\n"); in msdc_set_mclk()
889 host->mclk = 0; in msdc_set_mclk()
890 mmc->actual_clock = 0; in msdc_set_mclk()
891 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
895 flags = readl(host->base + MSDC_INTEN); in msdc_set_mclk()
896 sdr_clr_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
897 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
898 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_HS400_CK_MODE); in msdc_set_mclk()
900 sdr_clr_bits(host->base + MSDC_CFG, in msdc_set_mclk()
910 if (hz >= (host->src_clk_freq >> 2)) { in msdc_set_mclk()
912 sclk = host->src_clk_freq >> 2; /* sclk = clk / 4 */ in msdc_set_mclk()
914 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
915 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
920 hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
921 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
922 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
925 sdr_set_bits(host->base + MSDC_CFG, in msdc_set_mclk()
927 sclk = host->src_clk_freq >> 1; in msdc_set_mclk()
930 } else if (hz >= host->src_clk_freq) { in msdc_set_mclk()
933 sclk = host->src_clk_freq; in msdc_set_mclk()
936 if (hz >= (host->src_clk_freq >> 1)) { in msdc_set_mclk()
938 sclk = host->src_clk_freq >> 1; /* sclk = clk / 2 */ in msdc_set_mclk()
940 div = (host->src_clk_freq + ((hz << 2) - 1)) / (hz << 2); in msdc_set_mclk()
941 sclk = (host->src_clk_freq >> 2) / div; in msdc_set_mclk()
944 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
946 clk_disable_unprepare(host->src_clk_cg); in msdc_set_mclk()
947 if (host->dev_comp->clk_div_bits == 8) in msdc_set_mclk()
948 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
952 sdr_set_field(host->base + MSDC_CFG, in msdc_set_mclk()
956 clk_prepare_enable(host->src_clk_cg); in msdc_set_mclk()
957 readl_poll_timeout(host->base + MSDC_CFG, val, (val & MSDC_CFG_CKSTB), 0, 0); in msdc_set_mclk()
958 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_CKPDN); in msdc_set_mclk()
959 mmc->actual_clock = sclk; in msdc_set_mclk()
960 host->mclk = hz; in msdc_set_mclk()
961 host->timing = timing; in msdc_set_mclk()
963 msdc_set_timeout(host, host->timeout_ns, host->timeout_clks); in msdc_set_mclk()
964 sdr_set_bits(host->base + MSDC_INTEN, flags); in msdc_set_mclk()
970 if (mmc->actual_clock <= 52000000) { in msdc_set_mclk()
971 writel(host->def_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
972 if (host->top_base) { in msdc_set_mclk()
973 writel(host->def_tune_para.emmc_top_control, in msdc_set_mclk()
974 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
975 writel(host->def_tune_para.emmc_top_cmd, in msdc_set_mclk()
976 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
978 writel(host->def_tune_para.pad_tune, in msdc_set_mclk()
979 host->base + tune_reg); in msdc_set_mclk()
982 writel(host->saved_tune_para.iocon, host->base + MSDC_IOCON); in msdc_set_mclk()
983 writel(host->saved_tune_para.pad_cmd_tune, in msdc_set_mclk()
984 host->base + PAD_CMD_TUNE); in msdc_set_mclk()
985 if (host->top_base) { in msdc_set_mclk()
986 writel(host->saved_tune_para.emmc_top_control, in msdc_set_mclk()
987 host->top_base + EMMC_TOP_CONTROL); in msdc_set_mclk()
988 writel(host->saved_tune_para.emmc_top_cmd, in msdc_set_mclk()
989 host->top_base + EMMC_TOP_CMD); in msdc_set_mclk()
991 writel(host->saved_tune_para.pad_tune, in msdc_set_mclk()
992 host->base + tune_reg); in msdc_set_mclk()
997 host->dev_comp->hs400_tune) in msdc_set_mclk()
998 sdr_set_field(host->base + tune_reg, in msdc_set_mclk()
1000 host->hs400_cmd_int_delay); in msdc_set_mclk()
1001 dev_dbg(host->dev, "sclk: %d, timing: %d\n", mmc->actual_clock, in msdc_set_mclk()
1005 static inline u32 msdc_cmd_find_resp(struct msdc_host *host, in msdc_cmd_find_resp() argument
1033 static inline u32 msdc_cmd_prepare_raw_cmd(struct msdc_host *host, in msdc_cmd_prepare_raw_cmd() argument
1036 struct mmc_host *mmc = mmc_from_priv(host); in msdc_cmd_prepare_raw_cmd() local
1041 u32 opcode = cmd->opcode; in msdc_cmd_prepare_raw_cmd()
1042 u32 resp = msdc_cmd_find_resp(host, cmd); in msdc_cmd_prepare_raw_cmd()
1045 host->cmd_rsp = resp; in msdc_cmd_prepare_raw_cmd()
1047 if ((opcode == SD_IO_RW_DIRECT && cmd->flags == (unsigned int) -1) || in msdc_cmd_prepare_raw_cmd()
1059 if (cmd->data) { in msdc_cmd_prepare_raw_cmd()
1060 struct mmc_data *data = cmd->data; in msdc_cmd_prepare_raw_cmd()
1063 if (mmc_card_mmc(mmc->card) && mrq->sbc && in msdc_cmd_prepare_raw_cmd()
1064 !(mrq->sbc->arg & 0xFFFF0000)) in msdc_cmd_prepare_raw_cmd()
1068 rawcmd |= ((data->blksz & 0xFFF) << 16); in msdc_cmd_prepare_raw_cmd()
1069 if (data->flags & MMC_DATA_WRITE) in msdc_cmd_prepare_raw_cmd()
1071 if (data->blocks > 1) in msdc_cmd_prepare_raw_cmd()
1076 sdr_clr_bits(host->base + MSDC_CFG, MSDC_CFG_PIO); in msdc_cmd_prepare_raw_cmd()
1078 if (host->timeout_ns != data->timeout_ns || in msdc_cmd_prepare_raw_cmd()
1079 host->timeout_clks != data->timeout_clks) in msdc_cmd_prepare_raw_cmd()
1080 msdc_set_timeout(host, data->timeout_ns, in msdc_cmd_prepare_raw_cmd()
1081 data->timeout_clks); in msdc_cmd_prepare_raw_cmd()
1083 writel(data->blocks, host->base + SDC_BLK_NUM); in msdc_cmd_prepare_raw_cmd()
1088 static void msdc_start_data(struct msdc_host *host, struct mmc_command *cmd, in msdc_start_data() argument
1093 WARN_ON(host->data); in msdc_start_data()
1094 host->data = data; in msdc_start_data()
1095 read = data->flags & MMC_DATA_READ; in msdc_start_data()
1097 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_data()
1098 msdc_dma_setup(host, &host->dma, data); in msdc_start_data()
1099 sdr_set_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_start_data()
1100 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_START, 1); in msdc_start_data()
1101 dev_dbg(host->dev, "DMA start\n"); in msdc_start_data()
1102 dev_dbg(host->dev, "%s: cmd=%d DMA data: %d blocks; read=%d\n", in msdc_start_data()
1103 __func__, cmd->opcode, data->blocks, read); in msdc_start_data()
1106 static int msdc_auto_cmd_done(struct msdc_host *host, int events, in msdc_auto_cmd_done() argument
1109 u32 *rsp = cmd->resp; in msdc_auto_cmd_done()
1111 rsp[0] = readl(host->base + SDC_ACMD_RESP); in msdc_auto_cmd_done()
1114 cmd->error = 0; in msdc_auto_cmd_done()
1116 msdc_reset_hw(host); in msdc_auto_cmd_done()
1118 cmd->error = -EILSEQ; in msdc_auto_cmd_done()
1119 host->error |= REQ_STOP_EIO; in msdc_auto_cmd_done()
1121 cmd->error = -ETIMEDOUT; in msdc_auto_cmd_done()
1122 host->error |= REQ_STOP_TMO; in msdc_auto_cmd_done()
1124 dev_err(host->dev, in msdc_auto_cmd_done()
1126 __func__, cmd->opcode, cmd->arg, rsp[0], cmd->error); in msdc_auto_cmd_done()
1128 return cmd->error; in msdc_auto_cmd_done()
1132 * msdc_recheck_sdio_irq - recheck whether the SDIO irq is lost
1134 * Host controller may lost interrupt in some special case.
1138 static void msdc_recheck_sdio_irq(struct msdc_host *host) in msdc_recheck_sdio_irq() argument
1140 struct mmc_host *mmc = mmc_from_priv(host); in msdc_recheck_sdio_irq() local
1143 if (mmc->caps & MMC_CAP_SDIO_IRQ) { in msdc_recheck_sdio_irq()
1144 reg_inten = readl(host->base + MSDC_INTEN); in msdc_recheck_sdio_irq()
1146 reg_int = readl(host->base + MSDC_INT); in msdc_recheck_sdio_irq()
1147 reg_ps = readl(host->base + MSDC_PS); in msdc_recheck_sdio_irq()
1150 __msdc_enable_sdio_irq(host, 0); in msdc_recheck_sdio_irq()
1151 sdio_signal_irq(mmc); in msdc_recheck_sdio_irq()
1157 static void msdc_track_cmd_data(struct msdc_host *host, struct mmc_command *cmd) in msdc_track_cmd_data() argument
1159 if (host->error && in msdc_track_cmd_data()
1160 ((!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning) || in msdc_track_cmd_data()
1161 cmd->error == -ETIMEDOUT)) in msdc_track_cmd_data()
1162 dev_warn(host->dev, "%s: cmd=%d arg=%08X; host->error=0x%08X\n", in msdc_track_cmd_data()
1163 __func__, cmd->opcode, cmd->arg, host->error); in msdc_track_cmd_data()
1166 static void msdc_request_done(struct msdc_host *host, struct mmc_request *mrq) in msdc_request_done() argument
1174 cancel_delayed_work(&host->req_timeout); in msdc_request_done()
1176 spin_lock_irqsave(&host->lock, flags); in msdc_request_done()
1177 host->mrq = NULL; in msdc_request_done()
1178 spin_unlock_irqrestore(&host->lock, flags); in msdc_request_done()
1180 msdc_track_cmd_data(host, mrq->cmd); in msdc_request_done()
1181 if (mrq->data) in msdc_request_done()
1182 msdc_unprepare_data(host, mrq->data); in msdc_request_done()
1183 if (host->error) in msdc_request_done()
1184 msdc_reset_hw(host); in msdc_request_done()
1185 mmc_request_done(mmc_from_priv(host), mrq); in msdc_request_done()
1186 if (host->dev_comp->recheck_sdio_irq) in msdc_request_done()
1187 msdc_recheck_sdio_irq(host); in msdc_request_done()
1191 static bool msdc_cmd_done(struct msdc_host *host, int events, in msdc_cmd_done() argument
1199 if (mrq->sbc && cmd == mrq->cmd && in msdc_cmd_done()
1202 msdc_auto_cmd_done(host, events, mrq->sbc); in msdc_cmd_done()
1204 sbc_error = mrq->sbc && mrq->sbc->error; in msdc_cmd_done()
1211 spin_lock_irqsave(&host->lock, flags); in msdc_cmd_done()
1212 done = !host->cmd; in msdc_cmd_done()
1213 host->cmd = NULL; in msdc_cmd_done()
1214 spin_unlock_irqrestore(&host->lock, flags); in msdc_cmd_done()
1218 rsp = cmd->resp; in msdc_cmd_done()
1220 sdr_clr_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_cmd_done()
1222 if (cmd->flags & MMC_RSP_PRESENT) { in msdc_cmd_done()
1223 if (cmd->flags & MMC_RSP_136) { in msdc_cmd_done()
1224 rsp[0] = readl(host->base + SDC_RESP3); in msdc_cmd_done()
1225 rsp[1] = readl(host->base + SDC_RESP2); in msdc_cmd_done()
1226 rsp[2] = readl(host->base + SDC_RESP1); in msdc_cmd_done()
1227 rsp[3] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1229 rsp[0] = readl(host->base + SDC_RESP0); in msdc_cmd_done()
1235 (!mmc_op_tuning(cmd->opcode) && !host->hs400_tuning)) in msdc_cmd_done()
1241 msdc_reset_hw(host); in msdc_cmd_done()
1243 cmd->error = -EILSEQ; in msdc_cmd_done()
1244 host->error |= REQ_CMD_EIO; in msdc_cmd_done()
1246 cmd->error = -ETIMEDOUT; in msdc_cmd_done()
1247 host->error |= REQ_CMD_TMO; in msdc_cmd_done()
1250 if (cmd->error) in msdc_cmd_done()
1251 dev_dbg(host->dev, in msdc_cmd_done()
1253 __func__, cmd->opcode, cmd->arg, rsp[0], in msdc_cmd_done()
1254 cmd->error); in msdc_cmd_done()
1256 msdc_cmd_next(host, mrq, cmd); in msdc_cmd_done()
1261 * is correct before issue a request. but host design do below
1264 static inline bool msdc_cmd_is_ready(struct msdc_host *host, in msdc_cmd_is_ready() argument
1271 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1274 dev_err(host->dev, "CMD bus busy detected\n"); in msdc_cmd_is_ready()
1275 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1276 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); in msdc_cmd_is_ready()
1280 if (mmc_resp_type(cmd) == MMC_RSP_R1B || cmd->data) { in msdc_cmd_is_ready()
1282 ret = readl_poll_timeout_atomic(host->base + SDC_STS, val, in msdc_cmd_is_ready()
1285 dev_err(host->dev, "Controller busy detected\n"); in msdc_cmd_is_ready()
1286 host->error |= REQ_CMD_BUSY; in msdc_cmd_is_ready()
1287 msdc_cmd_done(host, MSDC_INT_CMDTMO, mrq, cmd); in msdc_cmd_is_ready()
1294 static void msdc_start_command(struct msdc_host *host, in msdc_start_command() argument
1300 WARN_ON(host->cmd); in msdc_start_command()
1301 host->cmd = cmd; in msdc_start_command()
1303 mod_delayed_work(system_wq, &host->req_timeout, DAT_TIMEOUT); in msdc_start_command()
1304 if (!msdc_cmd_is_ready(host, mrq, cmd)) in msdc_start_command()
1307 if ((readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_TXCNT) >> 16 || in msdc_start_command()
1308 readl(host->base + MSDC_FIFOCS) & MSDC_FIFOCS_RXCNT) { in msdc_start_command()
1309 dev_err(host->dev, "TX/RX FIFO non-empty before start of IO. Reset\n"); in msdc_start_command()
1310 msdc_reset_hw(host); in msdc_start_command()
1313 cmd->error = 0; in msdc_start_command()
1314 rawcmd = msdc_cmd_prepare_raw_cmd(host, mrq, cmd); in msdc_start_command()
1316 spin_lock_irqsave(&host->lock, flags); in msdc_start_command()
1317 sdr_set_bits(host->base + MSDC_INTEN, cmd_ints_mask); in msdc_start_command()
1318 spin_unlock_irqrestore(&host->lock, flags); in msdc_start_command()
1320 writel(cmd->arg, host->base + SDC_ARG); in msdc_start_command()
1321 writel(rawcmd, host->base + SDC_CMD); in msdc_start_command()
1324 static void msdc_cmd_next(struct msdc_host *host, in msdc_cmd_next() argument
1327 if ((cmd->error && in msdc_cmd_next()
1328 !(cmd->error == -EILSEQ && in msdc_cmd_next()
1329 (mmc_op_tuning(cmd->opcode) || host->hs400_tuning))) || in msdc_cmd_next()
1330 (mrq->sbc && mrq->sbc->error)) in msdc_cmd_next()
1331 msdc_request_done(host, mrq); in msdc_cmd_next()
1332 else if (cmd == mrq->sbc) in msdc_cmd_next()
1333 msdc_start_command(host, mrq, mrq->cmd); in msdc_cmd_next()
1334 else if (!cmd->data) in msdc_cmd_next()
1335 msdc_request_done(host, mrq); in msdc_cmd_next()
1337 msdc_start_data(host, cmd, cmd->data); in msdc_cmd_next()
1340 static void msdc_ops_request(struct mmc_host *mmc, struct mmc_request *mrq) in msdc_ops_request() argument
1342 struct msdc_host *host = mmc_priv(mmc); in msdc_ops_request() local
1344 host->error = 0; in msdc_ops_request()
1345 WARN_ON(host->mrq); in msdc_ops_request()
1346 host->mrq = mrq; in msdc_ops_request()
1348 if (mrq->data) in msdc_ops_request()
1349 msdc_prepare_data(host, mrq->data); in msdc_ops_request()
1355 if (mrq->sbc && (!mmc_card_mmc(mmc->card) || in msdc_ops_request()
1356 (mrq->sbc->arg & 0xFFFF0000))) in msdc_ops_request()
1357 msdc_start_command(host, mrq, mrq->sbc); in msdc_ops_request()
1359 msdc_start_command(host, mrq, mrq->cmd); in msdc_ops_request()
1362 static void msdc_pre_req(struct mmc_host *mmc, struct mmc_request *mrq) in msdc_pre_req() argument
1364 struct msdc_host *host = mmc_priv(mmc); in msdc_pre_req() local
1365 struct mmc_data *data = mrq->data; in msdc_pre_req()
1370 msdc_prepare_data(host, data); in msdc_pre_req()
1371 data->host_cookie |= MSDC_ASYNC_FLAG; in msdc_pre_req()
1374 static void msdc_post_req(struct mmc_host *mmc, struct mmc_request *mrq, in msdc_post_req() argument
1377 struct msdc_host *host = mmc_priv(mmc); in msdc_post_req() local
1378 struct mmc_data *data = mrq->data; in msdc_post_req()
1383 if (data->host_cookie) { in msdc_post_req()
1384 data->host_cookie &= ~MSDC_ASYNC_FLAG; in msdc_post_req()
1385 msdc_unprepare_data(host, data); in msdc_post_req()
1389 static void msdc_data_xfer_next(struct msdc_host *host, struct mmc_request *mrq) in msdc_data_xfer_next() argument
1391 if (mmc_op_multi(mrq->cmd->opcode) && mrq->stop && !mrq->stop->error && in msdc_data_xfer_next()
1392 !mrq->sbc) in msdc_data_xfer_next()
1393 msdc_start_command(host, mrq, mrq->stop); in msdc_data_xfer_next()
1395 msdc_request_done(host, mrq); in msdc_data_xfer_next()
1398 static void msdc_data_xfer_done(struct msdc_host *host, u32 events, in msdc_data_xfer_done() argument
1411 spin_lock_irqsave(&host->lock, flags); in msdc_data_xfer_done()
1412 done = !host->data; in msdc_data_xfer_done()
1414 host->data = NULL; in msdc_data_xfer_done()
1415 spin_unlock_irqrestore(&host->lock, flags); in msdc_data_xfer_done()
1419 stop = data->stop; in msdc_data_xfer_done()
1421 if (check_data || (stop && stop->error)) { in msdc_data_xfer_done()
1422 dev_dbg(host->dev, "DMA status: 0x%8X\n", in msdc_data_xfer_done()
1423 readl(host->base + MSDC_DMA_CFG)); in msdc_data_xfer_done()
1424 sdr_set_field(host->base + MSDC_DMA_CTRL, MSDC_DMA_CTRL_STOP, in msdc_data_xfer_done()
1427 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CTRL, val, in msdc_data_xfer_done()
1430 dev_dbg(host->dev, "DMA stop timed out\n"); in msdc_data_xfer_done()
1432 ret = readl_poll_timeout_atomic(host->base + MSDC_DMA_CFG, val, in msdc_data_xfer_done()
1435 dev_dbg(host->dev, "DMA inactive timed out\n"); in msdc_data_xfer_done()
1437 sdr_clr_bits(host->base + MSDC_INTEN, data_ints_mask); in msdc_data_xfer_done()
1438 dev_dbg(host->dev, "DMA stop\n"); in msdc_data_xfer_done()
1440 if ((events & MSDC_INT_XFER_COMPL) && (!stop || !stop->error)) { in msdc_data_xfer_done()
1441 data->bytes_xfered = data->blocks * data->blksz; in msdc_data_xfer_done()
1443 dev_dbg(host->dev, "interrupt events: %x\n", events); in msdc_data_xfer_done()
1444 msdc_reset_hw(host); in msdc_data_xfer_done()
1445 host->error |= REQ_DAT_ERR; in msdc_data_xfer_done()
1446 data->bytes_xfered = 0; in msdc_data_xfer_done()
1449 data->error = -ETIMEDOUT; in msdc_data_xfer_done()
1451 data->error = -EILSEQ; in msdc_data_xfer_done()
1453 dev_dbg(host->dev, "%s: cmd=%d; blocks=%d", in msdc_data_xfer_done()
1454 __func__, mrq->cmd->opcode, data->blocks); in msdc_data_xfer_done()
1455 dev_dbg(host->dev, "data_error=%d xfer_size=%d\n", in msdc_data_xfer_done()
1456 (int)data->error, data->bytes_xfered); in msdc_data_xfer_done()
1459 msdc_data_xfer_next(host, mrq); in msdc_data_xfer_done()
1463 static void msdc_set_buswidth(struct msdc_host *host, u32 width) in msdc_set_buswidth() argument
1465 u32 val = readl(host->base + SDC_CFG); in msdc_set_buswidth()
1482 writel(val, host->base + SDC_CFG); in msdc_set_buswidth()
1483 dev_dbg(host->dev, "Bus Width = %d", width); in msdc_set_buswidth()
1486 static int msdc_ops_switch_volt(struct mmc_host *mmc, struct mmc_ios *ios) in msdc_ops_switch_volt() argument
1488 struct msdc_host *host = mmc_priv(mmc); in msdc_ops_switch_volt() local
1491 if (!IS_ERR(mmc->supply.vqmmc)) { in msdc_ops_switch_volt()
1492 if (ios->signal_voltage != MMC_SIGNAL_VOLTAGE_330 && in msdc_ops_switch_volt()
1493 ios->signal_voltage != MMC_SIGNAL_VOLTAGE_180) { in msdc_ops_switch_volt()
1494 dev_err(host->dev, "Unsupported signal voltage!\n"); in msdc_ops_switch_volt()
1495 return -EINVAL; in msdc_ops_switch_volt()
1498 ret = mmc_regulator_set_vqmmc(mmc, ios); in msdc_ops_switch_volt()
1500 dev_dbg(host->dev, "Regulator set error %d (%d)\n", in msdc_ops_switch_volt()
1501 ret, ios->signal_voltage); in msdc_ops_switch_volt()
1506 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_180) in msdc_ops_switch_volt()
1507 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_ops_switch_volt()
1509 pinctrl_select_state(host->pinctrl, host->pins_default); in msdc_ops_switch_volt()
1514 static int msdc_card_busy(struct mmc_host *mmc) in msdc_card_busy() argument
1516 struct msdc_host *host = mmc_priv(mmc); in msdc_card_busy() local
1517 u32 status = readl(host->base + MSDC_PS); in msdc_card_busy()
1525 struct msdc_host *host = container_of(work, struct msdc_host, in msdc_request_timeout() local
1529 dev_err(host->dev, "%s: aborting cmd/data/mrq\n", __func__); in msdc_request_timeout()
1530 if (host->mrq) { in msdc_request_timeout()
1531 dev_err(host->dev, "%s: aborting mrq=%p cmd=%d\n", __func__, in msdc_request_timeout()
1532 host->mrq, host->mrq->cmd->opcode); in msdc_request_timeout()
1533 if (host->cmd) { in msdc_request_timeout()
1534 dev_err(host->dev, "%s: aborting cmd=%d\n", in msdc_request_timeout()
1535 __func__, host->cmd->opcode); in msdc_request_timeout()
1536 msdc_cmd_done(host, MSDC_INT_CMDTMO, host->mrq, in msdc_request_timeout()
1537 host->cmd); in msdc_request_timeout()
1538 } else if (host->data) { in msdc_request_timeout()
1539 dev_err(host->dev, "%s: abort data: cmd%d; %d blocks\n", in msdc_request_timeout()
1540 __func__, host->mrq->cmd->opcode, in msdc_request_timeout()
1541 host->data->blocks); in msdc_request_timeout()
1542 msdc_data_xfer_done(host, MSDC_INT_DATTMO, host->mrq, in msdc_request_timeout()
1543 host->data); in msdc_request_timeout()
1548 static void __msdc_enable_sdio_irq(struct msdc_host *host, int enb) in __msdc_enable_sdio_irq() argument
1551 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1552 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1553 if (host->dev_comp->recheck_sdio_irq) in __msdc_enable_sdio_irq()
1554 msdc_recheck_sdio_irq(host); in __msdc_enable_sdio_irq()
1556 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in __msdc_enable_sdio_irq()
1557 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in __msdc_enable_sdio_irq()
1561 static void msdc_enable_sdio_irq(struct mmc_host *mmc, int enb) in msdc_enable_sdio_irq() argument
1563 struct msdc_host *host = mmc_priv(mmc); in msdc_enable_sdio_irq() local
1567 spin_lock_irqsave(&host->lock, flags); in msdc_enable_sdio_irq()
1568 __msdc_enable_sdio_irq(host, enb); in msdc_enable_sdio_irq()
1569 spin_unlock_irqrestore(&host->lock, flags); in msdc_enable_sdio_irq()
1571 if (mmc_card_enable_async_irq(mmc->card) && host->pins_eint) { in msdc_enable_sdio_irq()
1579 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_enable_sdio_irq()
1580 ret = dev_pm_set_dedicated_wake_irq_reverse(host->dev, host->eint_irq); in msdc_enable_sdio_irq()
1583 dev_err(host->dev, "Failed to register SDIO wakeup irq!\n"); in msdc_enable_sdio_irq()
1584 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1585 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1587 dev_dbg(host->dev, "SDIO eint irq: %d!\n", host->eint_irq); in msdc_enable_sdio_irq()
1590 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_enable_sdio_irq()
1592 dev_pm_clear_wake_irq(host->dev); in msdc_enable_sdio_irq()
1596 /* Ensure host->pins_eint is NULL */ in msdc_enable_sdio_irq()
1597 host->pins_eint = NULL; in msdc_enable_sdio_irq()
1598 pm_runtime_get_noresume(host->dev); in msdc_enable_sdio_irq()
1600 pm_runtime_put_noidle(host->dev); in msdc_enable_sdio_irq()
1605 static irqreturn_t msdc_cmdq_irq(struct msdc_host *host, u32 intsts) in msdc_cmdq_irq() argument
1607 struct mmc_host *mmc = mmc_from_priv(host); in msdc_cmdq_irq() local
1611 cmd_err = -EILSEQ; in msdc_cmdq_irq()
1612 dev_err(host->dev, "%s: CMD CRC ERR", __func__); in msdc_cmdq_irq()
1614 cmd_err = -ETIMEDOUT; in msdc_cmdq_irq()
1615 dev_err(host->dev, "%s: CMD TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1619 dat_err = -EILSEQ; in msdc_cmdq_irq()
1620 dev_err(host->dev, "%s: DATA CRC ERR", __func__); in msdc_cmdq_irq()
1622 dat_err = -ETIMEDOUT; in msdc_cmdq_irq()
1623 dev_err(host->dev, "%s: DATA TIMEOUT ERR", __func__); in msdc_cmdq_irq()
1627 dev_err(host->dev, "cmd_err = %d, dat_err = %d, intsts = 0x%x", in msdc_cmdq_irq()
1631 return cqhci_irq(mmc, 0, cmd_err, dat_err); in msdc_cmdq_irq()
1636 struct msdc_host *host = (struct msdc_host *) dev_id; in msdc_irq() local
1637 struct mmc_host *mmc = mmc_from_priv(host); in msdc_irq() local
1645 spin_lock(&host->lock); in msdc_irq()
1646 events = readl(host->base + MSDC_INT); in msdc_irq()
1647 event_mask = readl(host->base + MSDC_INTEN); in msdc_irq()
1649 __msdc_enable_sdio_irq(host, 0); in msdc_irq()
1651 writel(events & event_mask, host->base + MSDC_INT); in msdc_irq()
1653 mrq = host->mrq; in msdc_irq()
1654 cmd = host->cmd; in msdc_irq()
1655 data = host->data; in msdc_irq()
1656 spin_unlock(&host->lock); in msdc_irq()
1659 sdio_signal_irq(mmc); in msdc_irq()
1662 if (host->internal_cd) in msdc_irq()
1663 mmc_detect_change(mmc, msecs_to_jiffies(20)); in msdc_irq()
1670 if ((mmc->caps2 & MMC_CAP2_CQE) && in msdc_irq()
1672 msdc_cmdq_irq(host, events); in msdc_irq()
1674 writel(events, host->base + MSDC_INT); in msdc_irq()
1679 dev_err(host->dev, in msdc_irq()
1686 dev_dbg(host->dev, "%s: events=%08X\n", __func__, events); in msdc_irq()
1689 msdc_cmd_done(host, events, mrq, cmd); in msdc_irq()
1691 msdc_data_xfer_done(host, events, mrq, data); in msdc_irq()
1697 static void msdc_init_hw(struct msdc_host *host) in msdc_init_hw() argument
1700 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_init_hw()
1701 struct mmc_host *mmc = mmc_from_priv(host); in msdc_init_hw() local
1703 if (host->reset) { in msdc_init_hw()
1704 reset_control_assert(host->reset); in msdc_init_hw()
1706 reset_control_deassert(host->reset); in msdc_init_hw()
1709 /* Configure to MMC/SD mode, clock free running */ in msdc_init_hw()
1710 sdr_set_bits(host->base + MSDC_CFG, MSDC_CFG_MODE | MSDC_CFG_CKPDN); in msdc_init_hw()
1713 msdc_reset_hw(host); in msdc_init_hw()
1716 writel(0, host->base + MSDC_INTEN); in msdc_init_hw()
1717 val = readl(host->base + MSDC_INT); in msdc_init_hw()
1718 writel(val, host->base + MSDC_INT); in msdc_init_hw()
1721 if (host->internal_cd) { in msdc_init_hw()
1722 sdr_set_field(host->base + MSDC_PS, MSDC_PS_CDDEBOUNCE, in msdc_init_hw()
1724 sdr_set_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1725 sdr_set_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1726 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1728 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_init_hw()
1729 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_init_hw()
1730 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_CDSC); in msdc_init_hw()
1733 if (host->top_base) { in msdc_init_hw()
1734 writel(0, host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1735 writel(0, host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1737 writel(0, host->base + tune_reg); in msdc_init_hw()
1739 writel(0, host->base + MSDC_IOCON); in msdc_init_hw()
1740 sdr_set_field(host->base + MSDC_IOCON, MSDC_IOCON_DDLSEL, 0); in msdc_init_hw()
1741 writel(0x403c0046, host->base + MSDC_PATCH_BIT); in msdc_init_hw()
1742 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_CKGEN_MSDC_DLY_SEL, 1); in msdc_init_hw()
1743 writel(0xffff4089, host->base + MSDC_PATCH_BIT1); in msdc_init_hw()
1744 sdr_set_bits(host->base + EMMC50_CFG0, EMMC50_CFG_CFCSTS_SEL); in msdc_init_hw()
1746 if (host->dev_comp->stop_clk_fix) { in msdc_init_hw()
1747 sdr_set_field(host->base + MSDC_PATCH_BIT1, in msdc_init_hw()
1749 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1751 sdr_clr_bits(host->base + SDC_FIFO_CFG, in msdc_init_hw()
1755 if (host->dev_comp->busy_check) in msdc_init_hw()
1756 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, BIT(7)); in msdc_init_hw()
1758 if (host->dev_comp->async_fifo) { in msdc_init_hw()
1759 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1761 if (host->dev_comp->enhance_rx) { in msdc_init_hw()
1762 if (host->top_base) in msdc_init_hw()
1763 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1766 sdr_set_bits(host->base + SDC_ADV_CFG0, in msdc_init_hw()
1769 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1771 sdr_set_field(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1775 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1777 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1781 if (host->dev_comp->support_64g) in msdc_init_hw()
1782 sdr_set_bits(host->base + MSDC_PATCH_BIT2, in msdc_init_hw()
1784 if (host->dev_comp->data_tune) { in msdc_init_hw()
1785 if (host->top_base) { in msdc_init_hw()
1786 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1788 sdr_clr_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1790 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1792 if (host->tuning_step > PAD_DELAY_HALF) { in msdc_init_hw()
1793 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1795 sdr_set_bits(host->top_base + EMMC_TOP_CMD, in msdc_init_hw()
1799 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1802 if (host->tuning_step > PAD_DELAY_HALF) in msdc_init_hw()
1803 sdr_set_bits(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_init_hw()
1809 if (host->top_base) in msdc_init_hw()
1810 sdr_set_bits(host->top_base + EMMC_TOP_CONTROL, in msdc_init_hw()
1813 sdr_set_bits(host->base + tune_reg, in msdc_init_hw()
1817 if (mmc->caps2 & MMC_CAP2_NO_SDIO) { in msdc_init_hw()
1818 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1819 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INTEN_SDIOIRQ); in msdc_init_hw()
1820 sdr_clr_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1823 sdr_set_bits(host->base + SDC_CFG, SDC_CFG_SDIO); in msdc_init_hw()
1826 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_SDIOIDE); in msdc_init_hw()
1827 sdr_set_bits(host->base + SDC_ADV_CFG0, SDC_DAT1_IRQ_TRIGGER); in msdc_init_hw()
1831 sdr_set_field(host->base + SDC_CFG, SDC_CFG_DTOC, 3); in msdc_init_hw()
1833 host->def_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1834 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_init_hw()
1835 if (host->top_base) { in msdc_init_hw()
1836 host->def_tune_para.emmc_top_control = in msdc_init_hw()
1837 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1838 host->def_tune_para.emmc_top_cmd = in msdc_init_hw()
1839 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1840 host->saved_tune_para.emmc_top_control = in msdc_init_hw()
1841 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_init_hw()
1842 host->saved_tune_para.emmc_top_cmd = in msdc_init_hw()
1843 readl(host->top_base + EMMC_TOP_CMD); in msdc_init_hw()
1845 host->def_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1846 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_init_hw()
1848 dev_dbg(host->dev, "init hardware done!"); in msdc_init_hw()
1851 static void msdc_deinit_hw(struct msdc_host *host) in msdc_deinit_hw() argument
1855 if (host->internal_cd) { in msdc_deinit_hw()
1856 /* Disabled card-detect */ in msdc_deinit_hw()
1857 sdr_clr_bits(host->base + MSDC_PS, MSDC_PS_CDEN); in msdc_deinit_hw()
1858 sdr_clr_bits(host->base + SDC_CFG, SDC_CFG_INSWKUP); in msdc_deinit_hw()
1862 writel(0, host->base + MSDC_INTEN); in msdc_deinit_hw()
1864 val = readl(host->base + MSDC_INT); in msdc_deinit_hw()
1865 writel(val, host->base + MSDC_INT); in msdc_deinit_hw()
1869 static void msdc_init_gpd_bd(struct msdc_host *host, struct msdc_dma *dma) in msdc_init_gpd_bd() argument
1871 struct mt_gpdma_desc *gpd = dma->gpd; in msdc_init_gpd_bd()
1872 struct mt_bdma_desc *bd = dma->bd; in msdc_init_gpd_bd()
1878 dma_addr = dma->gpd_addr + sizeof(struct mt_gpdma_desc); in msdc_init_gpd_bd()
1879 gpd->gpd_info = GPDMA_DESC_BDP; /* hwo, cs, bd pointer */ in msdc_init_gpd_bd()
1880 /* gpd->next is must set for desc DMA in msdc_init_gpd_bd()
1883 gpd->next = lower_32_bits(dma_addr); in msdc_init_gpd_bd()
1884 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1885 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 24; in msdc_init_gpd_bd()
1887 dma_addr = dma->bd_addr; in msdc_init_gpd_bd()
1888 gpd->ptr = lower_32_bits(dma->bd_addr); /* physical address */ in msdc_init_gpd_bd()
1889 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1890 gpd->gpd_info |= (upper_32_bits(dma_addr) & 0xf) << 28; in msdc_init_gpd_bd()
1893 for (i = 0; i < (MAX_BD_NUM - 1); i++) { in msdc_init_gpd_bd()
1894 dma_addr = dma->bd_addr + sizeof(*bd) * (i + 1); in msdc_init_gpd_bd()
1896 if (host->dev_comp->support_64g) in msdc_init_gpd_bd()
1901 static void msdc_ops_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) in msdc_ops_set_ios() argument
1903 struct msdc_host *host = mmc_priv(mmc); in msdc_ops_set_ios() local
1906 msdc_set_buswidth(host, ios->bus_width); in msdc_ops_set_ios()
1909 switch (ios->power_mode) { in msdc_ops_set_ios()
1911 if (!IS_ERR(mmc->supply.vmmc)) { in msdc_ops_set_ios()
1912 msdc_init_hw(host); in msdc_ops_set_ios()
1913 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in msdc_ops_set_ios()
1914 ios->vdd); in msdc_ops_set_ios()
1916 dev_err(host->dev, "Failed to set vmmc power!\n"); in msdc_ops_set_ios()
1922 if (!IS_ERR(mmc->supply.vqmmc) && !host->vqmmc_enabled) { in msdc_ops_set_ios()
1923 ret = regulator_enable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1925 dev_err(host->dev, "Failed to set vqmmc power!\n"); in msdc_ops_set_ios()
1927 host->vqmmc_enabled = true; in msdc_ops_set_ios()
1931 if (!IS_ERR(mmc->supply.vmmc)) in msdc_ops_set_ios()
1932 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in msdc_ops_set_ios()
1934 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) { in msdc_ops_set_ios()
1935 regulator_disable(mmc->supply.vqmmc); in msdc_ops_set_ios()
1936 host->vqmmc_enabled = false; in msdc_ops_set_ios()
1943 if (host->mclk != ios->clock || host->timing != ios->timing) in msdc_ops_set_ios()
1944 msdc_set_mclk(host, ios->timing, ios->clock); in msdc_ops_set_ios()
1957 for (i = 0; i < (PAD_DELAY_FULL - start_bit); i++) { in get_delay_len()
1961 return PAD_DELAY_FULL - start_bit; in get_delay_len()
1964 static struct msdc_delay_phase get_best_delay(struct msdc_host *host, u64 delay) in get_best_delay() argument
1972 dev_err(host->dev, "phase error: [map:%016llx]\n", delay); in get_best_delay()
1993 dev_dbg(host->dev, "phase: [map:%016llx] [maxlen:%d] [final:%d]\n", in get_best_delay()
2002 static inline void msdc_set_cmd_delay(struct msdc_host *host, u32 value) in msdc_set_cmd_delay() argument
2004 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_cmd_delay()
2006 if (host->top_base) { in msdc_set_cmd_delay()
2008 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, value); in msdc_set_cmd_delay()
2009 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, 0); in msdc_set_cmd_delay()
2011 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY, in msdc_set_cmd_delay()
2012 PAD_DELAY_HALF - 1); in msdc_set_cmd_delay()
2013 sdr_set_field(host->top_base + EMMC_TOP_CMD, PAD_CMD_RXDLY2, in msdc_set_cmd_delay()
2014 value - PAD_DELAY_HALF); in msdc_set_cmd_delay()
2018 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, value); in msdc_set_cmd_delay()
2019 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_cmd_delay()
2022 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRDLY, in msdc_set_cmd_delay()
2023 PAD_DELAY_HALF - 1); in msdc_set_cmd_delay()
2024 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_cmd_delay()
2025 MSDC_PAD_TUNE_CMDRDLY2, value - PAD_DELAY_HALF); in msdc_set_cmd_delay()
2030 static inline void msdc_set_data_delay(struct msdc_host *host, u32 value) in msdc_set_data_delay() argument
2032 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_set_data_delay()
2034 if (host->top_base) { in msdc_set_data_delay()
2036 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2038 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2041 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2042 PAD_DAT_RD_RXDLY, PAD_DELAY_HALF - 1); in msdc_set_data_delay()
2043 sdr_set_field(host->top_base + EMMC_TOP_CONTROL, in msdc_set_data_delay()
2044 PAD_DAT_RD_RXDLY2, value - PAD_DELAY_HALF); in msdc_set_data_delay()
2048 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, value); in msdc_set_data_delay()
2049 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_data_delay()
2052 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_DATRRDLY, in msdc_set_data_delay()
2053 PAD_DELAY_HALF - 1); in msdc_set_data_delay()
2054 sdr_set_field(host->base + tune_reg + TUNING_REG2_FIXED_OFFEST, in msdc_set_data_delay()
2055 MSDC_PAD_TUNE_DATRRDLY2, value - PAD_DELAY_HALF); in msdc_set_data_delay()
2060 static int msdc_tune_response(struct mmc_host *mmc, u32 opcode) in msdc_tune_response() argument
2062 struct msdc_host *host = mmc_priv(mmc); in msdc_tune_response() local
2068 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_tune_response()
2072 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in msdc_tune_response()
2073 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in msdc_tune_response()
2074 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2076 host->hs200_cmd_int_delay); in msdc_tune_response()
2078 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2079 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2080 msdc_set_cmd_delay(host, i); in msdc_tune_response()
2087 mmc_send_tuning(mmc, opcode, &cmd_err); in msdc_tune_response()
2096 final_rise_delay = get_best_delay(host, rise_delay); in msdc_tune_response()
2102 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2103 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2104 msdc_set_cmd_delay(host, i); in msdc_tune_response()
2111 mmc_send_tuning(mmc, opcode, &cmd_err); in msdc_tune_response()
2120 final_fall_delay = get_best_delay(host, fall_delay); in msdc_tune_response()
2127 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2130 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_response()
2133 msdc_set_cmd_delay(host, final_delay); in msdc_tune_response()
2135 if (host->dev_comp->async_fifo || host->hs200_cmd_int_delay) in msdc_tune_response()
2138 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_response()
2139 sdr_set_field(host->base + tune_reg, in msdc_tune_response()
2141 mmc_send_tuning(mmc, opcode, &cmd_err); in msdc_tune_response()
2145 dev_dbg(host->dev, "Final internal delay: 0x%x\n", internal_delay); in msdc_tune_response()
2146 internal_delay_phase = get_best_delay(host, internal_delay); in msdc_tune_response()
2147 sdr_set_field(host->base + tune_reg, MSDC_PAD_TUNE_CMDRRDLY, in msdc_tune_response()
2150 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in msdc_tune_response()
2151 return final_delay == 0xff ? -EIO : 0; in msdc_tune_response()
2154 static int hs400_tune_response(struct mmc_host *mmc, u32 opcode) in hs400_tune_response() argument
2156 struct msdc_host *host = mmc_priv(mmc); in hs400_tune_response() local
2164 sdr_set_bits(host->base + PAD_CMD_TUNE, BIT(0)); in hs400_tune_response()
2165 sdr_set_field(host->base + MSDC_PATCH_BIT1, MSDC_PATCH_BIT1_CMDTA, 2); in hs400_tune_response()
2167 if (mmc->ios.timing == MMC_TIMING_MMC_HS200 || in hs400_tune_response()
2168 mmc->ios.timing == MMC_TIMING_UHS_SDR104) in hs400_tune_response()
2169 sdr_set_field(host->base + MSDC_PAD_TUNE, in hs400_tune_response()
2171 host->hs200_cmd_int_delay); in hs400_tune_response()
2173 if (host->hs400_cmd_resp_sel_rising) in hs400_tune_response()
2174 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2176 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in hs400_tune_response()
2179 sdr_set_field(host->base + PAD_CMD_TUNE, in hs400_tune_response()
2187 mmc_send_tuning(mmc, opcode, &cmd_err); in hs400_tune_response()
2196 final_cmd_delay = get_best_delay(host, cmd_delay); in hs400_tune_response()
2197 sdr_set_field(host->base + PAD_CMD_TUNE, PAD_CMD_TUNE_RX_DLY3, in hs400_tune_response()
2201 dev_dbg(host->dev, "Final cmd pad delay: %x\n", final_delay); in hs400_tune_response()
2202 return final_delay == 0xff ? -EIO : 0; in hs400_tune_response()
2205 static int msdc_tune_data(struct mmc_host *mmc, u32 opcode) in msdc_tune_data() argument
2207 struct msdc_host *host = mmc_priv(mmc); in msdc_tune_data() local
2213 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_data()
2214 host->latch_ck); in msdc_tune_data()
2215 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2216 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2217 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_data()
2218 msdc_set_data_delay(host, i); in msdc_tune_data()
2219 ret = mmc_send_tuning(mmc, opcode, NULL); in msdc_tune_data()
2223 final_rise_delay = get_best_delay(host, rise_delay); in msdc_tune_data()
2229 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2230 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2231 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_data()
2232 msdc_set_data_delay(host, i); in msdc_tune_data()
2233 ret = mmc_send_tuning(mmc, opcode, NULL); in msdc_tune_data()
2237 final_fall_delay = get_best_delay(host, fall_delay); in msdc_tune_data()
2242 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2243 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2246 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_DSPL); in msdc_tune_data()
2247 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_W_DSPL); in msdc_tune_data()
2250 msdc_set_data_delay(host, final_delay); in msdc_tune_data()
2252 dev_dbg(host->dev, "Final data pad delay: %x\n", final_delay); in msdc_tune_data()
2253 return final_delay == 0xff ? -EIO : 0; in msdc_tune_data()
2260 static int msdc_tune_together(struct mmc_host *mmc, u32 opcode) in msdc_tune_together() argument
2262 struct msdc_host *host = mmc_priv(mmc); in msdc_tune_together() local
2268 sdr_set_field(host->base + MSDC_PATCH_BIT, MSDC_INT_DAT_LATCH_CK_SEL, in msdc_tune_together()
2269 host->latch_ck); in msdc_tune_together()
2271 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2272 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2274 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_together()
2275 msdc_set_cmd_delay(host, i); in msdc_tune_together()
2276 msdc_set_data_delay(host, i); in msdc_tune_together()
2277 ret = mmc_send_tuning(mmc, opcode, NULL); in msdc_tune_together()
2281 final_rise_delay = get_best_delay(host, rise_delay); in msdc_tune_together()
2287 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2288 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2290 for (i = 0; i < host->tuning_step; i++) { in msdc_tune_together()
2291 msdc_set_cmd_delay(host, i); in msdc_tune_together()
2292 msdc_set_data_delay(host, i); in msdc_tune_together()
2293 ret = mmc_send_tuning(mmc, opcode, NULL); in msdc_tune_together()
2297 final_fall_delay = get_best_delay(host, fall_delay); in msdc_tune_together()
2302 sdr_clr_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2303 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2307 sdr_set_bits(host->base + MSDC_IOCON, MSDC_IOCON_RSPL); in msdc_tune_together()
2308 sdr_set_bits(host->base + MSDC_IOCON, in msdc_tune_together()
2313 msdc_set_cmd_delay(host, final_delay); in msdc_tune_together()
2314 msdc_set_data_delay(host, final_delay); in msdc_tune_together()
2316 dev_dbg(host->dev, "Final pad delay: %x\n", final_delay); in msdc_tune_together()
2317 return final_delay == 0xff ? -EIO : 0; in msdc_tune_together()
2320 static int msdc_execute_tuning(struct mmc_host *mmc, u32 opcode) in msdc_execute_tuning() argument
2322 struct msdc_host *host = mmc_priv(mmc); in msdc_execute_tuning() local
2324 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_execute_tuning()
2326 if (host->dev_comp->data_tune && host->dev_comp->async_fifo) { in msdc_execute_tuning()
2327 ret = msdc_tune_together(mmc, opcode); in msdc_execute_tuning()
2328 if (host->hs400_mode) { in msdc_execute_tuning()
2329 sdr_clr_bits(host->base + MSDC_IOCON, in msdc_execute_tuning()
2331 msdc_set_data_delay(host, 0); in msdc_execute_tuning()
2335 if (host->hs400_mode && in msdc_execute_tuning()
2336 host->dev_comp->hs400_tune) in msdc_execute_tuning()
2337 ret = hs400_tune_response(mmc, opcode); in msdc_execute_tuning()
2339 ret = msdc_tune_response(mmc, opcode); in msdc_execute_tuning()
2340 if (ret == -EIO) { in msdc_execute_tuning()
2341 dev_err(host->dev, "Tune response fail!\n"); in msdc_execute_tuning()
2344 if (host->hs400_mode == false) { in msdc_execute_tuning()
2345 ret = msdc_tune_data(mmc, opcode); in msdc_execute_tuning()
2346 if (ret == -EIO) in msdc_execute_tuning()
2347 dev_err(host->dev, "Tune data fail!\n"); in msdc_execute_tuning()
2351 host->saved_tune_para.iocon = readl(host->base + MSDC_IOCON); in msdc_execute_tuning()
2352 host->saved_tune_para.pad_tune = readl(host->base + tune_reg); in msdc_execute_tuning()
2353 host->saved_tune_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_execute_tuning()
2354 if (host->top_base) { in msdc_execute_tuning()
2355 host->saved_tune_para.emmc_top_control = readl(host->top_base + in msdc_execute_tuning()
2357 host->saved_tune_para.emmc_top_cmd = readl(host->top_base + in msdc_execute_tuning()
2363 static int msdc_prepare_hs400_tuning(struct mmc_host *mmc, struct mmc_ios *ios) in msdc_prepare_hs400_tuning() argument
2365 struct msdc_host *host = mmc_priv(mmc); in msdc_prepare_hs400_tuning() local
2366 host->hs400_mode = true; in msdc_prepare_hs400_tuning()
2368 if (host->top_base) in msdc_prepare_hs400_tuning()
2369 writel(host->hs400_ds_delay, in msdc_prepare_hs400_tuning()
2370 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2372 writel(host->hs400_ds_delay, host->base + PAD_DS_TUNE); in msdc_prepare_hs400_tuning()
2374 sdr_clr_bits(host->base + MSDC_PATCH_BIT2, MSDC_PATCH_BIT2_CFGCRCSTS); in msdc_prepare_hs400_tuning()
2376 sdr_set_field(host->base + EMMC50_CFG3, EMMC50_CFG3_OUTS_WR, 2); in msdc_prepare_hs400_tuning()
2381 static int msdc_execute_hs400_tuning(struct mmc_host *mmc, struct mmc_card *card) in msdc_execute_hs400_tuning() argument
2383 struct msdc_host *host = mmc_priv(mmc); in msdc_execute_hs400_tuning() local
2389 if (host->top_base) { in msdc_execute_hs400_tuning()
2390 sdr_set_bits(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2392 if (host->hs400_ds_dly3) in msdc_execute_hs400_tuning()
2393 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2394 PAD_DS_DLY3, host->hs400_ds_dly3); in msdc_execute_hs400_tuning()
2396 sdr_set_bits(host->base + PAD_DS_TUNE, PAD_DS_TUNE_DLY_SEL); in msdc_execute_hs400_tuning()
2397 if (host->hs400_ds_dly3) in msdc_execute_hs400_tuning()
2398 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2399 PAD_DS_TUNE_DLY3, host->hs400_ds_dly3); in msdc_execute_hs400_tuning()
2402 host->hs400_tuning = true; in msdc_execute_hs400_tuning()
2404 if (host->top_base) in msdc_execute_hs400_tuning()
2405 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2408 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2416 host->hs400_tuning = false; in msdc_execute_hs400_tuning()
2418 dly1_delay = get_best_delay(host, result_dly1); in msdc_execute_hs400_tuning()
2420 dev_err(host->dev, "Failed to get DLY1 delay!\n"); in msdc_execute_hs400_tuning()
2423 if (host->top_base) in msdc_execute_hs400_tuning()
2424 sdr_set_field(host->top_base + EMMC50_PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2427 sdr_set_field(host->base + PAD_DS_TUNE, in msdc_execute_hs400_tuning()
2430 if (host->top_base) in msdc_execute_hs400_tuning()
2431 val = readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2433 val = readl(host->base + PAD_DS_TUNE); in msdc_execute_hs400_tuning()
2435 dev_info(host->dev, "Final PAD_DS_TUNE: 0x%x\n", val); in msdc_execute_hs400_tuning()
2440 dev_err(host->dev, "Failed to tuning DS pin delay!\n"); in msdc_execute_hs400_tuning()
2441 return -EIO; in msdc_execute_hs400_tuning()
2444 static void msdc_hw_reset(struct mmc_host *mmc) in msdc_hw_reset() argument
2446 struct msdc_host *host = mmc_priv(mmc); in msdc_hw_reset() local
2448 sdr_set_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2450 sdr_clr_bits(host->base + EMMC_IOCON, 1); in msdc_hw_reset()
2453 static void msdc_ack_sdio_irq(struct mmc_host *mmc) in msdc_ack_sdio_irq() argument
2456 struct msdc_host *host = mmc_priv(mmc); in msdc_ack_sdio_irq() local
2458 spin_lock_irqsave(&host->lock, flags); in msdc_ack_sdio_irq()
2459 __msdc_enable_sdio_irq(host, 1); in msdc_ack_sdio_irq()
2460 spin_unlock_irqrestore(&host->lock, flags); in msdc_ack_sdio_irq()
2463 static int msdc_get_cd(struct mmc_host *mmc) in msdc_get_cd() argument
2465 struct msdc_host *host = mmc_priv(mmc); in msdc_get_cd() local
2468 if (mmc->caps & MMC_CAP_NONREMOVABLE) in msdc_get_cd()
2471 if (!host->internal_cd) in msdc_get_cd()
2472 return mmc_gpio_get_cd(mmc); in msdc_get_cd()
2474 val = readl(host->base + MSDC_PS) & MSDC_PS_CDSTS; in msdc_get_cd()
2475 if (mmc->caps2 & MMC_CAP2_CD_ACTIVE_HIGH) in msdc_get_cd()
2481 static void msdc_hs400_enhanced_strobe(struct mmc_host *mmc, in msdc_hs400_enhanced_strobe() argument
2484 struct msdc_host *host = mmc_priv(mmc); in msdc_hs400_enhanced_strobe() local
2486 if (ios->enhanced_strobe) { in msdc_hs400_enhanced_strobe()
2487 msdc_prepare_hs400_tuning(mmc, ios); in msdc_hs400_enhanced_strobe()
2488 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 1); in msdc_hs400_enhanced_strobe()
2489 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 1); in msdc_hs400_enhanced_strobe()
2490 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 1); in msdc_hs400_enhanced_strobe()
2492 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2493 sdr_clr_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2494 sdr_clr_bits(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT); in msdc_hs400_enhanced_strobe()
2496 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_PADCMD_LATCHCK, 0); in msdc_hs400_enhanced_strobe()
2497 sdr_set_field(host->base + EMMC50_CFG0, EMMC50_CFG_CMD_RESP_SEL, 0); in msdc_hs400_enhanced_strobe()
2498 sdr_set_field(host->base + EMMC50_CFG1, EMMC50_CFG1_DS_CFG, 0); in msdc_hs400_enhanced_strobe()
2500 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_RD_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2501 sdr_set_bits(host->base + CQHCI_SETTING, CQHCI_WR_CMD_WND_SEL); in msdc_hs400_enhanced_strobe()
2502 sdr_set_field(host->base + EMMC51_CFG0, CMDQ_RDAT_CNT, 0xb4); in msdc_hs400_enhanced_strobe()
2506 static void msdc_cqe_cit_cal(struct msdc_host *host, u64 timer_ns) in msdc_cqe_cit_cal() argument
2508 struct mmc_host *mmc = mmc_from_priv(host); in msdc_cqe_cit_cal() local
2509 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_cit_cal()
2518 hclk_freq = (u64)clk_get_rate(host->h_clk); in msdc_cqe_cit_cal()
2536 host->cq_ssc1_time = 0x40; in msdc_cqe_cit_cal()
2542 host->cq_ssc1_time = value; in msdc_cqe_cit_cal()
2545 static void msdc_cqe_enable(struct mmc_host *mmc) in msdc_cqe_enable() argument
2547 struct msdc_host *host = mmc_priv(mmc); in msdc_cqe_enable() local
2548 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_enable()
2551 writel(MSDC_INT_CMDQ, host->base + MSDC_INTEN); in msdc_cqe_enable()
2553 sdr_set_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_enable()
2555 msdc_set_busy_timeout(host, 20 * 1000000000ULL, 0); in msdc_cqe_enable()
2557 msdc_set_timeout(host, 1000000000ULL, 0); in msdc_cqe_enable()
2560 cqhci_writel(cq_host, host->cq_ssc1_time, CQHCI_SSC1); in msdc_cqe_enable()
2563 static void msdc_cqe_disable(struct mmc_host *mmc, bool recovery) in msdc_cqe_disable() argument
2565 struct msdc_host *host = mmc_priv(mmc); in msdc_cqe_disable() local
2569 sdr_clr_bits(host->base + MSDC_INTEN, MSDC_INT_CMDQ); in msdc_cqe_disable()
2571 sdr_clr_bits(host->base + MSDC_PATCH_BIT1, MSDC_PB1_BUSY_CHECK_SEL); in msdc_cqe_disable()
2573 val = readl(host->base + MSDC_INT); in msdc_cqe_disable()
2574 writel(val, host->base + MSDC_INT); in msdc_cqe_disable()
2577 sdr_set_field(host->base + MSDC_DMA_CTRL, in msdc_cqe_disable()
2579 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CTRL, val, in msdc_cqe_disable()
2582 if (WARN_ON(readl_poll_timeout(host->base + MSDC_DMA_CFG, val, in msdc_cqe_disable()
2585 msdc_reset_hw(host); in msdc_cqe_disable()
2589 static void msdc_cqe_pre_enable(struct mmc_host *mmc) in msdc_cqe_pre_enable() argument
2591 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_pre_enable()
2599 static void msdc_cqe_post_disable(struct mmc_host *mmc) in msdc_cqe_post_disable() argument
2601 struct cqhci_host *cq_host = mmc->cqe_private; in msdc_cqe_post_disable()
2635 struct msdc_host *host) in msdc_of_property_parse() argument
2637 struct mmc_host *mmc = mmc_from_priv(host); in msdc_of_property_parse() local
2639 of_property_read_u32(pdev->dev.of_node, "mediatek,latch-ck", in msdc_of_property_parse()
2640 &host->latch_ck); in msdc_of_property_parse()
2642 of_property_read_u32(pdev->dev.of_node, "hs400-ds-delay", in msdc_of_property_parse()
2643 &host->hs400_ds_delay); in msdc_of_property_parse()
2645 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-ds-dly3", in msdc_of_property_parse()
2646 &host->hs400_ds_dly3); in msdc_of_property_parse()
2648 of_property_read_u32(pdev->dev.of_node, "mediatek,hs200-cmd-int-delay", in msdc_of_property_parse()
2649 &host->hs200_cmd_int_delay); in msdc_of_property_parse()
2651 of_property_read_u32(pdev->dev.of_node, "mediatek,hs400-cmd-int-delay", in msdc_of_property_parse()
2652 &host->hs400_cmd_int_delay); in msdc_of_property_parse()
2654 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2655 "mediatek,hs400-cmd-resp-sel-rising")) in msdc_of_property_parse()
2656 host->hs400_cmd_resp_sel_rising = true; in msdc_of_property_parse()
2658 host->hs400_cmd_resp_sel_rising = false; in msdc_of_property_parse()
2660 if (of_property_read_u32(pdev->dev.of_node, "mediatek,tuning-step", in msdc_of_property_parse()
2661 &host->tuning_step)) { in msdc_of_property_parse()
2662 if (mmc->caps2 & MMC_CAP2_NO_MMC) in msdc_of_property_parse()
2663 host->tuning_step = PAD_DELAY_FULL; in msdc_of_property_parse()
2665 host->tuning_step = PAD_DELAY_HALF; in msdc_of_property_parse()
2668 if (of_property_read_bool(pdev->dev.of_node, in msdc_of_property_parse()
2669 "supports-cqe")) in msdc_of_property_parse()
2670 host->cqhci = true; in msdc_of_property_parse()
2672 host->cqhci = false; in msdc_of_property_parse()
2676 struct msdc_host *host) in msdc_of_clock_parse() argument
2680 host->src_clk = devm_clk_get(&pdev->dev, "source"); in msdc_of_clock_parse()
2681 if (IS_ERR(host->src_clk)) in msdc_of_clock_parse()
2682 return PTR_ERR(host->src_clk); in msdc_of_clock_parse()
2684 host->h_clk = devm_clk_get(&pdev->dev, "hclk"); in msdc_of_clock_parse()
2685 if (IS_ERR(host->h_clk)) in msdc_of_clock_parse()
2686 return PTR_ERR(host->h_clk); in msdc_of_clock_parse()
2688 host->bus_clk = devm_clk_get_optional(&pdev->dev, "bus_clk"); in msdc_of_clock_parse()
2689 if (IS_ERR(host->bus_clk)) in msdc_of_clock_parse()
2690 host->bus_clk = NULL; in msdc_of_clock_parse()
2693 host->src_clk_cg = devm_clk_get_optional(&pdev->dev, "source_cg"); in msdc_of_clock_parse()
2694 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2695 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2698 * Fallback for legacy device-trees: src_clk and HCLK use the same in msdc_of_clock_parse()
2704 if (!host->src_clk_cg) { in msdc_of_clock_parse()
2705 host->src_clk_cg = clk_get_parent(host->src_clk); in msdc_of_clock_parse()
2706 if (IS_ERR(host->src_clk_cg)) in msdc_of_clock_parse()
2707 return PTR_ERR(host->src_clk_cg); in msdc_of_clock_parse()
2711 host->sys_clk_cg = devm_clk_get_optional_enabled(&pdev->dev, "sys_cg"); in msdc_of_clock_parse()
2712 if (IS_ERR(host->sys_clk_cg)) in msdc_of_clock_parse()
2713 host->sys_clk_cg = NULL; in msdc_of_clock_parse()
2715 host->bulk_clks[0].id = "pclk_cg"; in msdc_of_clock_parse()
2716 host->bulk_clks[1].id = "axi_cg"; in msdc_of_clock_parse()
2717 host->bulk_clks[2].id = "ahb_cg"; in msdc_of_clock_parse()
2718 ret = devm_clk_bulk_get_optional(&pdev->dev, MSDC_NR_CLOCKS, in msdc_of_clock_parse()
2719 host->bulk_clks); in msdc_of_clock_parse()
2721 dev_err(&pdev->dev, "Cannot get pclk/axi/ahb clock gates\n"); in msdc_of_clock_parse()
2730 struct mmc_host *mmc; in msdc_drv_probe() local
2731 struct msdc_host *host; in msdc_drv_probe() local
2735 if (!pdev->dev.of_node) { in msdc_drv_probe()
2736 dev_err(&pdev->dev, "No DT found\n"); in msdc_drv_probe()
2737 return -EINVAL; in msdc_drv_probe()
2740 /* Allocate MMC host for this device */ in msdc_drv_probe()
2741 mmc = mmc_alloc_host(sizeof(struct msdc_host), &pdev->dev); in msdc_drv_probe()
2742 if (!mmc) in msdc_drv_probe()
2743 return -ENOMEM; in msdc_drv_probe()
2745 host = mmc_priv(mmc); in msdc_drv_probe()
2746 ret = mmc_of_parse(mmc); in msdc_drv_probe()
2750 host->base = devm_platform_ioremap_resource(pdev, 0); in msdc_drv_probe()
2751 if (IS_ERR(host->base)) { in msdc_drv_probe()
2752 ret = PTR_ERR(host->base); in msdc_drv_probe()
2758 host->top_base = devm_ioremap_resource(&pdev->dev, res); in msdc_drv_probe()
2759 if (IS_ERR(host->top_base)) in msdc_drv_probe()
2760 host->top_base = NULL; in msdc_drv_probe()
2763 ret = mmc_regulator_get_supply(mmc); in msdc_drv_probe()
2767 ret = msdc_of_clock_parse(pdev, host); in msdc_drv_probe()
2771 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, in msdc_drv_probe()
2773 if (IS_ERR(host->reset)) { in msdc_drv_probe()
2774 ret = PTR_ERR(host->reset); in msdc_drv_probe()
2779 if (!(mmc->caps2 & MMC_CAP2_NO_MMC)) { in msdc_drv_probe()
2780 host->crypto_clk = devm_clk_get_optional(&pdev->dev, "crypto"); in msdc_drv_probe()
2781 if (IS_ERR(host->crypto_clk)) in msdc_drv_probe()
2782 host->crypto_clk = NULL; in msdc_drv_probe()
2784 mmc->caps2 |= MMC_CAP2_CRYPTO; in msdc_drv_probe()
2787 host->irq = platform_get_irq(pdev, 0); in msdc_drv_probe()
2788 if (host->irq < 0) { in msdc_drv_probe()
2789 ret = host->irq; in msdc_drv_probe()
2793 host->pinctrl = devm_pinctrl_get(&pdev->dev); in msdc_drv_probe()
2794 if (IS_ERR(host->pinctrl)) { in msdc_drv_probe()
2795 ret = PTR_ERR(host->pinctrl); in msdc_drv_probe()
2796 dev_err(&pdev->dev, "Cannot find pinctrl!\n"); in msdc_drv_probe()
2800 host->pins_default = pinctrl_lookup_state(host->pinctrl, "default"); in msdc_drv_probe()
2801 if (IS_ERR(host->pins_default)) { in msdc_drv_probe()
2802 ret = PTR_ERR(host->pins_default); in msdc_drv_probe()
2803 dev_err(&pdev->dev, "Cannot find pinctrl default!\n"); in msdc_drv_probe()
2807 host->pins_uhs = pinctrl_lookup_state(host->pinctrl, "state_uhs"); in msdc_drv_probe()
2808 if (IS_ERR(host->pins_uhs)) { in msdc_drv_probe()
2809 ret = PTR_ERR(host->pins_uhs); in msdc_drv_probe()
2810 dev_err(&pdev->dev, "Cannot find pinctrl uhs!\n"); in msdc_drv_probe()
2815 if ((mmc->pm_caps & MMC_PM_WAKE_SDIO_IRQ) && (mmc->pm_caps & MMC_PM_KEEP_POWER)) { in msdc_drv_probe()
2816 host->eint_irq = platform_get_irq_byname_optional(pdev, "sdio_wakeup"); in msdc_drv_probe()
2817 if (host->eint_irq > 0) { in msdc_drv_probe()
2818 host->pins_eint = pinctrl_lookup_state(host->pinctrl, "state_eint"); in msdc_drv_probe()
2819 if (IS_ERR(host->pins_eint)) { in msdc_drv_probe()
2820 dev_err(&pdev->dev, "Cannot find pinctrl eint!\n"); in msdc_drv_probe()
2821 host->pins_eint = NULL; in msdc_drv_probe()
2823 device_init_wakeup(&pdev->dev, true); in msdc_drv_probe()
2828 msdc_of_property_parse(pdev, host); in msdc_drv_probe()
2830 host->dev = &pdev->dev; in msdc_drv_probe()
2831 host->dev_comp = of_device_get_match_data(&pdev->dev); in msdc_drv_probe()
2832 host->src_clk_freq = clk_get_rate(host->src_clk); in msdc_drv_probe()
2833 /* Set host parameters to mmc */ in msdc_drv_probe()
2834 mmc->ops = &mt_msdc_ops; in msdc_drv_probe()
2835 if (host->dev_comp->clk_div_bits == 8) in msdc_drv_probe()
2836 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 255); in msdc_drv_probe()
2838 mmc->f_min = DIV_ROUND_UP(host->src_clk_freq, 4 * 4095); in msdc_drv_probe()
2840 if (!(mmc->caps & MMC_CAP_NONREMOVABLE) && in msdc_drv_probe()
2841 !mmc_can_gpio_cd(mmc) && in msdc_drv_probe()
2842 host->dev_comp->use_internal_cd) { in msdc_drv_probe()
2847 host->internal_cd = true; in msdc_drv_probe()
2850 if (mmc->caps & MMC_CAP_SDIO_IRQ) in msdc_drv_probe()
2851 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in msdc_drv_probe()
2853 mmc->caps |= MMC_CAP_CMD23; in msdc_drv_probe()
2854 if (host->cqhci) in msdc_drv_probe()
2855 mmc->caps2 |= MMC_CAP2_CQE | MMC_CAP2_CQE_DCMD; in msdc_drv_probe()
2856 /* MMC core transfer sizes tunable parameters */ in msdc_drv_probe()
2857 mmc->max_segs = MAX_BD_NUM; in msdc_drv_probe()
2858 if (host->dev_comp->support_64g) in msdc_drv_probe()
2859 mmc->max_seg_size = BDMA_DESC_BUFLEN_EXT; in msdc_drv_probe()
2861 mmc->max_seg_size = BDMA_DESC_BUFLEN; in msdc_drv_probe()
2862 mmc->max_blk_size = 2048; in msdc_drv_probe()
2863 mmc->max_req_size = 512 * 1024; in msdc_drv_probe()
2864 mmc->max_blk_count = mmc->max_req_size / 512; in msdc_drv_probe()
2865 if (host->dev_comp->support_64g) in msdc_drv_probe()
2866 host->dma_mask = DMA_BIT_MASK(36); in msdc_drv_probe()
2868 host->dma_mask = DMA_BIT_MASK(32); in msdc_drv_probe()
2869 mmc_dev(mmc)->dma_mask = &host->dma_mask; in msdc_drv_probe()
2871 host->timeout_clks = 3 * 1048576; in msdc_drv_probe()
2872 host->dma.gpd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2874 &host->dma.gpd_addr, GFP_KERNEL); in msdc_drv_probe()
2875 host->dma.bd = dma_alloc_coherent(&pdev->dev, in msdc_drv_probe()
2877 &host->dma.bd_addr, GFP_KERNEL); in msdc_drv_probe()
2878 if (!host->dma.gpd || !host->dma.bd) { in msdc_drv_probe()
2879 ret = -ENOMEM; in msdc_drv_probe()
2882 msdc_init_gpd_bd(host, &host->dma); in msdc_drv_probe()
2883 INIT_DELAYED_WORK(&host->req_timeout, msdc_request_timeout); in msdc_drv_probe()
2884 spin_lock_init(&host->lock); in msdc_drv_probe()
2886 platform_set_drvdata(pdev, mmc); in msdc_drv_probe()
2887 ret = msdc_ungate_clock(host); in msdc_drv_probe()
2889 dev_err(&pdev->dev, "Cannot ungate clocks!\n"); in msdc_drv_probe()
2892 msdc_init_hw(host); in msdc_drv_probe()
2894 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_drv_probe()
2895 host->cq_host = devm_kzalloc(mmc->parent, in msdc_drv_probe()
2896 sizeof(*host->cq_host), in msdc_drv_probe()
2898 if (!host->cq_host) { in msdc_drv_probe()
2899 ret = -ENOMEM; in msdc_drv_probe()
2902 host->cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in msdc_drv_probe()
2903 host->cq_host->mmio = host->base + 0x800; in msdc_drv_probe()
2904 host->cq_host->ops = &msdc_cmdq_ops; in msdc_drv_probe()
2905 ret = cqhci_init(host->cq_host, mmc, true); in msdc_drv_probe()
2908 mmc->max_segs = 128; in msdc_drv_probe()
2910 /* 0 size, means 65536 so we don't have to -1 here */ in msdc_drv_probe()
2911 mmc->max_seg_size = 64 * 1024; in msdc_drv_probe()
2913 msdc_cqe_cit_cal(host, 2350); in msdc_drv_probe()
2916 ret = devm_request_irq(&pdev->dev, host->irq, msdc_irq, in msdc_drv_probe()
2917 IRQF_TRIGGER_NONE, pdev->name, host); in msdc_drv_probe()
2921 pm_runtime_set_active(host->dev); in msdc_drv_probe()
2922 pm_runtime_set_autosuspend_delay(host->dev, MTK_MMC_AUTOSUSPEND_DELAY); in msdc_drv_probe()
2923 pm_runtime_use_autosuspend(host->dev); in msdc_drv_probe()
2924 pm_runtime_enable(host->dev); in msdc_drv_probe()
2925 ret = mmc_add_host(mmc); in msdc_drv_probe()
2932 pm_runtime_disable(host->dev); in msdc_drv_probe()
2935 msdc_deinit_hw(host); in msdc_drv_probe()
2936 msdc_gate_clock(host); in msdc_drv_probe()
2938 if (host->dma.gpd) in msdc_drv_probe()
2939 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2941 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_probe()
2942 if (host->dma.bd) in msdc_drv_probe()
2943 dma_free_coherent(&pdev->dev, in msdc_drv_probe()
2945 host->dma.bd, host->dma.bd_addr); in msdc_drv_probe()
2947 mmc_free_host(mmc); in msdc_drv_probe()
2954 struct mmc_host *mmc; in msdc_drv_remove() local
2955 struct msdc_host *host; in msdc_drv_remove() local
2957 mmc = platform_get_drvdata(pdev); in msdc_drv_remove()
2958 host = mmc_priv(mmc); in msdc_drv_remove()
2960 pm_runtime_get_sync(host->dev); in msdc_drv_remove()
2963 mmc_remove_host(mmc); in msdc_drv_remove()
2964 msdc_deinit_hw(host); in msdc_drv_remove()
2965 msdc_gate_clock(host); in msdc_drv_remove()
2967 pm_runtime_disable(host->dev); in msdc_drv_remove()
2968 pm_runtime_put_noidle(host->dev); in msdc_drv_remove()
2969 dma_free_coherent(&pdev->dev, in msdc_drv_remove()
2971 host->dma.gpd, host->dma.gpd_addr); in msdc_drv_remove()
2972 dma_free_coherent(&pdev->dev, MAX_BD_NUM * sizeof(struct mt_bdma_desc), in msdc_drv_remove()
2973 host->dma.bd, host->dma.bd_addr); in msdc_drv_remove()
2975 mmc_free_host(mmc); in msdc_drv_remove()
2978 static void msdc_save_reg(struct msdc_host *host) in msdc_save_reg() argument
2980 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_save_reg()
2982 host->save_para.msdc_cfg = readl(host->base + MSDC_CFG); in msdc_save_reg()
2983 host->save_para.iocon = readl(host->base + MSDC_IOCON); in msdc_save_reg()
2984 host->save_para.sdc_cfg = readl(host->base + SDC_CFG); in msdc_save_reg()
2985 host->save_para.patch_bit0 = readl(host->base + MSDC_PATCH_BIT); in msdc_save_reg()
2986 host->save_para.patch_bit1 = readl(host->base + MSDC_PATCH_BIT1); in msdc_save_reg()
2987 host->save_para.patch_bit2 = readl(host->base + MSDC_PATCH_BIT2); in msdc_save_reg()
2988 host->save_para.pad_ds_tune = readl(host->base + PAD_DS_TUNE); in msdc_save_reg()
2989 host->save_para.pad_cmd_tune = readl(host->base + PAD_CMD_TUNE); in msdc_save_reg()
2990 host->save_para.emmc50_cfg0 = readl(host->base + EMMC50_CFG0); in msdc_save_reg()
2991 host->save_para.emmc50_cfg3 = readl(host->base + EMMC50_CFG3); in msdc_save_reg()
2992 host->save_para.sdc_fifo_cfg = readl(host->base + SDC_FIFO_CFG); in msdc_save_reg()
2993 if (host->top_base) { in msdc_save_reg()
2994 host->save_para.emmc_top_control = in msdc_save_reg()
2995 readl(host->top_base + EMMC_TOP_CONTROL); in msdc_save_reg()
2996 host->save_para.emmc_top_cmd = in msdc_save_reg()
2997 readl(host->top_base + EMMC_TOP_CMD); in msdc_save_reg()
2998 host->save_para.emmc50_pad_ds_tune = in msdc_save_reg()
2999 readl(host->top_base + EMMC50_PAD_DS_TUNE); in msdc_save_reg()
3001 host->save_para.pad_tune = readl(host->base + tune_reg); in msdc_save_reg()
3005 static void msdc_restore_reg(struct msdc_host *host) in msdc_restore_reg() argument
3007 struct mmc_host *mmc = mmc_from_priv(host); in msdc_restore_reg() local
3008 u32 tune_reg = host->dev_comp->pad_tune_reg; in msdc_restore_reg()
3010 writel(host->save_para.msdc_cfg, host->base + MSDC_CFG); in msdc_restore_reg()
3011 writel(host->save_para.iocon, host->base + MSDC_IOCON); in msdc_restore_reg()
3012 writel(host->save_para.sdc_cfg, host->base + SDC_CFG); in msdc_restore_reg()
3013 writel(host->save_para.patch_bit0, host->base + MSDC_PATCH_BIT); in msdc_restore_reg()
3014 writel(host->save_para.patch_bit1, host->base + MSDC_PATCH_BIT1); in msdc_restore_reg()
3015 writel(host->save_para.patch_bit2, host->base + MSDC_PATCH_BIT2); in msdc_restore_reg()
3016 writel(host->save_para.pad_ds_tune, host->base + PAD_DS_TUNE); in msdc_restore_reg()
3017 writel(host->save_para.pad_cmd_tune, host->base + PAD_CMD_TUNE); in msdc_restore_reg()
3018 writel(host->save_para.emmc50_cfg0, host->base + EMMC50_CFG0); in msdc_restore_reg()
3019 writel(host->save_para.emmc50_cfg3, host->base + EMMC50_CFG3); in msdc_restore_reg()
3020 writel(host->save_para.sdc_fifo_cfg, host->base + SDC_FIFO_CFG); in msdc_restore_reg()
3021 if (host->top_base) { in msdc_restore_reg()
3022 writel(host->save_para.emmc_top_control, in msdc_restore_reg()
3023 host->top_base + EMMC_TOP_CONTROL); in msdc_restore_reg()
3024 writel(host->save_para.emmc_top_cmd, in msdc_restore_reg()
3025 host->top_base + EMMC_TOP_CMD); in msdc_restore_reg()
3026 writel(host->save_para.emmc50_pad_ds_tune, in msdc_restore_reg()
3027 host->top_base + EMMC50_PAD_DS_TUNE); in msdc_restore_reg()
3029 writel(host->save_para.pad_tune, host->base + tune_reg); in msdc_restore_reg()
3032 if (sdio_irq_claimed(mmc)) in msdc_restore_reg()
3033 __msdc_enable_sdio_irq(host, 1); in msdc_restore_reg()
3038 struct mmc_host *mmc = dev_get_drvdata(dev); in msdc_runtime_suspend() local
3039 struct msdc_host *host = mmc_priv(mmc); in msdc_runtime_suspend() local
3041 msdc_save_reg(host); in msdc_runtime_suspend()
3043 if (sdio_irq_claimed(mmc)) { in msdc_runtime_suspend()
3044 if (host->pins_eint) { in msdc_runtime_suspend()
3045 disable_irq(host->irq); in msdc_runtime_suspend()
3046 pinctrl_select_state(host->pinctrl, host->pins_eint); in msdc_runtime_suspend()
3049 __msdc_enable_sdio_irq(host, 0); in msdc_runtime_suspend()
3051 msdc_gate_clock(host); in msdc_runtime_suspend()
3057 struct mmc_host *mmc = dev_get_drvdata(dev); in msdc_runtime_resume() local
3058 struct msdc_host *host = mmc_priv(mmc); in msdc_runtime_resume() local
3061 ret = msdc_ungate_clock(host); in msdc_runtime_resume()
3065 msdc_restore_reg(host); in msdc_runtime_resume()
3067 if (sdio_irq_claimed(mmc) && host->pins_eint) { in msdc_runtime_resume()
3068 pinctrl_select_state(host->pinctrl, host->pins_uhs); in msdc_runtime_resume()
3069 enable_irq(host->irq); in msdc_runtime_resume()
3076 struct mmc_host *mmc = dev_get_drvdata(dev); in msdc_suspend() local
3077 struct msdc_host *host = mmc_priv(mmc); in msdc_suspend() local
3081 if (mmc->caps2 & MMC_CAP2_CQE) { in msdc_suspend()
3082 ret = cqhci_suspend(mmc); in msdc_suspend()
3085 val = readl(host->base + MSDC_INT); in msdc_suspend()
3086 writel(val, host->base + MSDC_INT); in msdc_suspend()
3090 * Bump up runtime PM usage counter otherwise dev->power.needs_force_resume will in msdc_suspend()
3093 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_suspend()
3101 struct mmc_host *mmc = dev_get_drvdata(dev); in msdc_resume() local
3102 struct msdc_host *host = mmc_priv(mmc); in msdc_resume() local
3104 if (sdio_irq_claimed(mmc) && host->pins_eint) in msdc_resume()
3119 .name = "mtk-msdc",
3128 MODULE_DESCRIPTION("MediaTek SD/MMC Card Driver");