mmc/host/dw_mmc.h

1 /* SPDX-License-Identifier: GPL-2.0-or-later */
4  *  (Based on NXP driver for lpc 31xx)
17 #include <linux/fault-inject.h>
59  * struct dw_mci - MMC controller state shared between all slots
77  * @dma_64bit_address: Whether DMA supports 64-bit address mode or not.
80  * @dma_ops: Pointer to platform-specific DMA callbacks.
84  * @dms: structure of slave-dma private data.
134  * @lock is a softirq-safe spinlock protecting @queue as well as
141  * @irq_lock is an irq-safe spinlock protecting the INTMASK register
143  * enough to read-modify-write INTMASK and no other locks are grabbed when
151  * EVENT_DATA_COMPLETE is set in @pending_events, all data-related
331  * Registers to support idmac 64-bit address mode
368 /* time-out register defines */
373 /* card-type register defines */
452 /* UHS-1 register defines */
459 /* All ctrl reset bits */
463 /* FIFO register access macros. These should not change the data endian-ness
476 	readl_relaxed((dev)->regs + SDMMC_##reg)
478 	writel_relaxed((value), (dev)->regs + SDMMC_##reg)
480 /* 16-bit FIFO access macros */
482 	readw_relaxed((dev)->regs + SDMMC_##reg)
484 	writew_relaxed((value), (dev)->regs + SDMMC_##reg)
486 /* 64-bit FIFO access macros */
489 	readq_relaxed((dev)->regs + SDMMC_##reg)
491 	writeq_relaxed((value), (dev)->regs + SDMMC_##reg)
502 	(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg))
504 	(*(volatile u64 __force *)((dev)->regs + SDMMC_##reg) = (value))
519  * struct dw_mci_slot - MMC slot state
527  * @clock: Clock rate configured by set_ios(). Protected by host->lock.
557  * dw_mci driver data - dw-mshc implementation specific driver data.