Lines Matching +full:gemini +full:- +full:rtc
1 // SPDX-License-Identifier: GPL-2.0-only
3 * lpc_ich.c - LPC interface for Intel ICH
7 * Power Management, System Management, GPIO, RTC, and LPC
12 * Copyright (c) 2017, 2021-2022 Intel Corporation
14 * Author: Aaron Sierra <asierra@xes-inc.com>
18 * document number 290655-003, 290677-014: 82801AA (ICH), 82801AB (ICHO)
19 * document number 290687-002, 298242-027: 82801BA (ICH2)
20 * document number 290733-003, 290739-013: 82801CA (ICH3-S)
21 * document number 290716-001, 290718-007: 82801CAM (ICH3-M)
22 * document number 290744-001, 290745-025: 82801DB (ICH4)
23 * document number 252337-001, 252663-008: 82801DBM (ICH4-M)
24 * document number 273599-001, 273645-002: 82801E (C-ICH)
25 * document number 252516-001, 252517-028: 82801EB (ICH5), 82801ER (ICH5R)
26 * document number 300641-004, 300884-013: 6300ESB
27 * document number 301473-002, 301474-026: 82801F (ICH6)
28 * document number 313082-001, 313075-006: 631xESB, 632xESB
29 * document number 307013-003, 307014-024: 82801G (ICH7)
30 * document number 322896-001, 322897-001: NM10
31 * document number 313056-003, 313057-017: 82801H (ICH8)
32 * document number 316972-004, 316973-012: 82801I (ICH9)
33 * document number 319973-002, 319974-002: 82801J (ICH10)
34 * document number 322169-001, 322170-003: 5 Series, 3400 Series (PCH)
35 * document number 320066-003, 320257-008: EP80597 (IICH)
36 * document number 324645-001, 324646-001: Cougar Point (CPT)
89 /* ACPI - TCO */
93 /* ACPI - SMI */
108 /* ACPI - GPE0 */
191 .name = "apollolake-pinctrl",
198 .name = "apollolake-pinctrl",
205 .name = "apollolake-pinctrl",
212 .name = "apollolake-pinctrl",
256 .name = "denverton-pinctrl",
273 .name = "intel-spi",
284 LPC_ICH2M, /* ICH2-M */
285 LPC_ICH3, /* ICH3-S */
286 LPC_ICH3M, /* ICH3-M */
288 LPC_ICH4M, /* ICH4-M */
289 LPC_CICH, /* C-ICH */
293 LPC_ICH6M, /* ICH6-M */
298 LPC_ICH7M, /* ICH7-M & ICH7-U */
299 LPC_ICH7MDH, /* ICH7-M DH */
305 LPC_ICH8ME, /* ICH8M-E */
311 LPC_ICH9ME, /* ICH9M-E */
339 LPC_LPT_LP, /* Lynx Point-LP */
344 LPC_WPT_LP, /* Wildcat Point-LP */
350 LPC_GLK, /* Gemini Lake SoC */
381 .name = "ICH2-M",
385 .name = "ICH3-S",
389 .name = "ICH3-M",
397 .name = "ICH4-M",
401 .name = "C-ICH",
418 .name = "ICH6-M",
443 .name = "ICH7-M or ICH7-U",
448 .name = "ICH7-M DH",
478 .name = "ICH8M-E",
508 .name = "ICH9M-E",
700 .name = "Gemini Lake SoC",
960 if (priv->abase_save >= 0) { in lpc_ich_restore_config_space()
961 pci_write_config_byte(dev, priv->abase, priv->abase_save); in lpc_ich_restore_config_space()
962 priv->abase_save = -1; in lpc_ich_restore_config_space()
965 if (priv->actrl_pbase_save >= 0) { in lpc_ich_restore_config_space()
966 pci_write_config_byte(dev, priv->actrl_pbase, in lpc_ich_restore_config_space()
967 priv->actrl_pbase_save); in lpc_ich_restore_config_space()
968 priv->actrl_pbase_save = -1; in lpc_ich_restore_config_space()
971 if (priv->gctrl_save >= 0) { in lpc_ich_restore_config_space()
972 pci_write_config_byte(dev, priv->gctrl, priv->gctrl_save); in lpc_ich_restore_config_space()
973 priv->gctrl_save = -1; in lpc_ich_restore_config_space()
982 switch (lpc_chipset_info[priv->chipset].iTCO_version) { in lpc_ich_enable_acpi_space()
988 pci_read_config_byte(dev, priv->abase, ®_save); in lpc_ich_enable_acpi_space()
989 pci_write_config_byte(dev, priv->abase, reg_save | 0x2); in lpc_ich_enable_acpi_space()
990 priv->abase_save = reg_save; in lpc_ich_enable_acpi_space()
997 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); in lpc_ich_enable_acpi_space()
998 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x80); in lpc_ich_enable_acpi_space()
999 priv->actrl_pbase_save = reg_save; in lpc_ich_enable_acpi_space()
1009 pci_read_config_byte(dev, priv->gctrl, ®_save); in lpc_ich_enable_gpio_space()
1010 pci_write_config_byte(dev, priv->gctrl, reg_save | 0x10); in lpc_ich_enable_gpio_space()
1011 priv->gctrl_save = reg_save; in lpc_ich_enable_gpio_space()
1019 pci_read_config_byte(dev, priv->actrl_pbase, ®_save); in lpc_ich_enable_pmc_space()
1020 pci_write_config_byte(dev, priv->actrl_pbase, reg_save | 0x2); in lpc_ich_enable_pmc_space()
1022 priv->actrl_pbase_save = reg_save; in lpc_ich_enable_pmc_space()
1032 pdata = devm_kzalloc(&dev->dev, sizeof(*pdata), GFP_KERNEL); in lpc_ich_finalize_wdt_cell()
1034 return -ENOMEM; in lpc_ich_finalize_wdt_cell()
1036 info = &lpc_chipset_info[priv->chipset]; in lpc_ich_finalize_wdt_cell()
1038 pdata->version = info->iTCO_version; in lpc_ich_finalize_wdt_cell()
1039 strscpy(pdata->name, info->name, sizeof(pdata->name)); in lpc_ich_finalize_wdt_cell()
1041 cell->platform_data = pdata; in lpc_ich_finalize_wdt_cell()
1042 cell->pdata_size = sizeof(*pdata); in lpc_ich_finalize_wdt_cell()
1051 cell->platform_data = &lpc_chipset_info[priv->chipset]; in lpc_ich_finalize_gpio_cell()
1052 cell->pdata_size = sizeof(struct lpc_ich_info); in lpc_ich_finalize_gpio_cell()
1066 !acpi_check_region(res->start + 0x40, 0x10, "LPC ICH GPIO3")) in lpc_ich_check_conflict_gpio()
1069 if (!acpi_check_region(res->start + 0x30, 0x10, "LPC ICH GPIO2")) in lpc_ich_check_conflict_gpio()
1072 ret = acpi_check_region(res->start + 0x00, 0x30, "LPC ICH GPIO1"); in lpc_ich_check_conflict_gpio()
1089 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); in lpc_ich_init_gpio()
1092 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); in lpc_ich_init_gpio()
1093 lpc_ich_gpio_cell.num_resources--; in lpc_ich_init_gpio()
1098 res->start = base_addr + ACPIBASE_GPE_OFF; in lpc_ich_init_gpio()
1099 res->end = base_addr + ACPIBASE_GPE_END; in lpc_ich_init_gpio()
1107 lpc_ich_gpio_cell.num_resources--; in lpc_ich_init_gpio()
1115 pci_read_config_dword(dev, priv->gbase, &base_addr_cfg); in lpc_ich_init_gpio()
1118 dev_notice(&dev->dev, "I/O space for GPIO uninitialized\n"); in lpc_ich_init_gpio()
1119 ret = -ENODEV; in lpc_ich_init_gpio()
1125 res->start = base_addr; in lpc_ich_init_gpio()
1126 switch (lpc_chipset_info[priv->chipset].gpio_version) { in lpc_ich_init_gpio()
1129 res->end = res->start + 128 - 1; in lpc_ich_init_gpio()
1132 res->end = res->start + 64 - 1; in lpc_ich_init_gpio()
1142 lpc_chipset_info[priv->chipset].use_gpio = ret; in lpc_ich_init_gpio()
1146 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, in lpc_ich_init_gpio()
1166 return -ENODEV; in lpc_ich_init_wdt()
1169 pci_read_config_dword(dev, priv->abase, &base_addr_cfg); in lpc_ich_init_wdt()
1172 dev_notice(&dev->dev, "I/O space for ACPI uninitialized\n"); in lpc_ich_init_wdt()
1173 ret = -ENODEV; in lpc_ich_init_wdt()
1178 res->start = base_addr + ACPIBASE_TCO_OFF; in lpc_ich_init_wdt()
1179 res->end = base_addr + ACPIBASE_TCO_END; in lpc_ich_init_wdt()
1182 res->start = base_addr + ACPIBASE_SMI_OFF; in lpc_ich_init_wdt()
1183 res->end = base_addr + ACPIBASE_SMI_END; in lpc_ich_init_wdt()
1189 * Get the Memory-Mapped GCS register. To get access to it in lpc_ich_init_wdt()
1198 if (lpc_chipset_info[priv->chipset].iTCO_version == 1) { in lpc_ich_init_wdt()
1200 lpc_ich_wdt_cell.num_resources--; in lpc_ich_init_wdt()
1201 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 2) { in lpc_ich_init_wdt()
1205 dev_notice(&dev->dev, "RCBA is disabled by " in lpc_ich_init_wdt()
1207 ret = -ENODEV; in lpc_ich_init_wdt()
1211 res->start = base_addr + ACPIBASE_GCS_OFF; in lpc_ich_init_wdt()
1212 res->end = base_addr + ACPIBASE_GCS_END; in lpc_ich_init_wdt()
1213 } else if (lpc_chipset_info[priv->chipset].iTCO_version == 3) { in lpc_ich_init_wdt()
1219 res->start = base_addr + ACPIBASE_PMC_OFF; in lpc_ich_init_wdt()
1220 res->end = base_addr + ACPIBASE_PMC_END; in lpc_ich_init_wdt()
1227 ret = mfd_add_devices(&dev->dev, PLATFORM_DEVID_AUTO, in lpc_ich_init_wdt()
1237 const struct lpc_ich_gpio_info *info = lpc_chipset_info[priv->chipset].gpio_info; in lpc_ich_init_pinctrl()
1243 if (acpi_dev_present(info->hid, NULL, -1)) in lpc_ich_init_pinctrl()
1244 return -EEXIST; in lpc_ich_init_pinctrl()
1246 ret = p2sb_bar(dev->bus, 0, &base); in lpc_ich_init_pinctrl()
1250 for (i = 0; i < info->nr_resources; i++) { in lpc_ich_init_pinctrl()
1251 struct resource *mem = info->resources[i]; in lpc_ich_init_pinctrl()
1252 resource_size_t offset = info->offsets[i]; in lpc_ich_init_pinctrl()
1255 mem->start = base.start + offset; in lpc_ich_init_pinctrl()
1256 mem->end = base.start + offset + INTEL_GPIO_RESOURCE_SIZE - 1; in lpc_ich_init_pinctrl()
1257 mem->flags = base.flags; in lpc_ich_init_pinctrl()
1260 return mfd_add_devices(&dev->dev, 0, info->devices, info->nr_devices, in lpc_ich_init_pinctrl()
1296 return lpc_ich_set_writeable(pdev->bus, pdev->devfn); in lpc_ich_lpt_set_writeable()
1303 return lpc_ich_set_writeable(pdev->bus, PCI_DEVFN(13, 2)); in lpc_ich_bxt_set_writeable()
1314 info = devm_kzalloc(&dev->dev, sizeof(*info), GFP_KERNEL); in lpc_ich_init_spi()
1316 return -ENOMEM; in lpc_ich_init_spi()
1318 info->type = lpc_chipset_info[priv->chipset].spi_type; in lpc_ich_init_spi()
1320 switch (info->type) { in lpc_ich_init_spi()
1324 res->start = spi_base & ~(SPIBASE_BYT_SZ - 1); in lpc_ich_init_spi()
1325 res->end = res->start + SPIBASE_BYT_SZ - 1; in lpc_ich_init_spi()
1327 info->set_writeable = lpc_ich_byt_set_writeable; in lpc_ich_init_spi()
1335 res->start = spi_base + SPIBASE_LPT; in lpc_ich_init_spi()
1336 res->end = res->start + SPIBASE_LPT_SZ - 1; in lpc_ich_init_spi()
1338 info->set_writeable = lpc_ich_lpt_set_writeable; in lpc_ich_init_spi()
1339 info->data = dev; in lpc_ich_init_spi()
1349 ret = p2sb_bar(dev->bus, PCI_DEVFN(13, 2), res); in lpc_ich_init_spi()
1353 info->set_writeable = lpc_ich_bxt_set_writeable; in lpc_ich_init_spi()
1354 info->data = dev; in lpc_ich_init_spi()
1358 return -EINVAL; in lpc_ich_init_spi()
1361 if (!res->start) in lpc_ich_init_spi()
1362 return -ENODEV; in lpc_ich_init_spi()
1367 return mfd_add_devices(&dev->dev, PLATFORM_DEVID_NONE, in lpc_ich_init_spi()
1378 priv = devm_kzalloc(&dev->dev, in lpc_ich_probe()
1381 return -ENOMEM; in lpc_ich_probe()
1383 priv->chipset = id->driver_data; in lpc_ich_probe()
1385 priv->actrl_pbase_save = -1; in lpc_ich_probe()
1386 priv->abase_save = -1; in lpc_ich_probe()
1388 priv->abase = ACPIBASE; in lpc_ich_probe()
1389 priv->actrl_pbase = ACPICTRL_PMCBASE; in lpc_ich_probe()
1391 priv->gctrl_save = -1; in lpc_ich_probe()
1392 if (priv->chipset <= LPC_ICH5) { in lpc_ich_probe()
1393 priv->gbase = GPIOBASE_ICH0; in lpc_ich_probe()
1394 priv->gctrl = GPIOCTRL_ICH0; in lpc_ich_probe()
1396 priv->gbase = GPIOBASE_ICH6; in lpc_ich_probe()
1397 priv->gctrl = GPIOCTRL_ICH6; in lpc_ich_probe()
1402 if (lpc_chipset_info[priv->chipset].iTCO_version) { in lpc_ich_probe()
1408 if (lpc_chipset_info[priv->chipset].gpio_version) { in lpc_ich_probe()
1414 if (lpc_chipset_info[priv->chipset].gpio_info) { in lpc_ich_probe()
1420 if (lpc_chipset_info[priv->chipset].spi_type) { in lpc_ich_probe()
1431 dev_warn(&dev->dev, "No MFD cells added\n"); in lpc_ich_probe()
1433 return -ENODEV; in lpc_ich_probe()
1441 mfd_remove_devices(&dev->dev); in lpc_ich_remove()
1454 MODULE_AUTHOR("Aaron Sierra <asierra@xes-inc.com>");