Lines Matching +full:timing +full:- +full:0
1 // SPDX-License-Identifier: GPL-2.0+
5 * Based on downstream driver from NVIDIA and tegra124-emc.c
6 * Copyright (C) 2011-2014 NVIDIA Corporation
9 * Copyright (C) 2019 GRATE-DRIVER project
18 #include <linux/interconnect-provider.h>
40 #define EMC_INTSTATUS 0x000
41 #define EMC_INTMASK 0x004
42 #define EMC_DBG 0x008
43 #define EMC_ADR_CFG 0x010
44 #define EMC_CFG 0x00c
45 #define EMC_REFCTRL 0x020
46 #define EMC_TIMING_CONTROL 0x028
47 #define EMC_RC 0x02c
48 #define EMC_RFC 0x030
49 #define EMC_RAS 0x034
50 #define EMC_RP 0x038
51 #define EMC_R2W 0x03c
52 #define EMC_W2R 0x040
53 #define EMC_R2P 0x044
54 #define EMC_W2P 0x048
55 #define EMC_RD_RCD 0x04c
56 #define EMC_WR_RCD 0x050
57 #define EMC_RRD 0x054
58 #define EMC_REXT 0x058
59 #define EMC_WDV 0x05c
60 #define EMC_QUSE 0x060
61 #define EMC_QRST 0x064
62 #define EMC_QSAFE 0x068
63 #define EMC_RDV 0x06c
64 #define EMC_REFRESH 0x070
65 #define EMC_BURST_REFRESH_NUM 0x074
66 #define EMC_PDEX2WR 0x078
67 #define EMC_PDEX2RD 0x07c
68 #define EMC_PCHG2PDEN 0x080
69 #define EMC_ACT2PDEN 0x084
70 #define EMC_AR2PDEN 0x088
71 #define EMC_RW2PDEN 0x08c
72 #define EMC_TXSR 0x090
73 #define EMC_TCKE 0x094
74 #define EMC_TFAW 0x098
75 #define EMC_TRPAB 0x09c
76 #define EMC_TCLKSTABLE 0x0a0
77 #define EMC_TCLKSTOP 0x0a4
78 #define EMC_TREFBW 0x0a8
79 #define EMC_QUSE_EXTRA 0x0ac
80 #define EMC_ODT_WRITE 0x0b0
81 #define EMC_ODT_READ 0x0b4
82 #define EMC_WEXT 0x0b8
83 #define EMC_CTT 0x0bc
84 #define EMC_MRS_WAIT_CNT 0x0c8
85 #define EMC_MRS 0x0cc
86 #define EMC_EMRS 0x0d0
87 #define EMC_SELF_REF 0x0e0
88 #define EMC_MRW 0x0e8
89 #define EMC_MRR 0x0ec
90 #define EMC_XM2DQSPADCTRL3 0x0f8
91 #define EMC_FBIO_SPARE 0x100
92 #define EMC_FBIO_CFG5 0x104
93 #define EMC_FBIO_CFG6 0x114
94 #define EMC_CFG_RSV 0x120
95 #define EMC_AUTO_CAL_CONFIG 0x2a4
96 #define EMC_AUTO_CAL_INTERVAL 0x2a8
97 #define EMC_AUTO_CAL_STATUS 0x2ac
98 #define EMC_STATUS 0x2b4
99 #define EMC_CFG_2 0x2b8
100 #define EMC_CFG_DIG_DLL 0x2bc
101 #define EMC_CFG_DIG_DLL_PERIOD 0x2c0
102 #define EMC_CTT_DURATION 0x2d8
103 #define EMC_CTT_TERM_CTRL 0x2dc
104 #define EMC_ZCAL_INTERVAL 0x2e0
105 #define EMC_ZCAL_WAIT_CNT 0x2e4
106 #define EMC_ZQ_CAL 0x2ec
107 #define EMC_XM2CMDPADCTRL 0x2f0
108 #define EMC_XM2DQSPADCTRL2 0x2fc
109 #define EMC_XM2DQPADCTRL2 0x304
110 #define EMC_XM2CLKPADCTRL 0x308
111 #define EMC_XM2COMPPADCTRL 0x30c
112 #define EMC_XM2VTTGENPADCTRL 0x310
113 #define EMC_XM2VTTGENPADCTRL2 0x314
114 #define EMC_XM2QUSEPADCTRL 0x318
115 #define EMC_DLL_XFORM_DQS0 0x328
116 #define EMC_DLL_XFORM_DQS1 0x32c
117 #define EMC_DLL_XFORM_DQS2 0x330
118 #define EMC_DLL_XFORM_DQS3 0x334
119 #define EMC_DLL_XFORM_DQS4 0x338
120 #define EMC_DLL_XFORM_DQS5 0x33c
121 #define EMC_DLL_XFORM_DQS6 0x340
122 #define EMC_DLL_XFORM_DQS7 0x344
123 #define EMC_DLL_XFORM_QUSE0 0x348
124 #define EMC_DLL_XFORM_QUSE1 0x34c
125 #define EMC_DLL_XFORM_QUSE2 0x350
126 #define EMC_DLL_XFORM_QUSE3 0x354
127 #define EMC_DLL_XFORM_QUSE4 0x358
128 #define EMC_DLL_XFORM_QUSE5 0x35c
129 #define EMC_DLL_XFORM_QUSE6 0x360
130 #define EMC_DLL_XFORM_QUSE7 0x364
131 #define EMC_DLL_XFORM_DQ0 0x368
132 #define EMC_DLL_XFORM_DQ1 0x36c
133 #define EMC_DLL_XFORM_DQ2 0x370
134 #define EMC_DLL_XFORM_DQ3 0x374
135 #define EMC_DLI_TRIM_TXDQS0 0x3a8
136 #define EMC_DLI_TRIM_TXDQS1 0x3ac
137 #define EMC_DLI_TRIM_TXDQS2 0x3b0
138 #define EMC_DLI_TRIM_TXDQS3 0x3b4
139 #define EMC_DLI_TRIM_TXDQS4 0x3b8
140 #define EMC_DLI_TRIM_TXDQS5 0x3bc
141 #define EMC_DLI_TRIM_TXDQS6 0x3c0
142 #define EMC_DLI_TRIM_TXDQS7 0x3c4
143 #define EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE 0x3c8
144 #define EMC_STALL_THEN_EXE_AFTER_CLKCHANGE 0x3cc
145 #define EMC_UNSTALL_RW_AFTER_CLKCHANGE 0x3d0
146 #define EMC_SEL_DPD_CTRL 0x3d8
147 #define EMC_PRE_REFRESH_REQ_CNT 0x3dc
148 #define EMC_DYN_SELF_REF_CONTROL 0x3e0
149 #define EMC_TXSRDLL 0x3e4
156 #define EMC_SELF_REF_CMD_ENABLED BIT(0)
158 #define DRAM_DEV_SEL_ALL (0 << 30)
164 #define EMC_ZQ_CAL_CMD BIT(0)
171 #define EMC_DBG_READ_MUX_ASSEMBLY BIT(0)
193 #define EMC_FBIO_CFG5_DRAM_TYPE_MASK 0x3
195 #define EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK 0x3ff
198 (0x3ff << EMC_MRS_WAIT_CNT_LONG_WAIT_SHIFT)
200 #define EMC_REFCTRL_DEV_SEL_MASK 0x3
203 (((num) > 1 ? 0 : 2) | EMC_REFCTRL_ENABLE)
204 #define EMC_REFCTRL_DISABLE_ALL(num) ((num) > 1 ? 0 : 2)
209 #define EMC_CLKCHANGE_REQ_ENABLE BIT(0)
213 #define EMC_TIMING_UPDATE BIT(0)
221 #define EMC_MRR_MRR_DATA GENMASK(15, 0)
223 #define EMC_ADR_CFG_EMEM_NUMDEV BIT(0)
239 [0] = EMC_RC,
392 /* protect shared rate-change code path */
403 writel_relaxed(EMC_TIMING_UPDATE, emc->regs + EMC_TIMING_CONTROL); in emc_seq_update_timing()
405 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_STATUS, val, in emc_seq_update_timing()
409 dev_err(emc->dev, "failed to update timing: %d\n", err); in emc_seq_update_timing()
413 return 0; in emc_seq_update_timing()
422 status = readl_relaxed(emc->regs + EMC_INTSTATUS) & intmask; in tegra_emc_isr()
428 dev_err_ratelimited(emc->dev, in tegra_emc_isr()
432 writel_relaxed(status, emc->regs + EMC_INTSTATUS); in tegra_emc_isr()
440 struct emc_timing *timing = NULL; in emc_find_timing() local
443 for (i = 0; i < emc->num_timings; i++) { in emc_find_timing()
444 if (emc->timings[i].rate >= rate) { in emc_find_timing()
445 timing = &emc->timings[i]; in emc_find_timing()
450 if (!timing) { in emc_find_timing()
451 dev_err(emc->dev, "no timing for rate %lu\n", rate); in emc_find_timing()
455 return timing; in emc_find_timing()
458 static bool emc_dqs_preset(struct tegra_emc *emc, struct emc_timing *timing, in emc_dqs_preset() argument
464 if (timing->data[71] & EMC_XM2DQSPADCTRL2_VREF_ENABLE) { in emc_dqs_preset()
465 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
469 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL2); in emc_dqs_preset()
475 if (timing->data[78] & EMC_XM2DQSPADCTRL3_VREF_ENABLE) { in emc_dqs_preset()
476 val = readl_relaxed(emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
480 writel_relaxed(val, emc->regs + EMC_XM2DQSPADCTRL3); in emc_dqs_preset()
486 if (timing->data[77] & EMC_XM2QUSEPADCTRL_IVREF_ENABLE) { in emc_dqs_preset()
487 val = readl_relaxed(emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
491 writel_relaxed(val, emc->regs + EMC_XM2QUSEPADCTRL); in emc_dqs_preset()
503 struct tegra_mc *mc = emc->mc; in emc_prepare_mc_clk_cfg()
508 for (i = 0; i < mc->num_timings; i++) { in emc_prepare_mc_clk_cfg()
509 if (mc->timings[i].rate != rate) in emc_prepare_mc_clk_cfg()
512 if (mc->timings[i].emem_data[misc0_index] & BIT(27)) in emc_prepare_mc_clk_cfg()
517 return tegra20_clk_prepare_emc_mc_same_freq(emc->clk, same); in emc_prepare_mc_clk_cfg()
520 return -EINVAL; in emc_prepare_mc_clk_cfg()
525 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_prepare_timing_change() local
529 unsigned int pre_wait = 0; in emc_prepare_timing_change()
538 if (!timing || emc->bad_state) in emc_prepare_timing_change()
539 return -EINVAL; in emc_prepare_timing_change()
541 dev_dbg(emc->dev, "%s: using timing rate %lu for requested rate %lu\n", in emc_prepare_timing_change()
542 __func__, timing->rate, rate); in emc_prepare_timing_change()
544 emc->bad_state = true; in emc_prepare_timing_change()
548 dev_err(emc->dev, "mc clock preparation failed: %d\n", err); in emc_prepare_timing_change()
552 emc->vref_cal_toggle = false; in emc_prepare_timing_change()
553 emc->mc_override = mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
554 emc->emc_cfg = readl_relaxed(emc->regs + EMC_CFG); in emc_prepare_timing_change()
555 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_prepare_timing_change()
557 if (emc->dll_on == !!(timing->emc_mode_1 & 0x1)) in emc_prepare_timing_change()
559 else if (timing->emc_mode_1 & 0x1) in emc_prepare_timing_change()
564 emc->dll_on = !!(timing->emc_mode_1 & 0x1); in emc_prepare_timing_change()
566 if (timing->data[80] && !readl_relaxed(emc->regs + EMC_ZCAL_INTERVAL)) in emc_prepare_timing_change()
567 emc->zcal_long = true; in emc_prepare_timing_change()
569 emc->zcal_long = false; in emc_prepare_timing_change()
571 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_prepare_timing_change()
574 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_prepare_timing_change()
576 /* disable dynamic self-refresh */ in emc_prepare_timing_change()
577 if (emc->emc_cfg & EMC_CFG_DYN_SREF_ENABLE) { in emc_prepare_timing_change()
578 emc->emc_cfg &= ~EMC_CFG_DYN_SREF_ENABLE; in emc_prepare_timing_change()
579 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
585 val = mc_readl(emc->mc, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
587 ((val & MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK) > 0x50)) { in emc_prepare_timing_change()
590 MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE | 0x50; in emc_prepare_timing_change()
591 mc_writel(emc->mc, val, MC_EMEM_ARB_OUTSTANDING_REQ); in emc_prepare_timing_change()
592 mc_writel(emc->mc, MC_TIMING_UPDATE, MC_TIMING_CONTROL); in emc_prepare_timing_change()
595 if (emc->mc_override & MC_EMEM_ARB_OVERRIDE_EACK_MASK) in emc_prepare_timing_change()
596 mc_writel(emc->mc, in emc_prepare_timing_change()
597 emc->mc_override & ~MC_EMEM_ARB_OVERRIDE_EACK_MASK, in emc_prepare_timing_change()
601 if (emc_dqs_preset(emc, timing, &schmitt_to_vref)) { in emc_prepare_timing_change()
614 /* disable auto-calibration if VREF mode is switching */ in emc_prepare_timing_change()
615 if (timing->emc_auto_cal_interval) { in emc_prepare_timing_change()
616 val = readl_relaxed(emc->regs + EMC_XM2COMPPADCTRL); in emc_prepare_timing_change()
617 val ^= timing->data[74]; in emc_prepare_timing_change()
620 writel_relaxed(0, emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_prepare_timing_change()
623 emc->regs + EMC_AUTO_CAL_STATUS, val, in emc_prepare_timing_change()
626 dev_err(emc->dev, in emc_prepare_timing_change()
627 "auto-cal finish timeout: %d\n", err); in emc_prepare_timing_change()
631 emc->vref_cal_toggle = true; in emc_prepare_timing_change()
636 for (i = 0; i < ARRAY_SIZE(timing->data); i++) { in emc_prepare_timing_change()
639 writel_relaxed(timing->data[i], in emc_prepare_timing_change()
640 emc->regs + emc_timing_registers[i]); in emc_prepare_timing_change()
643 err = tegra_mc_write_emem_configuration(emc->mc, timing->rate); in emc_prepare_timing_change()
651 if (emc->zcal_long) in emc_prepare_timing_change()
652 cnt -= dram_num * 256; in emc_prepare_timing_change()
654 val = timing->data[82] & EMC_MRS_WAIT_CNT_SHORT_WAIT_MASK; in emc_prepare_timing_change()
658 val = timing->data[82] & ~EMC_MRS_WAIT_CNT_LONG_WAIT_MASK; in emc_prepare_timing_change()
662 writel_relaxed(val, emc->regs + EMC_MRS_WAIT_CNT); in emc_prepare_timing_change()
666 val = readl_relaxed(emc->regs + EMC_SEL_DPD_CTRL); in emc_prepare_timing_change()
674 new_mode = timing->data[39] & EMC_CFG5_QUSE_MODE_MASK; in emc_prepare_timing_change()
685 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_BEFORE_CLKCHANGE); in emc_prepare_timing_change()
690 emc->regs + EMC_DBG); in emc_prepare_timing_change()
691 writel_relaxed(emc->emc_cfg | EMC_CFG_PERIODIC_QRST, in emc_prepare_timing_change()
692 emc->regs + EMC_CFG); in emc_prepare_timing_change()
693 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
696 /* disable auto-refresh to save time after clock change */ in emc_prepare_timing_change()
698 emc->regs + EMC_REFCTRL); in emc_prepare_timing_change()
700 /* turn off DLL and enter self-refresh on DDR3 */ in emc_prepare_timing_change()
703 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
704 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
708 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
712 writel_relaxed(0x1, emc->regs + EMC_STALL_THEN_EXE_AFTER_CLKCHANGE); in emc_prepare_timing_change()
714 /* enable write-active MUX, update unshadowed pad control */ in emc_prepare_timing_change()
715 writel_relaxed(emc_dbg | EMC_DBG_WRITE_MUX_ACTIVE, emc->regs + EMC_DBG); in emc_prepare_timing_change()
716 writel_relaxed(timing->data[73], emc->regs + EMC_XM2CLKPADCTRL); in emc_prepare_timing_change()
718 /* restore periodic QRST and disable write-active MUX */ in emc_prepare_timing_change()
719 val = !!(emc->emc_cfg & EMC_CFG_PERIODIC_QRST); in emc_prepare_timing_change()
720 if (qrst_used || timing->emc_cfg_periodic_qrst != val) { in emc_prepare_timing_change()
721 if (timing->emc_cfg_periodic_qrst) in emc_prepare_timing_change()
722 emc->emc_cfg |= EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
724 emc->emc_cfg &= ~EMC_CFG_PERIODIC_QRST; in emc_prepare_timing_change()
726 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_prepare_timing_change()
728 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_prepare_timing_change()
730 /* exit self-refresh on DDR3 */ in emc_prepare_timing_change()
733 emc->regs + EMC_SELF_REF); in emc_prepare_timing_change()
735 /* set DRAM-mode registers */ in emc_prepare_timing_change()
737 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
738 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
739 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
741 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
742 writel_relaxed(timing->emc_mode_2, in emc_prepare_timing_change()
743 emc->regs + EMC_EMRS); in emc_prepare_timing_change()
745 if (timing->emc_mode_reset != emc->emc_mode_reset || in emc_prepare_timing_change()
747 val = timing->emc_mode_reset; in emc_prepare_timing_change()
754 writel_relaxed(val, emc->regs + EMC_MRS); in emc_prepare_timing_change()
757 if (timing->emc_mode_2 != emc->emc_mode_2) in emc_prepare_timing_change()
758 writel_relaxed(timing->emc_mode_2, in emc_prepare_timing_change()
759 emc->regs + EMC_MRW); in emc_prepare_timing_change()
761 if (timing->emc_mode_1 != emc->emc_mode_1) in emc_prepare_timing_change()
762 writel_relaxed(timing->emc_mode_1, in emc_prepare_timing_change()
763 emc->regs + EMC_MRW); in emc_prepare_timing_change()
766 emc->emc_mode_1 = timing->emc_mode_1; in emc_prepare_timing_change()
767 emc->emc_mode_2 = timing->emc_mode_2; in emc_prepare_timing_change()
768 emc->emc_mode_reset = timing->emc_mode_reset; in emc_prepare_timing_change()
771 if (emc->zcal_long) { in emc_prepare_timing_change()
773 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
777 emc->regs + EMC_ZQ_CAL); in emc_prepare_timing_change()
781 writel_relaxed(0x1, emc->regs + EMC_UNSTALL_RW_AFTER_CLKCHANGE); in emc_prepare_timing_change()
787 mc_readl(emc->mc, MC_EMEM_ARB_OVERRIDE); in emc_prepare_timing_change()
789 return 0; in emc_prepare_timing_change()
795 struct emc_timing *timing = emc_find_timing(emc, rate); in emc_complete_timing_change() local
800 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, v, in emc_complete_timing_change()
804 dev_err(emc->dev, "emc-car handshake timeout: %d\n", err); in emc_complete_timing_change()
808 /* re-enable auto-refresh */ in emc_complete_timing_change()
809 dram_num = tegra_mc_get_emem_device_count(emc->mc); in emc_complete_timing_change()
811 emc->regs + EMC_REFCTRL); in emc_complete_timing_change()
813 /* restore auto-calibration */ in emc_complete_timing_change()
814 if (emc->vref_cal_toggle) in emc_complete_timing_change()
815 writel_relaxed(timing->emc_auto_cal_interval, in emc_complete_timing_change()
816 emc->regs + EMC_AUTO_CAL_INTERVAL); in emc_complete_timing_change()
818 /* restore dynamic self-refresh */ in emc_complete_timing_change()
819 if (timing->emc_cfg_dyn_self_ref) { in emc_complete_timing_change()
820 emc->emc_cfg |= EMC_CFG_DYN_SREF_ENABLE; in emc_complete_timing_change()
821 writel_relaxed(emc->emc_cfg, emc->regs + EMC_CFG); in emc_complete_timing_change()
825 if (emc->zcal_long) in emc_complete_timing_change()
826 writel_relaxed(timing->emc_zcal_cnt_long, in emc_complete_timing_change()
827 emc->regs + EMC_ZCAL_WAIT_CNT); in emc_complete_timing_change()
832 /* update restored timing */ in emc_complete_timing_change()
835 emc->bad_state = false; in emc_complete_timing_change()
838 mc_writel(emc->mc, emc->mc_override, MC_EMEM_ARB_OVERRIDE); in emc_complete_timing_change()
846 if (!emc->bad_state) { in emc_unprepare_timing_change()
848 dev_err(emc->dev, "timing configuration can't be reverted\n"); in emc_unprepare_timing_change()
849 emc->bad_state = true; in emc_unprepare_timing_change()
852 return 0; in emc_unprepare_timing_change()
868 disable_irq(emc->irq); in emc_clk_change_notify()
869 err = emc_prepare_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
870 enable_irq(emc->irq); in emc_clk_change_notify()
874 err = emc_unprepare_timing_change(emc, cnd->old_rate); in emc_clk_change_notify()
878 err = emc_complete_timing_change(emc, cnd->new_rate); in emc_clk_change_notify()
889 struct emc_timing *timing, in load_one_timing_from_dt() argument
895 err = of_property_read_u32(node, "clock-frequency", &value); in load_one_timing_from_dt()
897 dev_err(emc->dev, "timing %pOF: failed to read rate: %d\n", in load_one_timing_from_dt()
902 timing->rate = value; in load_one_timing_from_dt()
904 err = of_property_read_u32_array(node, "nvidia,emc-configuration", in load_one_timing_from_dt()
905 timing->data, in load_one_timing_from_dt()
908 dev_err(emc->dev, in load_one_timing_from_dt()
909 "timing %pOF: failed to read emc timing data: %d\n", in load_one_timing_from_dt()
915 timing->prop = of_property_read_bool(node, dtprop); in load_one_timing_from_dt()
918 err = of_property_read_u32(node, dtprop, &timing->prop); \ in load_one_timing_from_dt()
920 dev_err(emc->dev, \ in load_one_timing_from_dt()
921 "timing %pOFn: failed to read " #prop ": %d\n", \ in load_one_timing_from_dt()
926 EMC_READ_U32(emc_auto_cal_interval, "nvidia,emc-auto-cal-interval") in load_one_timing_from_dt()
927 EMC_READ_U32(emc_mode_1, "nvidia,emc-mode-1") in load_one_timing_from_dt()
928 EMC_READ_U32(emc_mode_2, "nvidia,emc-mode-2") in load_one_timing_from_dt()
929 EMC_READ_U32(emc_mode_reset, "nvidia,emc-mode-reset") in load_one_timing_from_dt()
930 EMC_READ_U32(emc_zcal_cnt_long, "nvidia,emc-zcal-cnt-long") in load_one_timing_from_dt()
931 EMC_READ_BOOL(emc_cfg_dyn_self_ref, "nvidia,emc-cfg-dyn-self-ref") in load_one_timing_from_dt()
932 EMC_READ_BOOL(emc_cfg_periodic_qrst, "nvidia,emc-cfg-periodic-qrst") in load_one_timing_from_dt()
937 dev_dbg(emc->dev, "%s: %pOF: rate %lu\n", __func__, node, timing->rate); in load_one_timing_from_dt()
939 return 0; in load_one_timing_from_dt()
947 if (a->rate < b->rate) in cmp_timings()
948 return -1; in cmp_timings()
950 if (a->rate > b->rate) in cmp_timings()
953 return 0; in cmp_timings()
958 struct tegra_mc *mc = emc->mc; in emc_check_mc_timings()
961 if (emc->num_timings != mc->num_timings) { in emc_check_mc_timings()
962 dev_err(emc->dev, "emc/mc timings number mismatch: %u %u\n", in emc_check_mc_timings()
963 emc->num_timings, mc->num_timings); in emc_check_mc_timings()
964 return -EINVAL; in emc_check_mc_timings()
967 for (i = 0; i < mc->num_timings; i++) { in emc_check_mc_timings()
968 if (emc->timings[i].rate != mc->timings[i].rate) { in emc_check_mc_timings()
969 dev_err(emc->dev, in emc_check_mc_timings()
970 "emc/mc timing rate mismatch: %lu %lu\n", in emc_check_mc_timings()
971 emc->timings[i].rate, mc->timings[i].rate); in emc_check_mc_timings()
972 return -EINVAL; in emc_check_mc_timings()
976 return 0; in emc_check_mc_timings()
983 struct emc_timing *timing; in emc_load_timings_from_dt() local
989 dev_err(emc->dev, "no memory timings in: %pOF\n", node); in emc_load_timings_from_dt()
990 return -EINVAL; in emc_load_timings_from_dt()
993 emc->timings = devm_kcalloc(emc->dev, child_count, sizeof(*timing), in emc_load_timings_from_dt()
995 if (!emc->timings) in emc_load_timings_from_dt()
996 return -ENOMEM; in emc_load_timings_from_dt()
998 emc->num_timings = child_count; in emc_load_timings_from_dt()
999 timing = emc->timings; in emc_load_timings_from_dt()
1002 err = load_one_timing_from_dt(emc, timing++, child); in emc_load_timings_from_dt()
1009 sort(emc->timings, emc->num_timings, sizeof(*timing), cmp_timings, in emc_load_timings_from_dt()
1016 dev_info_once(emc->dev, in emc_load_timings_from_dt()
1018 emc->num_timings, in emc_load_timings_from_dt()
1020 emc->timings[0].rate / 1000000, in emc_load_timings_from_dt()
1021 emc->timings[emc->num_timings - 1].rate / 1000000); in emc_load_timings_from_dt()
1023 return 0; in emc_load_timings_from_dt()
1028 struct device *dev = emc->dev; in emc_find_node_by_ram_code()
1033 if (emc->mrr_error) { in emc_find_node_by_ram_code()
1038 if (of_get_child_count(dev->of_node) == 0) { in emc_find_node_by_ram_code()
1039 dev_info_once(dev, "device-tree doesn't have memory timings\n"); in emc_find_node_by_ram_code()
1045 for_each_child_of_node(dev->of_node, np) { in emc_find_node_by_ram_code()
1046 err = of_property_read_u32(np, "nvidia,ram-code", &value); in emc_find_node_by_ram_code()
1053 dev_err(dev, "no memory timings for RAM code %u found in device-tree\n", in emc_find_node_by_ram_code()
1065 u32 val, mr_mask = 0xff; in emc_read_lpddr_mode_register()
1068 /* clear data-valid interrupt status */ in emc_read_lpddr_mode_register()
1069 writel_relaxed(EMC_MRR_DIVLD_INT, emc->regs + EMC_INTSTATUS); in emc_read_lpddr_mode_register()
1075 writel_relaxed(val, emc->regs + EMC_MRR); in emc_read_lpddr_mode_register()
1077 /* wait for the LPDDR2 data-valid interrupt */ in emc_read_lpddr_mode_register()
1078 err = readl_relaxed_poll_timeout_atomic(emc->regs + EMC_INTSTATUS, val, in emc_read_lpddr_mode_register()
1082 dev_err(emc->dev, "mode register %u read failed: %d\n", in emc_read_lpddr_mode_register()
1084 emc->mrr_error = true; in emc_read_lpddr_mode_register()
1089 val = readl_relaxed(emc->regs + EMC_MRR); in emc_read_lpddr_mode_register()
1092 return 0; in emc_read_lpddr_mode_register()
1109 …dev_info(emc->dev, "SDRAM[dev%u]: manufacturer: 0x%x (%s) rev1: 0x%x rev2: 0x%x prefetch: S%u dens… in emc_read_lpddr_sdram_info()
1127 fbio_cfg5 = readl_relaxed(emc->regs + EMC_FBIO_CFG5); in emc_setup_hw()
1130 emc_cfg = readl_relaxed(emc->regs + EMC_CFG_2); in emc_setup_hw()
1148 writel_relaxed(emc_cfg, emc->regs + EMC_CFG_2); in emc_setup_hw()
1151 writel_relaxed(intmask, emc->regs + EMC_INTMASK); in emc_setup_hw()
1152 writel_relaxed(0xffffffff, emc->regs + EMC_INTSTATUS); in emc_setup_hw()
1155 emc_dbg = readl_relaxed(emc->regs + EMC_DBG); in emc_setup_hw()
1160 writel_relaxed(emc_dbg, emc->regs + EMC_DBG); in emc_setup_hw()
1177 emc_adr_cfg = readl_relaxed(emc->regs + EMC_ADR_CFG); in emc_setup_hw()
1180 dev_info_once(emc->dev, "%u %s %s attached\n", emem_numdev, in emc_setup_hw()
1184 while (emem_numdev--) in emc_setup_hw()
1190 return 0; in emc_setup_hw()
1198 struct emc_timing *timing = NULL; in emc_round_rate() local
1202 if (!emc->num_timings) in emc_round_rate()
1203 return clk_get_rate(emc->clk); in emc_round_rate()
1205 min_rate = min(min_rate, emc->timings[emc->num_timings - 1].rate); in emc_round_rate()
1207 for (i = 0; i < emc->num_timings; i++) { in emc_round_rate()
1208 if (emc->timings[i].rate < rate && i != emc->num_timings - 1) in emc_round_rate()
1211 if (emc->timings[i].rate > max_rate) { in emc_round_rate()
1212 i = max(i, 1u) - 1; in emc_round_rate()
1214 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1218 if (emc->timings[i].rate < min_rate) in emc_round_rate()
1221 timing = &emc->timings[i]; in emc_round_rate()
1225 if (!timing) { in emc_round_rate()
1226 dev_err(emc->dev, "no timing for rate %lu min %lu max %lu\n", in emc_round_rate()
1228 return -EINVAL; in emc_round_rate()
1231 return timing->rate; in emc_round_rate()
1238 for (i = 0; i < EMC_RATE_TYPE_MAX; i++) { in tegra_emc_rate_requests_init()
1239 emc->requested_rate[i].min_rate = 0; in tegra_emc_rate_requests_init()
1240 emc->requested_rate[i].max_rate = ULONG_MAX; in tegra_emc_rate_requests_init()
1249 struct emc_rate_request *req = emc->requested_rate; in emc_request_rate()
1250 unsigned long min_rate = 0, max_rate = ULONG_MAX; in emc_request_rate()
1255 for (i = 0; i < EMC_RATE_TYPE_MAX; i++, req++) { in emc_request_rate()
1260 min_rate = max(req->min_rate, min_rate); in emc_request_rate()
1261 max_rate = min(req->max_rate, max_rate); in emc_request_rate()
1266 dev_err_ratelimited(emc->dev, "%s: type %u: out of range: %lu %lu\n", in emc_request_rate()
1268 return -ERANGE; in emc_request_rate()
1272 * EMC rate-changes should go via OPP API because it manages voltage in emc_request_rate()
1275 err = dev_pm_opp_set_rate(emc->dev, min_rate); in emc_request_rate()
1279 emc->requested_rate[type].min_rate = new_min_rate; in emc_request_rate()
1280 emc->requested_rate[type].max_rate = new_max_rate; in emc_request_rate()
1282 return 0; in emc_request_rate()
1288 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_min_rate()
1291 mutex_lock(&emc->rate_lock); in emc_set_min_rate()
1292 ret = emc_request_rate(emc, rate, req->max_rate, type); in emc_set_min_rate()
1293 mutex_unlock(&emc->rate_lock); in emc_set_min_rate()
1301 struct emc_rate_request *req = &emc->requested_rate[type]; in emc_set_max_rate()
1304 mutex_lock(&emc->rate_lock); in emc_set_max_rate()
1305 ret = emc_request_rate(emc, req->min_rate, rate, type); in emc_set_max_rate()
1306 mutex_unlock(&emc->rate_lock); in emc_set_max_rate()
1315 * to control the EMC frequency. The top-level directory can be found here:
1321 * - available_rates: This file contains a list of valid, space-separated
1324 * - min_rate: Writing a value to this file sets the given frequency as the
1329 * - max_rate: Similarily to the min_rate file, writing a value to this file
1340 for (i = 0; i < emc->num_timings; i++) in tegra_emc_validate_rate()
1341 if (rate == emc->timings[i].rate) in tegra_emc_validate_rate()
1349 struct tegra_emc *emc = s->private; in tegra_emc_debug_available_rates_show()
1353 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debug_available_rates_show()
1354 seq_printf(s, "%s%lu", prefix, emc->timings[i].rate); in tegra_emc_debug_available_rates_show()
1360 return 0; in tegra_emc_debug_available_rates_show()
1368 *rate = emc->debugfs.min_rate; in tegra_emc_debug_min_rate_get()
1370 return 0; in tegra_emc_debug_min_rate_get()
1379 return -EINVAL; in tegra_emc_debug_min_rate_set()
1382 if (err < 0) in tegra_emc_debug_min_rate_set()
1385 emc->debugfs.min_rate = rate; in tegra_emc_debug_min_rate_set()
1387 return 0; in tegra_emc_debug_min_rate_set()
1398 *rate = emc->debugfs.max_rate; in tegra_emc_debug_max_rate_get()
1400 return 0; in tegra_emc_debug_max_rate_get()
1409 return -EINVAL; in tegra_emc_debug_max_rate_set()
1412 if (err < 0) in tegra_emc_debug_max_rate_set()
1415 emc->debugfs.max_rate = rate; in tegra_emc_debug_max_rate_set()
1417 return 0; in tegra_emc_debug_max_rate_set()
1426 struct device *dev = emc->dev; in tegra_emc_debugfs_init()
1430 emc->debugfs.min_rate = ULONG_MAX; in tegra_emc_debugfs_init()
1431 emc->debugfs.max_rate = 0; in tegra_emc_debugfs_init()
1433 for (i = 0; i < emc->num_timings; i++) { in tegra_emc_debugfs_init()
1434 if (emc->timings[i].rate < emc->debugfs.min_rate) in tegra_emc_debugfs_init()
1435 emc->debugfs.min_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1437 if (emc->timings[i].rate > emc->debugfs.max_rate) in tegra_emc_debugfs_init()
1438 emc->debugfs.max_rate = emc->timings[i].rate; in tegra_emc_debugfs_init()
1441 if (!emc->num_timings) { in tegra_emc_debugfs_init()
1442 emc->debugfs.min_rate = clk_get_rate(emc->clk); in tegra_emc_debugfs_init()
1443 emc->debugfs.max_rate = emc->debugfs.min_rate; in tegra_emc_debugfs_init()
1446 err = clk_set_rate_range(emc->clk, emc->debugfs.min_rate, in tegra_emc_debugfs_init()
1447 emc->debugfs.max_rate); in tegra_emc_debugfs_init()
1448 if (err < 0) { in tegra_emc_debugfs_init()
1449 dev_err(dev, "failed to set rate range [%lu-%lu] for %pC\n", in tegra_emc_debugfs_init()
1450 emc->debugfs.min_rate, emc->debugfs.max_rate, in tegra_emc_debugfs_init()
1451 emc->clk); in tegra_emc_debugfs_init()
1454 emc->debugfs.root = debugfs_create_dir("emc", NULL); in tegra_emc_debugfs_init()
1456 debugfs_create_file("available_rates", 0444, emc->debugfs.root, in tegra_emc_debugfs_init()
1458 debugfs_create_file("min_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1460 debugfs_create_file("max_rate", 0644, emc->debugfs.root, in tegra_emc_debugfs_init()
1478 list_for_each_entry(node, &provider->nodes, node_list) { in emc_of_icc_xlate_extended()
1479 if (node->id != TEGRA_ICC_EMEM) in emc_of_icc_xlate_extended()
1484 return ERR_PTR(-ENOMEM); in emc_of_icc_xlate_extended()
1490 ndata->tag = TEGRA_MC_ICC_TAG_ISO; in emc_of_icc_xlate_extended()
1491 ndata->node = node; in emc_of_icc_xlate_extended()
1496 return ERR_PTR(-EPROBE_DEFER); in emc_of_icc_xlate_extended()
1501 struct tegra_emc *emc = to_tegra_emc_provider(dst->provider); in emc_icc_set()
1502 unsigned long long peak_bw = icc_units_to_bps(dst->peak_bw); in emc_icc_set()
1503 unsigned long long avg_bw = icc_units_to_bps(dst->avg_bw); in emc_icc_set()
1521 return 0; in emc_icc_set()
1526 const struct tegra_mc_soc *soc = emc->mc->soc; in tegra_emc_interconnect_init()
1530 emc->provider.dev = emc->dev; in tegra_emc_interconnect_init()
1531 emc->provider.set = emc_icc_set; in tegra_emc_interconnect_init()
1532 emc->provider.data = &emc->provider; in tegra_emc_interconnect_init()
1533 emc->provider.aggregate = soc->icc_ops->aggregate; in tegra_emc_interconnect_init()
1534 emc->provider.xlate_extended = emc_of_icc_xlate_extended; in tegra_emc_interconnect_init()
1536 icc_provider_init(&emc->provider); in tegra_emc_interconnect_init()
1545 node->name = "External Memory Controller"; in tegra_emc_interconnect_init()
1546 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1560 node->name = "External Memory (DRAM)"; in tegra_emc_interconnect_init()
1561 icc_node_add(node, &emc->provider); in tegra_emc_interconnect_init()
1563 err = icc_provider_register(&emc->provider); in tegra_emc_interconnect_init()
1567 return 0; in tegra_emc_interconnect_init()
1570 icc_nodes_remove(&emc->provider); in tegra_emc_interconnect_init()
1572 dev_err(emc->dev, "failed to initialize ICC: %d\n", err); in tegra_emc_interconnect_init()
1586 clk_notifier_unregister(emc->clk, &emc->clk_nb); in devm_tegra_emc_unreg_clk_notifier()
1595 err = devm_add_action_or_reset(emc->dev, devm_tegra_emc_unset_callback, in tegra_emc_init_clk()
1600 emc->clk = devm_clk_get(emc->dev, NULL); in tegra_emc_init_clk()
1601 if (IS_ERR(emc->clk)) { in tegra_emc_init_clk()
1602 dev_err(emc->dev, "failed to get EMC clock: %pe\n", emc->clk); in tegra_emc_init_clk()
1603 return PTR_ERR(emc->clk); in tegra_emc_init_clk()
1606 err = clk_notifier_register(emc->clk, &emc->clk_nb); in tegra_emc_init_clk()
1608 dev_err(emc->dev, "failed to register clk notifier: %d\n", err); in tegra_emc_init_clk()
1612 err = devm_add_action_or_reset(emc->dev, in tegra_emc_init_clk()
1617 return 0; in tegra_emc_init_clk()
1627 emc = devm_kzalloc(&pdev->dev, sizeof(*emc), GFP_KERNEL); in tegra_emc_probe()
1629 return -ENOMEM; in tegra_emc_probe()
1631 emc->mc = devm_tegra_memory_controller_get(&pdev->dev); in tegra_emc_probe()
1632 if (IS_ERR(emc->mc)) in tegra_emc_probe()
1633 return PTR_ERR(emc->mc); in tegra_emc_probe()
1635 mutex_init(&emc->rate_lock); in tegra_emc_probe()
1636 emc->clk_nb.notifier_call = emc_clk_change_notify; in tegra_emc_probe()
1637 emc->dev = &pdev->dev; in tegra_emc_probe()
1639 emc->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_emc_probe()
1640 if (IS_ERR(emc->regs)) in tegra_emc_probe()
1641 return PTR_ERR(emc->regs); in tegra_emc_probe()
1655 err = platform_get_irq(pdev, 0); in tegra_emc_probe()
1656 if (err < 0) in tegra_emc_probe()
1659 emc->irq = err; in tegra_emc_probe()
1661 err = devm_request_irq(&pdev->dev, emc->irq, tegra_emc_isr, 0, in tegra_emc_probe()
1662 dev_name(&pdev->dev), emc); in tegra_emc_probe()
1664 dev_err(&pdev->dev, "failed to request irq: %d\n", err); in tegra_emc_probe()
1674 err = devm_tegra_core_dev_init_opp_table(&pdev->dev, &opp_params); in tegra_emc_probe()
1690 return 0; in tegra_emc_probe()
1699 err = clk_rate_exclusive_get(emc->clk); in tegra_emc_suspend()
1701 dev_err(emc->dev, "failed to acquire clk: %d\n", err); in tegra_emc_suspend()
1706 if (WARN(emc->bad_state, "hardware in a bad state\n")) in tegra_emc_suspend()
1707 return -EINVAL; in tegra_emc_suspend()
1709 emc->bad_state = true; in tegra_emc_suspend()
1711 return 0; in tegra_emc_suspend()
1719 emc->bad_state = false; in tegra_emc_resume()
1721 clk_rate_exclusive_put(emc->clk); in tegra_emc_resume()
1723 return 0; in tegra_emc_resume()
1732 { .compatible = "nvidia,tegra30-emc", },
1740 .name = "tegra30-emc",