15 	const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;  in prepare_tile_info_buffer()  local
18 	unsigned int num_tile_rows = pps->num_tile_rows_minus1 + 1;  in prepare_tile_info_buffer()
19 	unsigned int num_tile_cols = pps->num_tile_columns_minus1 + 1;  in prepare_tile_info_buffer()
25 	tiles_enabled = !!(pps->flags & V4L2_HEVC_PPS_FLAG_TILES_ENABLED);  in prepare_tile_info_buffer()
26 	uniform_spacing = !!(pps->flags & V4L2_HEVC_PPS_FLAG_UNIFORM_SPACING);  in prepare_tile_info_buffer()
57 					h = pps->row_height_minus1[i] + 1;  in prepare_tile_info_buffer()
62 					tmp_w += pps->column_width_minus1[j] + 1;  in prepare_tile_info_buffer()
63 					*p++ = pps->column_width_minus1[j] + 1;  in prepare_tile_info_buffer()
86 					    (pps->column_width_minus1[0] + 1) == 1 &&  in prepare_tile_info_buffer()
111 	const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;  in compute_header_skip_length()  local
114 	if (pps->flags & V4L2_HEVC_PPS_FLAG_OUTPUT_FLAG_PRESENT)  in compute_header_skip_length()
145 	const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;  in set_params()  local
206 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED));  in set_params()
208 	if (pps->flags & V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED) {  in set_params()
210 		hantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth);  in set_params()
216 	hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset);  in set_params()
217 	hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset);  in set_params()
219 	hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2);  in set_params()
220 	hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2);  in set_params()
222 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_SLICE_SEGMENT_HEADER_EXTENSION_PRESENT));  in set_params()
223 	hantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits);  in set_params()
225 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_SLICE_CHROMA_QP_OFFSETS_PRESENT));  in set_params()
227 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED));  in set_params()
229 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED));  in set_params()
231 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LISTS_MODIFICATION_PRESENT));  in set_params()
233 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED));  in set_params()
235 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));  in set_params()
239 			 pps->log2_parallel_merge_level_minus2 + 2);  in set_params()
262 	hantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26);  in set_params()
264 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED));  in set_params()
266 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CABAC_INIT_PRESENT));  in set_params()
268 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED));  in set_params()
270 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED));  in set_params()
272 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_DISABLE_DEBLOCKING_FILTER));  in set_params()
274 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_CONTROL_PRESENT));  in set_params()
276 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEPENDENT_SLICE_SEGMENT_ENABLED));  in set_params()
278 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_DEBLOCKING_FILTER_OVERRIDE_ENABLED));  in set_params()
280 			 pps->num_ref_idx_l0_default_active_minus1 + 1);  in set_params()
282 			 pps->num_ref_idx_l1_default_active_minus1 + 1);  in set_params()
366 	const struct v4l2_ctrl_hevc_pps *pps = ctrls->pps;  in set_ref()  local
407 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED));  in set_ref()
409 			 !!(pps->flags & V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED));  in set_ref()