Lines Matching full:vpu
3 * Hantro VPU HEVC codec driver
13 struct hantro_dev *vpu = ctx->dev; in prepare_tile_info_buffer() local
28 hantro_reg_write(vpu, &g2_tile_e, tiles_enabled); in prepare_tile_info_buffer()
46 hantro_reg_write(vpu, &g2_num_tile_rows, num_tile_rows); in prepare_tile_info_buffer()
47 hantro_reg_write(vpu, &g2_num_tile_cols, num_tile_cols); in prepare_tile_info_buffer()
94 hantro_reg_write(vpu, &g2_num_tile_rows, 1); in prepare_tile_info_buffer()
95 hantro_reg_write(vpu, &g2_num_tile_cols, 1); in prepare_tile_info_buffer()
147 struct hantro_dev *vpu = ctx->dev; in set_params() local
153 hantro_reg_write(vpu, &g2_bit_depth_y_minus8, sps->bit_depth_luma_minus8); in set_params()
154 hantro_reg_write(vpu, &g2_bit_depth_c_minus8, sps->bit_depth_chroma_minus8); in set_params()
156 hantro_reg_write(vpu, &g2_hdr_skip_length, compute_header_skip_length(ctx)); in set_params()
161 hantro_reg_write(vpu, &g2_min_cb_size, min_log2_cb_size); in set_params()
162 hantro_reg_write(vpu, &g2_max_cb_size, max_log2_ctb_size); in set_params()
175 hantro_reg_write(vpu, &g2_partial_ctb_x, partial_ctb_x); in set_params()
176 hantro_reg_write(vpu, &g2_partial_ctb_y, partial_ctb_y); in set_params()
178 hantro_reg_write(vpu, &g2_pic_width_in_cbs, pic_width_in_min_cbs); in set_params()
179 hantro_reg_write(vpu, &g2_pic_height_in_cbs, pic_height_in_min_cbs); in set_params()
181 hantro_reg_write(vpu, &g2_pic_width_4x4, in set_params()
183 hantro_reg_write(vpu, &g2_pic_height_4x4, in set_params()
186 hantro_reg_write(vpu, &hevc_max_inter_hierdepth, in set_params()
188 hantro_reg_write(vpu, &hevc_max_intra_hierdepth, in set_params()
190 hantro_reg_write(vpu, &hevc_min_trb_size, in set_params()
192 hantro_reg_write(vpu, &hevc_max_trb_size, in set_params()
196 hantro_reg_write(vpu, &g2_tempor_mvp_e, in set_params()
199 hantro_reg_write(vpu, &g2_strong_smooth_e, in set_params()
201 hantro_reg_write(vpu, &g2_asym_pred_e, in set_params()
203 hantro_reg_write(vpu, &g2_sao_e, in set_params()
205 hantro_reg_write(vpu, &g2_sign_data_hide, in set_params()
209 hantro_reg_write(vpu, &g2_cu_qpd_e, 1); in set_params()
210 hantro_reg_write(vpu, &g2_max_cu_qpd_depth, pps->diff_cu_qp_delta_depth); in set_params()
212 hantro_reg_write(vpu, &g2_cu_qpd_e, 0); in set_params()
213 hantro_reg_write(vpu, &g2_max_cu_qpd_depth, 0); in set_params()
216 hantro_reg_write(vpu, &g2_cb_qp_offset, pps->pps_cb_qp_offset); in set_params()
217 hantro_reg_write(vpu, &g2_cr_qp_offset, pps->pps_cr_qp_offset); in set_params()
219 hantro_reg_write(vpu, &g2_filt_offset_beta, pps->pps_beta_offset_div2); in set_params()
220 hantro_reg_write(vpu, &g2_filt_offset_tc, pps->pps_tc_offset_div2); in set_params()
221 hantro_reg_write(vpu, &g2_slice_hdr_ext_e, in set_params()
223 hantro_reg_write(vpu, &g2_slice_hdr_ext_bits, pps->num_extra_slice_header_bits); in set_params()
224 hantro_reg_write(vpu, &g2_slice_chqp_present, in set_params()
226 hantro_reg_write(vpu, &g2_weight_bipr_idc, in set_params()
228 hantro_reg_write(vpu, &g2_transq_bypass, in set_params()
230 hantro_reg_write(vpu, &g2_list_mod_e, in set_params()
232 hantro_reg_write(vpu, &g2_entropy_sync_e, in set_params()
234 hantro_reg_write(vpu, &g2_cabac_init_present, in set_params()
236 hantro_reg_write(vpu, &g2_idr_pic_e, in set_params()
238 hantro_reg_write(vpu, &hevc_parallel_merge, in set_params()
240 hantro_reg_write(vpu, &g2_pcm_filt_d, in set_params()
242 hantro_reg_write(vpu, &g2_pcm_e, in set_params()
245 hantro_reg_write(vpu, &g2_max_pcm_size, in set_params()
248 hantro_reg_write(vpu, &g2_min_pcm_size, in set_params()
250 hantro_reg_write(vpu, &g2_bit_depth_pcm_y, in set_params()
252 hantro_reg_write(vpu, &g2_bit_depth_pcm_c, in set_params()
255 hantro_reg_write(vpu, &g2_max_pcm_size, 0); in set_params()
256 hantro_reg_write(vpu, &g2_min_pcm_size, 0); in set_params()
257 hantro_reg_write(vpu, &g2_bit_depth_pcm_y, 0); in set_params()
258 hantro_reg_write(vpu, &g2_bit_depth_pcm_c, 0); in set_params()
261 hantro_reg_write(vpu, &g2_start_code_e, 1); in set_params()
262 hantro_reg_write(vpu, &g2_init_qp, pps->init_qp_minus26 + 26); in set_params()
263 hantro_reg_write(vpu, &g2_weight_pred_e, in set_params()
265 hantro_reg_write(vpu, &g2_cabac_init_present, in set_params()
267 hantro_reg_write(vpu, &g2_const_intra_e, in set_params()
269 hantro_reg_write(vpu, &g2_transform_skip, in set_params()
271 hantro_reg_write(vpu, &g2_out_filtering_dis, in set_params()
273 hantro_reg_write(vpu, &g2_filt_ctrl_pres, in set_params()
275 hantro_reg_write(vpu, &g2_dependent_slice, in set_params()
277 hantro_reg_write(vpu, &g2_filter_override, in set_params()
279 hantro_reg_write(vpu, &g2_refidx0_active, in set_params()
281 hantro_reg_write(vpu, &g2_refidx1_active, in set_params()
283 hantro_reg_write(vpu, &g2_apf_threshold, 8); in set_params()
289 struct hantro_dev *vpu = ctx->dev; in set_ref_pic_list() local
358 hantro_reg_write(vpu, &ref_pic_regs0[i], list0[i]); in set_ref_pic_list()
359 hantro_reg_write(vpu, &ref_pic_regs1[i], list1[i]); in set_ref_pic_list()
370 struct hantro_dev *vpu = ctx->dev; in set_ref() local
405 hantro_reg_write(vpu, &g2_num_ref_frames, max_ref_frames); in set_ref()
406 hantro_reg_write(vpu, &g2_filter_over_slices, in set_ref()
408 hantro_reg_write(vpu, &g2_filter_over_tiles, in set_ref()
417 hantro_reg_write(vpu, &cur_poc[i], poc_diff); in set_ref()
425 hantro_reg_write(vpu, &cur_poc[i], 0); in set_ref()
431 hantro_reg_write(vpu, &cur_poc[i], decode_params->pic_order_cnt_val); in set_ref()
452 hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr); in set_ref()
453 hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr); in set_ref()
454 hantro_write_addr(vpu, G2_REF_MV_ADDR(i), mv_addr); in set_ref()
469 hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), luma_addr); in set_ref()
470 hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), chroma_addr); in set_ref()
471 hantro_write_addr(vpu, G2_REF_MV_ADDR(i++), mv_addr); in set_ref()
473 hantro_write_addr(vpu, G2_OUT_LUMA_ADDR, luma_addr); in set_ref()
474 hantro_write_addr(vpu, G2_OUT_CHROMA_ADDR, chroma_addr); in set_ref()
475 hantro_write_addr(vpu, G2_OUT_MV_ADDR, mv_addr); in set_ref()
478 hantro_write_addr(vpu, G2_REF_LUMA_ADDR(i), 0); in set_ref()
479 hantro_write_addr(vpu, G2_REF_CHROMA_ADDR(i), 0); in set_ref()
480 hantro_write_addr(vpu, G2_REF_MV_ADDR(i), 0); in set_ref()
483 hantro_reg_write(vpu, &g2_refer_lterm_e, dpb_longterm_e); in set_ref()
491 struct hantro_dev *vpu = ctx->dev; in set_buffers() local
502 hantro_write_addr(vpu, G2_STREAM_ADDR, src_dma); in set_buffers()
503 hantro_reg_write(vpu, &g2_stream_len, src_len); in set_buffers()
504 hantro_reg_write(vpu, &g2_strm_buffer_len, src_buf_len); in set_buffers()
505 hantro_reg_write(vpu, &g2_strm_start_offset, 0); in set_buffers()
506 hantro_reg_write(vpu, &g2_write_mvs_e, 1); in set_buffers()
508 hantro_write_addr(vpu, G2_TILE_SIZES_ADDR, ctx->hevc_dec.tile_sizes.dma); in set_buffers()
509 hantro_write_addr(vpu, G2_TILE_FILTER_ADDR, ctx->hevc_dec.tile_filter.dma); in set_buffers()
510 hantro_write_addr(vpu, G2_TILE_SAO_ADDR, ctx->hevc_dec.tile_sao.dma); in set_buffers()
511 hantro_write_addr(vpu, G2_TILE_BSD_ADDR, ctx->hevc_dec.tile_bsd.dma); in set_buffers()
516 struct hantro_dev *vpu = ctx->dev; in prepare_scaling_list_buffer() local
525 hantro_reg_write(vpu, &g2_scaling_list_e, scaling_list_enabled); in prepare_scaling_list_buffer()
561 hantro_write_addr(vpu, G2_HEVC_SCALING_LIST_ADDR, ctx->hevc_dec.scaling_lists.dma); in prepare_scaling_list_buffer()
566 struct hantro_dev *vpu = ctx->dev; in hantro_g2_hevc_dec_run() local
569 hantro_g2_check_idle(vpu); in hantro_g2_hevc_dec_run()
591 hantro_reg_write(vpu, &g2_mode, HEVC_DEC_MODE); in hantro_g2_hevc_dec_run()
592 hantro_reg_write(vpu, &g2_clk_gate_e, 1); in hantro_g2_hevc_dec_run()
595 hantro_reg_write(vpu, &g2_out_dis, 0); in hantro_g2_hevc_dec_run()
598 hantro_reg_write(vpu, &g2_ref_compress_bypass, 1); in hantro_g2_hevc_dec_run()
601 hantro_reg_write(vpu, &g2_buswidth, BUS_WIDTH_128); in hantro_g2_hevc_dec_run()
602 hantro_reg_write(vpu, &g2_max_burst, 16); in hantro_g2_hevc_dec_run()
605 hantro_reg_write(vpu, &g2_strm_swap, 0xf); in hantro_g2_hevc_dec_run()
606 hantro_reg_write(vpu, &g2_dirmv_swap, 0xf); in hantro_g2_hevc_dec_run()
607 hantro_reg_write(vpu, &g2_compress_swap, 0xf); in hantro_g2_hevc_dec_run()
610 vdpu_write(vpu, G2_REG_INTERRUPT_DEC_E, G2_REG_INTERRUPT); in hantro_g2_hevc_dec_run()