Lines Matching +full:v +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
16 #define G1_REG_INTERRUPT_DEC_PIC_INF BIT(24)
17 #define G1_REG_INTERRUPT_DEC_TIMEOUT BIT(18)
18 #define G1_REG_INTERRUPT_DEC_SLICE_INT BIT(17)
19 #define G1_REG_INTERRUPT_DEC_ERROR_INT BIT(16)
20 #define G1_REG_INTERRUPT_DEC_ASO_INT BIT(15)
21 #define G1_REG_INTERRUPT_DEC_BUFFER_INT BIT(14)
22 #define G1_REG_INTERRUPT_DEC_BUS_INT BIT(13)
23 #define G1_REG_INTERRUPT_DEC_RDY_INT BIT(12)
24 #define G1_REG_INTERRUPT_DEC_IRQ BIT(8)
25 #define G1_REG_INTERRUPT_DEC_IRQ_DIS BIT(4)
26 #define G1_REG_INTERRUPT_DEC_E BIT(0)
29 #define G1_REG_CONFIG_DEC_TIMEOUT_E BIT(23)
30 #define G1_REG_CONFIG_DEC_STRSWAP32_E BIT(22)
31 #define G1_REG_CONFIG_DEC_STRENDIAN_E BIT(21)
32 #define G1_REG_CONFIG_DEC_INSWAP32_E BIT(20)
33 #define G1_REG_CONFIG_DEC_OUTSWAP32_E BIT(19)
34 #define G1_REG_CONFIG_DEC_DATA_DISC_E BIT(18)
35 #define G1_REG_CONFIG_TILED_MODE_MSB BIT(17)
36 #define G1_REG_CONFIG_DEC_OUT_TILED_E BIT(17)
38 #define G1_REG_CONFIG_DEC_CLK_GATE_E BIT(10)
39 #define G1_REG_CONFIG_DEC_IN_ENDIAN BIT(9)
40 #define G1_REG_CONFIG_DEC_OUT_ENDIAN BIT(8)
42 #define G1_REG_CONFIG_TILED_MODE_LSB BIT(7)
43 #define G1_REG_CONFIG_DEC_ADV_PRE_DIS BIT(6)
44 #define G1_REG_CONFIG_DEC_SCMD_DIS BIT(5)
48 #define G1_REG_DEC_CTRL0_RLC_MODE_E BIT(27)
49 #define G1_REG_DEC_CTRL0_SKIP_MODE BIT(26)
50 #define G1_REG_DEC_CTRL0_DIVX3_E BIT(25)
51 #define G1_REG_DEC_CTRL0_PJPEG_E BIT(24)
52 #define G1_REG_DEC_CTRL0_PIC_INTERLACE_E BIT(23)
53 #define G1_REG_DEC_CTRL0_PIC_FIELDMODE_E BIT(22)
54 #define G1_REG_DEC_CTRL0_PIC_B_E BIT(21)
55 #define G1_REG_DEC_CTRL0_PIC_INTER_E BIT(20)
56 #define G1_REG_DEC_CTRL0_PIC_TOPFIELD_E BIT(19)
57 #define G1_REG_DEC_CTRL0_FWD_INTERLACE_E BIT(18)
58 #define G1_REG_DEC_CTRL0_SORENSON_E BIT(17)
59 #define G1_REG_DEC_CTRL0_REF_TOPFIELD_E BIT(16)
60 #define G1_REG_DEC_CTRL0_DEC_OUT_DIS BIT(15)
61 #define G1_REG_DEC_CTRL0_FILTERING_DIS BIT(14)
62 #define G1_REG_DEC_CTRL0_WEBP_E BIT(13)
63 #define G1_REG_DEC_CTRL0_MVC_E BIT(13)
64 #define G1_REG_DEC_CTRL0_PIC_FIXED_QUANT BIT(13)
65 #define G1_REG_DEC_CTRL0_WRITE_MVS_E BIT(12)
66 #define G1_REG_DEC_CTRL0_REFTOPFIRST_E BIT(11)
67 #define G1_REG_DEC_CTRL0_SEQ_MBAFF_E BIT(10)
68 #define G1_REG_DEC_CTRL0_PICORD_COUNT_E BIT(9)
69 #define G1_REG_DEC_CTRL0_DEC_AHB_HLOCK_E BIT(8)
78 #define G1_REG_DEC_CTRL1_ALT_SCAN_E BIT(6)
79 #define G1_REG_DEC_CTRL1_TOPFIELDFIRST_E BIT(5)
83 #define G1_REG_DEC_CTRL1_PIC_REFER_FLAG BIT(0)
86 #define G1_REG_DEC_CTRL2_SYNC_MARKER_E BIT(25)
87 #define G1_REG_DEC_CTRL2_TYPE1_QUANT_E BIT(24)
90 #define G1_REG_DEC_CTRL2_FIELDPIC_FLAG_E BIT(0)
93 #define G1_REG_DEC_CTRL2_DQ_PROFILE BIT(24)
94 #define G1_REG_DEC_CTRL2_DQBI_LEVEL BIT(23)
95 #define G1_REG_DEC_CTRL2_RANGE_RED_FRM_E BIT(22)
96 #define G1_REG_DEC_CTRL2_FAST_UVMC_E BIT(20)
97 #define G1_REG_DEC_CTRL2_TRANSDCTAB BIT(17)
105 #define G1_REG_DEC_CTRL2_QSCALE_TYPE BIT(24)
106 #define G1_REG_DEC_CTRL2_CON_MV_E BIT(4)
108 #define G1_REG_DEC_CTRL2_INTRA_VLC_TAB BIT(1)
109 #define G1_REG_DEC_CTRL2_FRAME_PRED_DCT BIT(0)
112 #define G1_REG_DEC_CTRL2_JPEG_FILRIGHT_E BIT(7)
113 #define G1_REG_DEC_CTRL2_JPEG_STREAM_ALL BIT(6)
114 #define G1_REG_DEC_CTRL2_CR_AC_VLCTABLE BIT(5)
115 #define G1_REG_DEC_CTRL2_CB_AC_VLCTABLE BIT(4)
116 #define G1_REG_DEC_CTRL2_CR_DC_VLCTABLE BIT(3)
117 #define G1_REG_DEC_CTRL2_CB_DC_VLCTABLE BIT(2)
118 #define G1_REG_DEC_CTRL2_CR_DC_VLCTABLE3 BIT(1)
119 #define G1_REG_DEC_CTRL2_CB_DC_VLCTABLE3 BIT(0)
121 #define G1_REG_DEC_CTRL2_HUFFMAN_E BIT(17)
122 #define G1_REG_DEC_CTRL2_MULTISTREAM_E BIT(16)
128 #define G1_REG_DEC_CTRL3_START_CODE_E BIT(31)
130 #define G1_REG_DEC_CTRL3_CH_8PIX_ILEAV_E BIT(24)
134 #define G1_REG_DEC_CTRL4_CABAC_E BIT(31)
135 #define G1_REG_DEC_CTRL4_BLACKWHITE_E BIT(30)
136 #define G1_REG_DEC_CTRL4_DIR_8X8_INFER_E BIT(29)
137 #define G1_REG_DEC_CTRL4_WEIGHT_PRED_E BIT(28)
139 #define G1_REG_DEC_CTRL4_AVS_H264_H_EXT BIT(25)
142 #define G1_REG_DEC_CTRL4_BITPLANE0_E BIT(31)
143 #define G1_REG_DEC_CTRL4_BITPLANE1_E BIT(30)
144 #define G1_REG_DEC_CTRL4_BITPLANE2_E BIT(29)
147 #define G1_REG_DEC_CTRL4_TTMBF BIT(19)
149 #define G1_REG_DEC_CTRL4_VC1_HEIGHT_EXT BIT(13)
150 #define G1_REG_DEC_CTRL4_BILIN_MC_E BIT(12)
151 #define G1_REG_DEC_CTRL4_UNIQP_E BIT(11)
152 #define G1_REG_DEC_CTRL4_HALFQP_E BIT(10)
154 #define G1_REG_DEC_CTRL4_2ND_BYTE_EMUL_E BIT(7)
155 #define G1_REG_DEC_CTRL4_DQUANT_E BIT(6)
156 #define G1_REG_DEC_CTRL4_VC1_ADV_E BIT(5)
157 #define G1_REG_DEC_CTRL4_PJPEG_FILDOWN_E BIT(26)
158 #define G1_REG_DEC_CTRL4_PJPEG_WDIV8 BIT(25)
159 #define G1_REG_DEC_CTRL4_PJPEG_HDIV8 BIT(24)
166 #define G1_REG_DEC_CTRL4_CH_MV_RES BIT(13)
169 #define G1_REG_DEC_CTRL4_VP7_VERSION BIT(5)
171 #define G1_REG_DEC_CTRL5_CONST_INTRA_E BIT(31)
172 #define G1_REG_DEC_CTRL5_FILT_CTRL_PRES BIT(30)
173 #define G1_REG_DEC_CTRL5_RDPIC_CNT_PRES BIT(29)
174 #define G1_REG_DEC_CTRL5_8X8TRANS_FLAG_E BIT(28)
176 #define G1_REG_DEC_CTRL5_IDR_PIC_E BIT(16)
182 #define G1_REG_DEC_CTRL5_VARIANCE_TEST_E BIT(13)
185 #define G1_REG_DEC_CTRL5_DIVX_IDCT_E BIT(8)
199 #define G1_REG_DEC_CTRL6_ICOMP0_E BIT(24)
212 #define G1_REG_FWD_PIC1_ICOMP1_E BIT(24)
216 #define G1_REG_FWD_PIC1_SEGMENT_UPD_E BIT(1)
217 #define G1_REG_FWD_PIC1_SEGMENT_E BIT(0)
225 #define G1_REG_DEC_CTRL7_ICOMP2_E BIT(24)
236 #define G1_REG_ADDR_REF_FIELD_E BIT(1)
237 #define G1_REG_ADDR_REF_TOPC_E BIT(0)
239 #define G1_REG_REF_PIC_FILT_TYPE_E BIT(31)
292 #define G1_REG_REF_BUF_CTRL_REFBU_E BIT(31)
295 #define G1_REG_REF_BUF_CTRL_REFBU_EVAL_E BIT(13)
296 #define G1_REG_REF_BUF_CTRL_REFBU_FPARMOD_E BIT(12)
299 #define G1_REG_REF_BUF_CTRL2_REFBU2_BUF_E BIT(31)
305 /* Post-processor registers. */
307 #define G1_REG_PP_READY_IRQ BIT(12)
308 #define G1_REG_PP_IRQ BIT(8)
309 #define G1_REG_PP_IRQ_DIS BIT(4)
310 #define G1_REG_PP_PIPELINE_EN BIT(1)
311 #define G1_REG_PP_EXTERNAL_TRIGGER BIT(0)
313 #define G1_REG_PP_AXI_RD_ID(v) (((v) << 24) & GENMASK(31, 24)) argument
314 #define G1_REG_PP_AXI_WR_ID(v) (((v) << 16) & GENMASK(23, 16)) argument
315 #define G1_REG_PP_INSWAP32_E(v) ((v) ? BIT(10) : 0) argument
316 #define G1_REG_PP_DATA_DISC_E(v) ((v) ? BIT(9) : 0) argument
317 #define G1_REG_PP_CLK_GATE_E(v) ((v) ? BIT(8) : 0) argument
318 #define G1_REG_PP_IN_ENDIAN(v) ((v) ? BIT(7) : 0) argument
319 #define G1_REG_PP_OUT_ENDIAN(v) ((v) ? BIT(6) : 0) argument
320 #define G1_REG_PP_OUTSWAP32_E(v) ((v) ? BIT(5) : 0) argument
321 #define G1_REG_PP_MAX_BURST(v) (((v) << 0) & GENMASK(4, 0)) argument
332 #define G1_REG_PP_INPUT_SIZE_HEIGHT(v) (((v) << 9) & GENMASK(16, 9)) argument
333 #define G1_REG_PP_INPUT_SIZE_WIDTH(v) (((v) << 0) & GENMASK(8, 0)) argument
335 #define G1_REG_PP_PADD_R(v) (((v) << 23) & GENMASK(27, 23)) argument
336 #define G1_REG_PP_PADD_G(v) (((v) << 18) & GENMASK(22, 18)) argument
337 #define G1_REG_PP_RANGEMAP_Y(v) ((v) ? BIT(31) : 0) argument
338 #define G1_REG_PP_RANGEMAP_C(v) ((v) ? BIT(30) : 0) argument
339 #define G1_REG_PP_YCBCR_RANGE(v) ((v) ? BIT(29) : 0) argument
340 #define G1_REG_PP_RGB_16(v) ((v) ? BIT(28) : 0) argument
342 #define G1_REG_PP_PADD_B(v) (((v) << 18) & GENMASK(22, 18)) argument
347 #define G1_REG_PP_CONTROL_IN_FMT(v) (((v) << 29) & GENMASK(31, 29)) argument
348 #define G1_REG_PP_CONTROL_OUT_FMT(v) (((v) << 26) & GENMASK(28, 26)) argument
349 #define G1_REG_PP_CONTROL_OUT_HEIGHT(v) (((v) << 15) & GENMASK(25, 15)) argument
350 #define G1_REG_PP_CONTROL_OUT_WIDTH(v) (((v) << 4) & GENMASK(14, 4)) argument
352 #define G1_REG_PP_ORIG_WIDTH(v) (((v) << 23) & GENMASK(31, 23)) argument