Lines Matching +full:mt8183 +full:- +full:mdp3 +full:- +full:rsz
1 // SPDX-License-Identifier: GPL-2.0-only
4 * Author: Ping-Hsun Wu <ping-hsun.wu@mediatek.com>
11 #include "mtk-mdp3-cfg.h"
12 #include "mtk-mdp3-comp.h"
13 #include "mtk-mdp3-core.h"
14 #include "mtk-mdp3-regs.h"
31 return ctx->comp->mdp_dev->mdp_data->mdp_cfg; in __get_plat_cfg()
39 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0); in get_comp_flag()
40 rsz1 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RSZ1); in get_comp_flag()
44 if (mdp_cfg && mdp_cfg->rdma_rsz1_sram_sharing) in get_comp_flag()
45 if (ctx->comp->inner_id == rdma0) in get_comp_flag()
48 return BIT(ctx->comp->inner_id); in get_comp_flag()
54 phys_addr_t base = ctx->comp->reg_base; in init_rdma()
55 u8 subsys_id = ctx->comp->subsys_id; in init_rdma()
58 rdma0 = mdp_cfg_get_id_inner(ctx->comp->mdp_dev, MDP_COMP_RDMA0); in init_rdma()
60 return -EINVAL; in init_rdma()
62 if (mdp_cfg && mdp_cfg->rdma_support_10bit) { in init_rdma()
63 struct mdp_comp *prz1 = ctx->comp->mdp_dev->comp[MDP_COMP_RSZ1]; in init_rdma()
66 if (ctx->comp->inner_id == rdma0 && prz1) in init_rdma()
67 MM_REG_WRITE(cmd, subsys_id, prz1->reg_base, PRZ_ENABLE, in init_rdma()
83 u32 colorformat = ctx->input->buffer.format.colorformat; in config_rdma_frame()
86 phys_addr_t base = ctx->comp->reg_base; in config_rdma_frame()
87 u8 subsys_id = ctx->comp->subsys_id; in config_rdma_frame()
90 if (mdp_cfg && mdp_cfg->rdma_support_10bit) { in config_rdma_frame()
102 (1 << 16), //enable pre-ultra in config_rdma_frame()
106 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
107 reg = CFG_COMP(MT8183, ctx->param, rdma.src_ctrl); in config_rdma_frame()
112 if (mdp_cfg->rdma_support_10bit && en_ufo) { in config_rdma_frame()
114 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
115 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_y); in config_rdma_frame()
119 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
120 reg = CFG_COMP(MT8183, ctx->param, rdma.ufo_dec_c); in config_rdma_frame()
126 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
127 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd_in_pxl); in config_rdma_frame()
134 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
135 reg = CFG_COMP(MT8183, ctx->param, rdma.control); in config_rdma_frame()
139 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
140 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); in config_rdma_frame()
143 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
144 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[1]); in config_rdma_frame()
147 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
148 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[2]); in config_rdma_frame()
152 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
153 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); in config_rdma_frame()
156 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
157 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[1]); in config_rdma_frame()
160 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
161 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[2]); in config_rdma_frame()
165 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
166 reg = CFG_COMP(MT8183, ctx->param, rdma.mf_bkgd); in config_rdma_frame()
169 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
170 reg = CFG_COMP(MT8183, ctx->param, rdma.sf_bkgd); in config_rdma_frame()
174 if (CFG_CHECK(MT8183, p_id)) in config_rdma_frame()
175 reg = CFG_COMP(MT8183, ctx->param, rdma.transform); in config_rdma_frame()
186 u32 colorformat = ctx->input->buffer.format.colorformat; in config_rdma_subfrm()
189 phys_addr_t base = ctx->comp->reg_base; in config_rdma_subfrm()
190 u8 subsys_id = ctx->comp->subsys_id; in config_rdma_subfrm()
198 if (CFG_CHECK(MT8183, p_id)) in config_rdma_subfrm()
199 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); in config_rdma_subfrm()
205 if (mdp_cfg->rdma_support_10bit && block10bit && en_ufo) { in config_rdma_subfrm()
206 if (CFG_CHECK(MT8183, p_id)) in config_rdma_subfrm()
207 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset_0_p); in config_rdma_subfrm()
215 if (CFG_CHECK(MT8183, p_id)) in config_rdma_subfrm()
216 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[1]); in config_rdma_subfrm()
220 if (CFG_CHECK(MT8183, p_id)) in config_rdma_subfrm()
221 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[2]); in config_rdma_subfrm()
225 if (CFG_CHECK(MT8183, p_id)) in config_rdma_subfrm()
226 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].src); in config_rdma_subfrm()
230 if (CFG_CHECK(MT8183, p_id)) in config_rdma_subfrm()
231 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip); in config_rdma_subfrm()
235 if (CFG_CHECK(MT8183, p_id)) in config_rdma_subfrm()
236 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].clip_ofst); in config_rdma_subfrm()
240 if (CFG_CHECK(MT8183, p_id)) { in config_rdma_subfrm()
241 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_rdma_subfrm()
242 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_rdma_subfrm()
244 if (mdp_cfg && mdp_cfg->rdma_upsample_repeat_only) in config_rdma_subfrm()
245 if ((csf_r - csf_l + 1) > 320) in config_rdma_subfrm()
254 struct device *dev = &ctx->comp->mdp_dev->pdev->dev; in wait_rdma_event()
255 phys_addr_t base = ctx->comp->reg_base; in wait_rdma_event()
256 u8 subsys_id = ctx->comp->subsys_id; in wait_rdma_event()
258 if (ctx->comp->alias_id == 0) in wait_rdma_event()
259 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_rdma_event()
278 phys_addr_t base = ctx->comp->reg_base; in init_rsz()
279 u8 subsys_id = ctx->comp->subsys_id; in init_rsz()
281 /* Reset RSZ */ in init_rsz()
284 /* Enable RSZ */ in init_rsz()
293 phys_addr_t base = ctx->comp->reg_base; in config_rsz_frame()
294 u8 subsys_id = ctx->comp->subsys_id; in config_rsz_frame()
298 if (CFG_CHECK(MT8183, p_id)) in config_rsz_frame()
299 bypass = CFG_COMP(MT8183, ctx->param, frame.bypass); in config_rsz_frame()
302 /* Disable RSZ */ in config_rsz_frame()
307 if (CFG_CHECK(MT8183, p_id)) in config_rsz_frame()
308 reg = CFG_COMP(MT8183, ctx->param, rsz.control1); in config_rsz_frame()
311 if (CFG_CHECK(MT8183, p_id)) in config_rsz_frame()
312 reg = CFG_COMP(MT8183, ctx->param, rsz.control2); in config_rsz_frame()
315 if (CFG_CHECK(MT8183, p_id)) in config_rsz_frame()
316 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_x); in config_rsz_frame()
319 if (CFG_CHECK(MT8183, p_id)) in config_rsz_frame()
320 reg = CFG_COMP(MT8183, ctx->param, rsz.coeff_step_y); in config_rsz_frame()
330 phys_addr_t base = ctx->comp->reg_base; in config_rsz_subfrm()
331 u8 subsys_id = ctx->comp->subsys_id; in config_rsz_subfrm()
335 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
336 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].control2); in config_rsz_subfrm()
339 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
340 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].src); in config_rsz_subfrm()
344 if (CFG_CHECK(MT8183, p_id)) { in config_rsz_subfrm()
345 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_rsz_subfrm()
346 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_rsz_subfrm()
348 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) in config_rsz_subfrm()
349 if ((csf_r - csf_l + 1) <= 16) in config_rsz_subfrm()
353 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
354 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left); in config_rsz_subfrm()
357 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
358 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.left_subpix); in config_rsz_subfrm()
362 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
363 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top); in config_rsz_subfrm()
366 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
367 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].luma.top_subpix); in config_rsz_subfrm()
370 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
371 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left); in config_rsz_subfrm()
375 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
376 reg = CFG_COMP(MT8183, ctx->param, subfrms[index].chroma.left_subpix); in config_rsz_subfrm()
381 if (CFG_CHECK(MT8183, p_id)) in config_rsz_subfrm()
382 reg = CFG_COMP(MT8183, ctx->param, rsz.subfrms[index].clip); in config_rsz_subfrm()
394 if (mdp_cfg && mdp_cfg->rsz_disable_dcm_small_sample) { in advance_rsz_subfrm()
395 phys_addr_t base = ctx->comp->reg_base; in advance_rsz_subfrm()
396 u8 subsys_id = ctx->comp->subsys_id; in advance_rsz_subfrm()
399 if (CFG_CHECK(MT8183, p_id)) { in advance_rsz_subfrm()
400 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in advance_rsz_subfrm()
401 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in advance_rsz_subfrm()
404 if ((csf_r - csf_l + 1) <= 16) in advance_rsz_subfrm()
422 phys_addr_t base = ctx->comp->reg_base; in init_wrot()
423 u8 subsys_id = ctx->comp->subsys_id; in init_wrot()
438 phys_addr_t base = ctx->comp->reg_base; in config_wrot_frame()
439 u8 subsys_id = ctx->comp->subsys_id; in config_wrot_frame()
443 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
444 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); in config_wrot_frame()
447 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
448 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[1]); in config_wrot_frame()
451 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
452 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[2]); in config_wrot_frame()
456 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
457 reg = CFG_COMP(MT8183, ctx->param, wrot.control); in config_wrot_frame()
461 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
462 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); in config_wrot_frame()
466 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
467 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[1]); in config_wrot_frame()
470 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
471 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[2]); in config_wrot_frame()
475 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
476 reg = CFG_COMP(MT8183, ctx->param, wrot.mat_ctrl); in config_wrot_frame()
485 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
486 reg = CFG_COMP(MT8183, ctx->param, wrot.fifo_test); in config_wrot_frame()
491 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) { in config_wrot_frame()
492 if (CFG_CHECK(MT8183, p_id)) in config_wrot_frame()
493 reg = CFG_COMP(MT8183, ctx->param, wrot.filter); in config_wrot_frame()
504 phys_addr_t base = ctx->comp->reg_base; in config_wrot_subfrm()
505 u8 subsys_id = ctx->comp->subsys_id; in config_wrot_subfrm()
509 if (CFG_CHECK(MT8183, p_id)) in config_wrot_subfrm()
510 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); in config_wrot_subfrm()
514 if (CFG_CHECK(MT8183, p_id)) in config_wrot_subfrm()
515 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[1]); in config_wrot_subfrm()
519 if (CFG_CHECK(MT8183, p_id)) in config_wrot_subfrm()
520 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[2]); in config_wrot_subfrm()
524 if (CFG_CHECK(MT8183, p_id)) in config_wrot_subfrm()
525 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].src); in config_wrot_subfrm()
529 if (CFG_CHECK(MT8183, p_id)) in config_wrot_subfrm()
530 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip); in config_wrot_subfrm()
533 if (CFG_CHECK(MT8183, p_id)) in config_wrot_subfrm()
534 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].clip_ofst); in config_wrot_subfrm()
538 if (CFG_CHECK(MT8183, p_id)) in config_wrot_subfrm()
539 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].main_buf); in config_wrot_subfrm()
552 struct device *dev = &ctx->comp->mdp_dev->pdev->dev; in wait_wrot_event()
553 phys_addr_t base = ctx->comp->reg_base; in wait_wrot_event()
554 u8 subsys_id = ctx->comp->subsys_id; in wait_wrot_event()
556 if (ctx->comp->alias_id == 0) in wait_wrot_event()
557 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_wrot_event()
561 if (mdp_cfg && mdp_cfg->wrot_filter_constraint) in wait_wrot_event()
581 phys_addr_t base = ctx->comp->reg_base; in init_wdma()
582 u8 subsys_id = ctx->comp->subsys_id; in init_wdma()
595 phys_addr_t base = ctx->comp->reg_base; in config_wdma_frame()
596 u8 subsys_id = ctx->comp->subsys_id; in config_wdma_frame()
603 if (CFG_CHECK(MT8183, p_id)) in config_wdma_frame()
604 reg = CFG_COMP(MT8183, ctx->param, wdma.wdma_cfg); in config_wdma_frame()
608 if (CFG_CHECK(MT8183, p_id)) in config_wdma_frame()
609 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); in config_wdma_frame()
612 if (CFG_CHECK(MT8183, p_id)) in config_wdma_frame()
613 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[1]); in config_wdma_frame()
616 if (CFG_CHECK(MT8183, p_id)) in config_wdma_frame()
617 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[2]); in config_wdma_frame()
621 if (CFG_CHECK(MT8183, p_id)) in config_wdma_frame()
622 reg = CFG_COMP(MT8183, ctx->param, wdma.w_in_byte); in config_wdma_frame()
626 if (CFG_CHECK(MT8183, p_id)) in config_wdma_frame()
627 reg = CFG_COMP(MT8183, ctx->param, wdma.uv_stride); in config_wdma_frame()
640 phys_addr_t base = ctx->comp->reg_base; in config_wdma_subfrm()
641 u8 subsys_id = ctx->comp->subsys_id; in config_wdma_subfrm()
645 if (CFG_CHECK(MT8183, p_id)) in config_wdma_subfrm()
646 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); in config_wdma_subfrm()
650 if (CFG_CHECK(MT8183, p_id)) in config_wdma_subfrm()
651 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[1]); in config_wdma_subfrm()
655 if (CFG_CHECK(MT8183, p_id)) in config_wdma_subfrm()
656 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[2]); in config_wdma_subfrm()
660 if (CFG_CHECK(MT8183, p_id)) in config_wdma_subfrm()
661 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].src); in config_wdma_subfrm()
665 if (CFG_CHECK(MT8183, p_id)) in config_wdma_subfrm()
666 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip); in config_wdma_subfrm()
670 if (CFG_CHECK(MT8183, p_id)) in config_wdma_subfrm()
671 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].clip_ofst); in config_wdma_subfrm()
683 phys_addr_t base = ctx->comp->reg_base; in wait_wdma_event()
684 u8 subsys_id = ctx->comp->subsys_id; in wait_wdma_event()
686 MM_REG_WAIT(cmd, ctx->comp->gce_event[MDP_GCE_EVENT_EOF]); in wait_wdma_event()
702 phys_addr_t base = ctx->comp->reg_base; in init_ccorr()
703 u8 subsys_id = ctx->comp->subsys_id; in init_ccorr()
715 phys_addr_t base = ctx->comp->reg_base; in config_ccorr_subfrm()
716 u8 subsys_id = ctx->comp->subsys_id; in config_ccorr_subfrm()
721 if (CFG_CHECK(MT8183, p_id)) { in config_ccorr_subfrm()
722 csf_l = CFG_COMP(MT8183, ctx->param, subfrms[index].in.left); in config_ccorr_subfrm()
723 csf_r = CFG_COMP(MT8183, ctx->param, subfrms[index].in.right); in config_ccorr_subfrm()
724 csf_t = CFG_COMP(MT8183, ctx->param, subfrms[index].in.top); in config_ccorr_subfrm()
725 csf_b = CFG_COMP(MT8183, ctx->param, subfrms[index].in.bottom); in config_ccorr_subfrm()
728 hsize = csf_r - csf_l + 1; in config_ccorr_subfrm()
729 vsize = csf_b - csf_t + 1; in config_ccorr_subfrm()
751 .compatible = "mediatek,mt8183-mdp3-rdma",
754 .compatible = "mediatek,mt8183-mdp3-ccorr",
757 .compatible = "mediatek,mt8183-mdp3-rsz",
760 .compatible = "mediatek,mt8183-mdp3-wrot",
763 .compatible = "mediatek,mt8183-mdp3-wdma",
789 for (i = 0; i < mdp->mdp_data->comp_data_len; i++) in mdp_comp_get_id()
790 if (mdp->mdp_data->comp_data[i].match.type == type && in mdp_comp_get_id()
791 mdp->mdp_data->comp_data[i].match.alias_id == alias_id) in mdp_comp_get_id()
793 return -ENODEV; in mdp_comp_get_id()
801 if (comp->comp_dev && is_dma_capable(comp->type)) { in mdp_comp_clock_on()
802 ret = pm_runtime_resume_and_get(comp->comp_dev); in mdp_comp_clock_on()
806 ret, comp->type, comp->inner_id); in mdp_comp_clock_on()
811 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_on()
812 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_on()
814 ret = clk_prepare_enable(comp->clks[i]); in mdp_comp_clock_on()
818 i, comp->type, comp->inner_id); in mdp_comp_clock_on()
826 while (--i >= 0) { in mdp_comp_clock_on()
827 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_on()
829 clk_disable_unprepare(comp->clks[i]); in mdp_comp_clock_on()
831 if (comp->comp_dev && is_dma_capable(comp->type)) in mdp_comp_clock_on()
832 pm_runtime_put_sync(comp->comp_dev); in mdp_comp_clock_on()
841 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_off()
842 if (IS_ERR_OR_NULL(comp->clks[i])) in mdp_comp_clock_off()
844 clk_disable_unprepare(comp->clks[i]); in mdp_comp_clock_off()
847 if (comp->comp_dev && is_dma_capable(comp->type)) in mdp_comp_clock_off()
848 pm_runtime_put(comp->comp_dev); in mdp_comp_clock_off()
881 return -EINVAL; in mdp_get_subsys_id()
887 comp->public_id, comp->inner_id, comp->type); in mdp_get_subsys_id()
888 return -ENODEV; in mdp_get_subsys_id()
891 index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst; in mdp_get_subsys_id()
892 ret = cmdq_dev_get_client_reg(&comp_pdev->dev, &cmdq_reg, index); in mdp_get_subsys_id()
894 dev_err(&comp_pdev->dev, "cmdq_dev_get_subsys fail!\n"); in mdp_get_subsys_id()
895 put_device(&comp_pdev->dev); in mdp_get_subsys_id()
896 return -EINVAL; in mdp_get_subsys_id()
899 comp->subsys_id = cmdq_reg.subsys; in mdp_get_subsys_id()
900 dev_dbg(&comp_pdev->dev, "subsys id=%d\n", cmdq_reg.subsys); in mdp_get_subsys_id()
901 put_device(&comp_pdev->dev); in mdp_get_subsys_id()
913 index = mdp->mdp_data->comp_data[comp->public_id].info.dts_reg_ofst; in __mdp_comp_init()
919 comp->mdp_dev = mdp; in __mdp_comp_init()
920 comp->regs = of_iomap(node, 0); in __mdp_comp_init()
921 comp->reg_base = base; in __mdp_comp_init()
927 struct device *dev = &mdp->pdev->dev; in mdp_comp_init()
935 return -EINVAL; in mdp_comp_init()
941 node->name); in mdp_comp_init()
942 return -ENODEV; in mdp_comp_init()
945 comp->comp_dev = &pdev_c->dev; in mdp_comp_init()
946 comp->public_id = id; in mdp_comp_init()
947 comp->type = mdp->mdp_data->comp_data[id].match.type; in mdp_comp_init()
948 comp->inner_id = mdp->mdp_data->comp_data[id].match.inner_id; in mdp_comp_init()
949 comp->alias_id = mdp->mdp_data->comp_data[id].match.alias_id; in mdp_comp_init()
950 comp->ops = mdp_comp_ops[comp->type]; in mdp_comp_init()
953 comp->clk_num = mdp->mdp_data->comp_data[id].info.clk_num; in mdp_comp_init()
954 comp->clks = devm_kzalloc(dev, sizeof(struct clk *) * comp->clk_num, in mdp_comp_init()
956 if (!comp->clks) in mdp_comp_init()
957 return -ENOMEM; in mdp_comp_init()
959 clk_ofst = mdp->mdp_data->comp_data[id].info.clk_ofst; in mdp_comp_init()
961 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_init()
962 comp->clks[i] = of_clk_get(node, i + clk_ofst); in mdp_comp_init()
963 if (IS_ERR(comp->clks[i])) in mdp_comp_init()
970 if (is_bypass_gce_event(comp->type) || in mdp_comp_init()
971 of_property_read_u32_index(node, "mediatek,gce-events", in mdp_comp_init()
975 comp->gce_event[MDP_GCE_EVENT_SOF] = event; in mdp_comp_init()
978 if (is_dma_capable(comp->type)) { in mdp_comp_init()
979 if (of_property_read_u32_index(node, "mediatek,gce-events", in mdp_comp_init()
982 return -EINVAL; in mdp_comp_init()
988 comp->gce_event[MDP_GCE_EVENT_EOF] = event; in mdp_comp_init()
998 if (comp->comp_dev && comp->clks) { in mdp_comp_deinit()
999 devm_kfree(&comp->mdp_dev->pdev->dev, comp->clks); in mdp_comp_deinit()
1000 comp->clks = NULL; in mdp_comp_deinit()
1003 if (comp->regs) in mdp_comp_deinit()
1004 iounmap(comp->regs); in mdp_comp_deinit()
1011 struct device *dev = &mdp->pdev->dev; in mdp_comp_create()
1015 if (mdp->comp[id]) in mdp_comp_create()
1016 return ERR_PTR(-EEXIST); in mdp_comp_create()
1020 return ERR_PTR(-ENOMEM); in mdp_comp_create()
1027 mdp->comp[id] = comp; in mdp_comp_create()
1028 mdp->comp[id]->mdp_dev = mdp; in mdp_comp_create()
1031 dev->of_node->name, comp->type, comp->alias_id, id, comp->inner_id, in mdp_comp_create()
1032 (u32)comp->reg_base, comp->regs); in mdp_comp_create()
1038 struct device *dev = &mdp->pdev->dev; in mdp_comp_sub_create()
1042 parent = dev->of_node->parent; in mdp_comp_sub_create()
1050 of_id = of_match_node(mdp->mdp_data->mdp_sub_comp_dt_ids, node); in mdp_comp_sub_create()
1059 type = (enum mdp_comp_type)(uintptr_t)of_id->data; in mdp_comp_sub_create()
1066 ret = -EINVAL; in mdp_comp_sub_create()
1088 for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { in mdp_comp_destroy()
1089 if (mdp->comp[i]) { in mdp_comp_destroy()
1090 if (is_dma_capable(mdp->comp[i]->type)) in mdp_comp_destroy()
1091 pm_runtime_disable(mdp->comp[i]->comp_dev); in mdp_comp_destroy()
1092 mdp_comp_deinit(mdp->comp[i]); in mdp_comp_destroy()
1093 devm_kfree(mdp->comp[i]->comp_dev, mdp->comp[i]); in mdp_comp_destroy()
1094 mdp->comp[i] = NULL; in mdp_comp_destroy()
1101 struct device *dev = &mdp->pdev->dev; in mdp_comp_config()
1106 p_id = mdp->mdp_data->mdp_plat_id; in mdp_comp_config()
1108 parent = dev->of_node->parent; in mdp_comp_config()
1126 type = (enum mdp_comp_type)(uintptr_t)of_id->data; in mdp_comp_config()
1145 if (!is_dma_capable(comp->type)) in mdp_comp_config()
1147 pm_runtime_enable(comp->comp_dev); in mdp_comp_config()
1165 struct device *dev = &mdp->pdev->dev; in mdp_comp_ctx_config()
1172 return -EINVAL; in mdp_comp_ctx_config()
1175 if (CFG_CHECK(MT8183, p_id)) in mdp_comp_ctx_config()
1176 arg = CFG_COMP(MT8183, param, type); in mdp_comp_ctx_config()
1178 return -EINVAL; in mdp_comp_ctx_config()
1182 return -EINVAL; in mdp_comp_ctx_config()
1185 ctx->comp = mdp->comp[public_id]; in mdp_comp_ctx_config()
1186 if (!ctx->comp) { in mdp_comp_ctx_config()
1188 return -EINVAL; in mdp_comp_ctx_config()
1191 ctx->param = param; in mdp_comp_ctx_config()
1192 if (CFG_CHECK(MT8183, p_id)) in mdp_comp_ctx_config()
1193 arg = CFG_COMP(MT8183, param, input); in mdp_comp_ctx_config()
1195 return -EINVAL; in mdp_comp_ctx_config()
1196 ctx->input = &frame->inputs[arg]; in mdp_comp_ctx_config()
1197 if (CFG_CHECK(MT8183, p_id)) in mdp_comp_ctx_config()
1198 idx = CFG_COMP(MT8183, param, num_outputs); in mdp_comp_ctx_config()
1200 return -EINVAL; in mdp_comp_ctx_config()
1202 if (CFG_CHECK(MT8183, p_id)) in mdp_comp_ctx_config()
1203 arg = CFG_COMP(MT8183, param, outputs[i]); in mdp_comp_ctx_config()
1205 return -EINVAL; in mdp_comp_ctx_config()
1206 ctx->outputs[i] = &frame->outputs[arg]; in mdp_comp_ctx_config()