Lines Matching +full:0 +full:x001fffff
68 0x0, BIT(0)); in init_rdma()
72 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, BIT(0), BIT(0)); in init_rdma()
74 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_RESET, 0x0, BIT(0)); in init_rdma()
75 return 0; in init_rdma()
88 u32 reg = 0; in config_rdma_frame()
93 MDP_RDMA_RESV_DUMMY_0, 0x7, 0x7); in config_rdma_frame()
96 MDP_RDMA_RESV_DUMMY_0, 0x0, 0x7); in config_rdma_frame()
103 0x00030071); in config_rdma_frame()
109 0x03C8FE0F); in config_rdma_frame()
118 reg, 0xFFFFFFFF); in config_rdma_frame()
123 reg, 0xFFFFFFFF); in config_rdma_frame()
130 reg, 0x001FFFFF); in config_rdma_frame()
137 0x1110); in config_rdma_frame()
140 reg = CFG_COMP(MT8183, ctx->param, rdma.iova[0]); in config_rdma_frame()
142 0xFFFFFFFF); in config_rdma_frame()
146 0xFFFFFFFF); in config_rdma_frame()
150 0xFFFFFFFF); in config_rdma_frame()
153 reg = CFG_COMP(MT8183, ctx->param, rdma.iova_end[0]); in config_rdma_frame()
155 reg, 0xFFFFFFFF); in config_rdma_frame()
159 reg, 0xFFFFFFFF); in config_rdma_frame()
163 reg, 0xFFFFFFFF); in config_rdma_frame()
168 reg, 0x001FFFFF); in config_rdma_frame()
172 reg, 0x001FFFFF); in config_rdma_frame()
177 reg, 0x0F110000); in config_rdma_frame()
179 return 0; in config_rdma_frame()
191 u32 csf_l = 0, csf_r = 0; in config_rdma_subfrm()
192 u32 reg = 0; in config_rdma_subfrm()
195 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, BIT(0), BIT(0)); in config_rdma_subfrm()
199 reg = CFG_COMP(MT8183, ctx->param, rdma.subfrms[index].offset[0]); in config_rdma_subfrm()
201 reg, 0xFFFFFFFF); in config_rdma_subfrm()
210 reg, 0xFFFFFFFF); in config_rdma_subfrm()
218 reg, 0xFFFFFFFF); in config_rdma_subfrm()
223 reg, 0xFFFFFFFF); in config_rdma_subfrm()
228 0x1FFF1FFF); in config_rdma_subfrm()
233 reg, 0x1FFF1FFF); in config_rdma_subfrm()
238 reg, 0x003F001F); in config_rdma_subfrm()
249 return 0; in config_rdma_subfrm()
258 if (ctx->comp->alias_id == 0) in wait_rdma_event()
264 MM_REG_WRITE(cmd, subsys_id, base, MDP_RDMA_EN, 0x0, BIT(0)); in wait_rdma_event()
265 return 0; in wait_rdma_event()
282 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x10000, BIT(16)); in init_rsz()
283 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(16)); in init_rsz()
285 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, BIT(0), BIT(0)); in init_rsz()
286 return 0; in init_rsz()
296 u32 reg = 0; in config_rsz_frame()
303 MM_REG_WRITE(cmd, subsys_id, base, PRZ_ENABLE, 0x0, BIT(0)); in config_rsz_frame()
304 return 0; in config_rsz_frame()
310 0x03FFFDF3); in config_rsz_frame()
314 0x0FFFC290); in config_rsz_frame()
318 reg, 0x007FFFFF); in config_rsz_frame()
322 reg, 0x007FFFFF); in config_rsz_frame()
323 return 0; in config_rsz_frame()
332 u32 csf_l = 0, csf_r = 0; in config_rsz_subfrm()
333 u32 reg = 0; in config_rsz_subfrm()
338 0x00003800); in config_rsz_subfrm()
342 0xFFFFFFFF); in config_rsz_subfrm()
356 reg, 0xFFFF); in config_rsz_subfrm()
361 reg, 0x1FFFFF); in config_rsz_subfrm()
365 reg, 0xFFFF); in config_rsz_subfrm()
369 reg, 0x1FFFFF); in config_rsz_subfrm()
374 reg, 0xFFFF); in config_rsz_subfrm()
379 reg, 0x1FFFFF); in config_rsz_subfrm()
384 0xFFFFFFFF); in config_rsz_subfrm()
386 return 0; in config_rsz_subfrm()
397 u32 csf_l = 0, csf_r = 0; in advance_rsz_subfrm()
405 MM_REG_WRITE(cmd, subsys_id, base, PRZ_CONTROL_1, 0x0, in advance_rsz_subfrm()
409 return 0; in advance_rsz_subfrm()
426 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, BIT(0), BIT(0)); in init_wrot()
427 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, BIT(0), BIT(0)); in init_wrot()
428 MM_REG_WRITE(cmd, subsys_id, base, VIDO_SOFT_RST, 0x0, BIT(0)); in init_wrot()
429 MM_REG_POLL(cmd, subsys_id, base, VIDO_SOFT_RST_STAT, 0x0, BIT(0)); in init_wrot()
430 return 0; in init_wrot()
440 u32 reg = 0; in config_wrot_frame()
444 reg = CFG_COMP(MT8183, ctx->param, wrot.iova[0]); in config_wrot_frame()
446 0xFFFFFFFF); in config_wrot_frame()
450 0xFFFFFFFF); in config_wrot_frame()
454 0xFFFFFFFF); in config_wrot_frame()
459 0xF131510F); in config_wrot_frame()
462 reg = CFG_COMP(MT8183, ctx->param, wrot.stride[0]); in config_wrot_frame()
464 0x0000FFFF); in config_wrot_frame()
469 0xFFFF); in config_wrot_frame()
473 0xFFFF); in config_wrot_frame()
477 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAT_CTRL, reg, 0xF3); in config_wrot_frame()
479 /* Set the fixed ALPHA as 0xFF */ in config_wrot_frame()
480 MM_REG_WRITE(cmd, subsys_id, base, VIDO_DITHER, 0xFF000000, in config_wrot_frame()
481 0xFF000000); in config_wrot_frame()
487 if (reg != 0) in config_wrot_frame()
489 reg, 0xFFF); in config_wrot_frame()
495 reg, 0x77); in config_wrot_frame()
498 return 0; in config_wrot_frame()
506 u32 reg = 0; in config_wrot_subfrm()
510 reg = CFG_COMP(MT8183, ctx->param, wrot.subfrms[index].offset[0]); in config_wrot_subfrm()
512 reg, 0x0FFFFFFF); in config_wrot_subfrm()
517 reg, 0x0FFFFFFF); in config_wrot_subfrm()
522 reg, 0x0FFFFFFF); in config_wrot_subfrm()
527 0x1FFF1FFF); in config_wrot_subfrm()
532 0x1FFF1FFF); in config_wrot_subfrm()
536 0x1FFF1FFF); in config_wrot_subfrm()
541 reg, 0x1FFF7F00); in config_wrot_subfrm()
544 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, BIT(0), BIT(0)); in config_wrot_subfrm()
546 return 0; in config_wrot_subfrm()
556 if (ctx->comp->alias_id == 0) in wait_wrot_event()
562 MM_REG_WRITE(cmd, subsys_id, base, VIDO_MAIN_BUF_SIZE, 0x0, in wait_wrot_event()
563 0x77); in wait_wrot_event()
566 MM_REG_WRITE(cmd, subsys_id, base, VIDO_ROT_EN, 0x0, BIT(0)); in wait_wrot_event()
568 return 0; in wait_wrot_event()
585 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, BIT(0), BIT(0)); in init_wdma()
586 MM_REG_POLL(cmd, subsys_id, base, WDMA_FLOW_CTRL_DBG, BIT(0), BIT(0)); in init_wdma()
587 MM_REG_WRITE(cmd, subsys_id, base, WDMA_RST, 0x0, BIT(0)); in init_wdma()
588 return 0; in init_wdma()
597 u32 reg = 0; in config_wdma_frame()
599 MM_REG_WRITE(cmd, subsys_id, base, WDMA_BUF_CON2, 0x10101050, in config_wdma_frame()
600 0xFFFFFFFF); in config_wdma_frame()
606 0x0F01B8F0); in config_wdma_frame()
609 reg = CFG_COMP(MT8183, ctx->param, wdma.iova[0]); in config_wdma_frame()
611 0xFFFFFFFF); in config_wdma_frame()
615 0xFFFFFFFF); in config_wdma_frame()
619 0xFFFFFFFF); in config_wdma_frame()
624 reg, 0x0000FFFF); in config_wdma_frame()
629 reg, 0x0000FFFF); in config_wdma_frame()
630 /* Set the fixed ALPHA as 0xFF */ in config_wdma_frame()
631 MM_REG_WRITE(cmd, subsys_id, base, WDMA_ALPHA, 0x800000FF, in config_wdma_frame()
632 0x800000FF); in config_wdma_frame()
634 return 0; in config_wdma_frame()
642 u32 reg = 0; in config_wdma_subfrm()
646 reg = CFG_COMP(MT8183, ctx->param, wdma.subfrms[index].offset[0]); in config_wdma_subfrm()
648 reg, 0x0FFFFFFF); in config_wdma_subfrm()
653 reg, 0x0FFFFFFF); in config_wdma_subfrm()
658 reg, 0x0FFFFFFF); in config_wdma_subfrm()
663 0x3FFF3FFF); in config_wdma_subfrm()
668 0x3FFF3FFF); in config_wdma_subfrm()
673 0x3FFF3FFF); in config_wdma_subfrm()
676 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, BIT(0), BIT(0)); in config_wdma_subfrm()
678 return 0; in config_wdma_subfrm()
688 MM_REG_WRITE(cmd, subsys_id, base, WDMA_EN, 0x0, BIT(0)); in wait_wdma_event()
689 return 0; in wait_wdma_event()
706 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_EN, BIT(0), BIT(0)); in init_ccorr()
708 MM_REG_WRITE(cmd, subsys_id, base, MDP_CCORR_CFG, BIT(0), BIT(0)); in init_ccorr()
709 return 0; in init_ccorr()
717 u32 csf_l = 0, csf_r = 0; in config_ccorr_subfrm()
718 u32 csf_t = 0, csf_b = 0; in config_ccorr_subfrm()
731 (hsize << 16) + (vsize << 0), 0x1FFF1FFF); in config_ccorr_subfrm()
732 return 0; in config_ccorr_subfrm()
789 for (i = 0; i < mdp->mdp_data->comp_data_len; i++) in mdp_comp_get_id()
803 if (ret < 0) { in mdp_comp_clock_on()
811 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_on()
823 return 0; in mdp_comp_clock_on()
826 while (--i >= 0) { in mdp_comp_clock_on()
841 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_clock_off()
855 for (i = 0; i < num; i++) { in mdp_comp_clocks_on()
861 return 0; in mdp_comp_clocks_on()
868 for (i = 0; i < num; i++) in mdp_comp_clocks_off()
877 int ret = 0; in mdp_get_subsys_id()
878 int index = 0; in mdp_get_subsys_id()
893 if (ret != 0) { in mdp_get_subsys_id()
903 return 0; in mdp_get_subsys_id()
914 if (of_address_to_resource(node, index, &res) < 0) in __mdp_comp_init()
915 base = 0L; in __mdp_comp_init()
920 comp->regs = of_iomap(node, 0); in __mdp_comp_init()
933 if (id < 0 || id >= MDP_MAX_COMP_COUNT) { in mdp_comp_init()
961 for (i = 0; i < comp->clk_num; i++) { in mdp_comp_init()
990 return 0; in mdp_comp_init()
1040 int ret = 0; in mdp_comp_sub_create()
1062 if (id < 0) { in mdp_comp_sub_create()
1088 for (i = 0; i < ARRAY_SIZE(mdp->comp); i++) { in mdp_comp_destroy()
1105 memset(mdp_comp_alias_id, 0, sizeof(mdp_comp_alias_id)); in mdp_comp_config()
1129 if (id < 0) { in mdp_comp_config()
1154 return 0; in mdp_comp_config()
1180 if (public_id < 0) { in mdp_comp_ctx_config()
1201 for (i = 0; i < idx; i++) { in mdp_comp_ctx_config()
1208 return 0; in mdp_comp_ctx_config()