chips-media/wave5/wave5-vpuapi.h

1 /* SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause) */
3  * Wave5 series multi-standard codec IP - helper definitions
5  * Copyright (C) 2021-2023 CHIPS&MEDIA INC
13 #include <media/v4l2-device.h>
14 #include <media/v4l2-mem2mem.h>
15 #include <media/v4l2-ctrls.h>
16 #include "wave5-vpuerror.h"
17 #include "wave5-vpuconfig.h"
18 #include "wave5-vdi.h"
39 	VPU_INST_STATE_STOP = 4
48 #define WAVE5_DEC_AVC_BUF_SIZE(_w, _h) ((((ALIGN(_w, 256) / 16) * (ALIGN(_h, 16) / 16)) + 16) * 80)
50 #define WAVE5_FBC_LUMA_TABLE_SIZE(_w, _h) (ALIGN(_h, 64) * ALIGN(_w, 256) / 32)
51 #define WAVE5_FBC_CHROMA_TABLE_SIZE(_w, _h) (ALIGN((_h), 64) * ALIGN((_w) / 2, 256) / 32)
52 #define WAVE5_ENC_AVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) * ALIGN(_h, 64) / 32)
53 #define WAVE5_ENC_HEVC_BUF_SIZE(_w, _h) (ALIGN(_w, 64) / 64 * ALIGN(_h, 64) / 64 * 128)
93 #define H264_PROFILE_HP 4
135 #define REFRESH_MODE_CTUS			4
192 #define DISPLAY_IDX_FLAG_SEQ_END -1
193 #define DISPLAY_IDX_FLAG_NO_FB -3
194 #define DECODED_IDX_FLAG_NO_FB -1
195 #define DECODED_IDX_FLAG_SKIP -2
197 #define RECON_IDX_FLAG_ENC_END -1
198 #define RECON_IDX_FLAG_ENC_DELAY -2
199 #define RECON_IDX_FLAG_HEADER_ONLY -3
200 #define RECON_IDX_FLAG_CHANGE_PARAM -4
221 	FORMAT_ERR = -1,
235 	/* 4:2:2 packed format */
283 	INT_WAVE5_FLUSH_INSTANCE = 4,
351 	unsigned int left; /* horizontal pixel offset from left edge */
352 	unsigned int top; /* vertical pixel offset from top edge */
353 	unsigned int right; /* horizontal pixel offset from right edge */
354 	unsigned int bottom; /* vertical pixel offset from bottom edge */
373 	u32 luma_bitdepth; /* bit-depth of the luma sample */
374 	u32 chroma_bitdepth; /* bit-depth of the chroma sample */
390 	 * reordering in AVC or B-frames in VC1), this index might be different to
394 	 * -3(0xFFFD) or -2(0xFFFE) : when a display output cannot be given due to picture
396 	 * -1(0xFFFF) : when there is no more output for display at the end of sequence
405 	 * -2 : indicates that no decoded output is generated because decoder meets EOS
407 	 * -1 : indicates that the decoder fails to decode a picture because there is no available
484 	u32 internal_bit_depth: 4; /* 8/10 */
485 	u32 gop_preset_idx: 4; /* 0 - 9 */
486 	u32 decoding_refresh_type: 2; /* 0=non-IRAP, 1=CRA, 2=IDR */
498 	 * - intra_ctu_refresh_mode (1) -> number of consecutive CTU rows
499 	 * - intra_ctu_refresh_mode (2) -> the number of consecutive CTU columns
500 	 * - intra_ctu_refresh_mode (3) -> step size in CTU
501 	 * - intra_ctu_refresh_mode (4) -> number of intra ct_us to be encoded in a picture
512 	u32 independ_slice_mode : 1; /* 0=no-multi-slice, 1=slice-in-ctu-number*/
515 	s32 beta_offset_div2: 4; /* sets beta_offset_div2 for deblocking filter */
516 	s32 tc_offset_div2: 4; /* sets tc_offset_div3 for deblocking filter */
517 	u32 hvs_qp_scale: 4; /* QP scaling factor for CU QP adjust if hvs_qp_scale_enable is 1 */
534 	u32 avc_idr_period; /* period of IDR picture (0 ~ 1024). 0 - implies an infinite period */
536 	u32 intra_mb_refresh_mode: 2; /* 0=none, 1=row, 2=column, 3=step-size-in-mb */
540 	 * intra_mb_refresh_mode (1) -> number of consecutive MB rows
541 	 * intra_mb_refresh_mode (2) ->the number of consecutive MB columns
542 	 * intra_mb_refresh_mode (3) -> step size in MB
551 	u32 avc_slice_mode: 1; /* 0=none, 1=slice-in-mb-number */
557 	u32 disable_deblk: 1; /* disable in-loop deblocking filtering */
568 	u32 mb_level_rc_enable: 1; /* enable MB-level rate control */
648 	PRESET_IDX_IBPBP = 4, /* gopsize = 2 */
649 	PRESET_IDX_IBBBP = 5, /* gopsize = 4 */
650 	PRESET_IDX_IPPPP = 6, /* consecutive P, cyclic gopsize = 4 */
651 	PRESET_IDX_IBBBB = 7, /* consecutive B, cyclic gopsize = 4 */
724 	struct vpu_buf vb_sub_sam_buf; /* sub-sampled buffer for ME */