Lines Matching +full:msb +full:- +full:justified
1 // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
3 * Wave5 series multi-standard codec IP - wave5 backend logic
5 * Copyright (C) 2021-2023 CHIPS&MEDIA INC
10 #include "wave5-vpu.h"
12 #include "wave5-regdefine.h"
85 struct device *dev = vpu_dev->dev; in _wave5_print_reg_err()
133 return -ETIMEDOUT; in wave5_wait_fio_readl()
150 dev_dbg_ratelimited(vpu_dev->dev, "FIO write timeout: addr=0x%x data=%x\n", in wave5_fio_writel()
158 if (vpu_dev->product_code == WAVE521C_CODE || in wave5_wait_bus_busy()
159 vpu_dev->product_code == WAVE521_CODE || in wave5_wait_bus_busy()
160 vpu_dev->product_code == WAVE521E1_CODE) in wave5_wait_bus_busy()
197 dev_err(vpu_dev->dev, "Unsupported product id (%x)\n", val); in wave5_vpu_get_product_id()
200 dev_err(vpu_dev->dev, "Invalid product id (%x)\n", val); in wave5_vpu_get_product_id()
213 instance_index = inst->id; in wave5_bit_issue_command()
214 codec_mode = inst->std; in wave5_bit_issue_command()
224 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x (%s)\n", __func__, cmd, in wave5_bit_issue_command()
225 cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); in wave5_bit_issue_command()
227 dev_dbg(vpu_dev->dev, "%s: cmd=0x%x\n", __func__, cmd); in wave5_bit_issue_command()
244 * If the fail_res argument is NULL, then just return -EIO. in wave5_vpu_firmware_command_queue_error_check()
251 return -EIO; in wave5_vpu_firmware_command_queue_error_check()
254 return -EBUSY; in wave5_vpu_firmware_command_queue_error_check()
264 wave5_bit_issue_command(inst->dev, inst, cmd); in send_firmware_command()
265 ret = wave5_wait_vpu_busy(inst->dev, W5_VPU_BUSY_STATUS); in send_firmware_command()
267 dev_warn(inst->dev->dev, "%s: command: '%s', timed out\n", __func__, in send_firmware_command()
268 cmd_to_str(cmd, inst->type == VPU_INST_TYPE_DEC)); in send_firmware_command()
269 return -ETIMEDOUT; in send_firmware_command()
273 *queue_status = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in send_firmware_command()
281 return wave5_vpu_firmware_command_queue_error_check(inst->dev, fail_result); in send_firmware_command()
295 dev_warn(vpu_dev->dev, "command: 'W5_QUERY', timed out opt=0x%x\n", query_opt); in wave5_send_query()
305 struct vpu_attr *p_attr = &vpu_dev->attr; in setup_wave5_properties()
317 p_attr->product_name[0] = str[3]; in setup_wave5_properties()
318 p_attr->product_name[1] = str[2]; in setup_wave5_properties()
319 p_attr->product_name[2] = str[1]; in setup_wave5_properties()
320 p_attr->product_name[3] = str[0]; in setup_wave5_properties()
321 p_attr->product_name[4] = 0; in setup_wave5_properties()
323 p_attr->product_id = wave5_vpu_get_product_id(vpu_dev); in setup_wave5_properties()
324 p_attr->product_version = vpu_read_reg(vpu_dev, W5_RET_PRODUCT_VERSION); in setup_wave5_properties()
325 p_attr->fw_version = vpu_read_reg(vpu_dev, W5_RET_FW_VERSION); in setup_wave5_properties()
326 p_attr->customer_id = vpu_read_reg(vpu_dev, W5_RET_CUSTOMER_ID); in setup_wave5_properties()
331 p_attr->support_hevc10bit_enc = FIELD_GET(FEATURE_HEVC10BIT_ENC, hw_config_feature); in setup_wave5_properties()
332 p_attr->support_avc10bit_enc = FIELD_GET(FEATURE_AVC10BIT_ENC, hw_config_feature); in setup_wave5_properties()
334 p_attr->support_decoders = FIELD_GET(FEATURE_AVC_DECODER, hw_config_def1) << STD_AVC; in setup_wave5_properties()
335 p_attr->support_decoders |= FIELD_GET(FEATURE_HEVC_DECODER, hw_config_def1) << STD_HEVC; in setup_wave5_properties()
336 p_attr->support_encoders = FIELD_GET(FEATURE_AVC_ENCODER, hw_config_def1) << STD_AVC; in setup_wave5_properties()
337 p_attr->support_encoders |= FIELD_GET(FEATURE_HEVC_ENCODER, hw_config_def1) << STD_HEVC; in setup_wave5_properties()
339 p_attr->support_backbone = FIELD_GET(FEATURE_BACKBONE, hw_config_def0); in setup_wave5_properties()
340 p_attr->support_vcpu_backbone = FIELD_GET(FEATURE_VCPU_BACKBONE, hw_config_def0); in setup_wave5_properties()
341 p_attr->support_vcore_backbone = FIELD_GET(FEATURE_VCORE_BACKBONE, hw_config_def0); in setup_wave5_properties()
361 return -EINVAL; in wave5_vpu_get_version()
380 common_vb = &vpu_dev->common_mem; in wave5_vpu_init()
382 code_base = common_vb->daddr; in wave5_vpu_init()
386 return -EINVAL; in wave5_vpu_init()
388 temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; in wave5_vpu_init()
393 dev_err(vpu_dev->dev, "VPU init, Writing firmware to common buffer, fail: %d\n", in wave5_vpu_init()
448 dev_err(vpu_dev->dev, "VPU init(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_init()
463 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_build_up_dec_param()
464 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_build_up_dec_param()
466 p_dec_info->cycle_per_tick = 256; in wave5_vpu_build_up_dec_param()
467 if (vpu_dev->sram_buf.size) { in wave5_vpu_build_up_dec_param()
468 p_dec_info->sec_axi_info.use_bit_enable = 1; in wave5_vpu_build_up_dec_param()
469 p_dec_info->sec_axi_info.use_ip_enable = 1; in wave5_vpu_build_up_dec_param()
470 p_dec_info->sec_axi_info.use_lf_row_enable = 1; in wave5_vpu_build_up_dec_param()
472 switch (inst->std) { in wave5_vpu_build_up_dec_param()
474 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_HEVC; in wave5_vpu_build_up_dec_param()
477 p_dec_info->seq_change_mask = SEQ_CHANGE_ENABLE_ALL_AVC; in wave5_vpu_build_up_dec_param()
480 return -EINVAL; in wave5_vpu_build_up_dec_param()
483 p_dec_info->vb_work.size = WAVE521DEC_WORKBUF_SIZE; in wave5_vpu_build_up_dec_param()
484 ret = wave5_vdi_allocate_dma_memory(inst->dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
488 vpu_write_reg(inst->dev, W5_CMD_DEC_VCORE_INFO, 1); in wave5_vpu_build_up_dec_param()
490 wave5_vdi_clear_memory(inst->dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
492 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_dec_info->vb_work.daddr); in wave5_vpu_build_up_dec_param()
493 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_dec_info->vb_work.size); in wave5_vpu_build_up_dec_param()
495 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_build_up_dec_param()
496 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_build_up_dec_param()
498 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_START_ADDR, p_dec_info->stream_buf_start_addr); in wave5_vpu_build_up_dec_param()
499 vpu_write_reg(inst->dev, W5_CMD_DEC_BS_SIZE, p_dec_info->stream_buf_size); in wave5_vpu_build_up_dec_param()
501 /* NOTE: SDMA reads MSB first */ in wave5_vpu_build_up_dec_param()
502 vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, BITSTREAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_build_up_dec_param()
504 vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); in wave5_vpu_build_up_dec_param()
505 vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); in wave5_vpu_build_up_dec_param()
509 wave5_vdi_free_dma_memory(vpu_dev, &p_dec_info->vb_work); in wave5_vpu_build_up_dec_param()
513 p_dec_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_dec_param()
520 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_hw_flush_instance()
533 dev_warn(inst->dev->dev, in wave5_vpu_hw_flush_instance()
538 p_dec_info->instance_queue_count = 0; in wave5_vpu_hw_flush_instance()
539 p_dec_info->report_queue_count = 0; in wave5_vpu_hw_flush_instance()
548 if (info->stream_endflag) in get_bitstream_options()
555 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_init_seq()
560 if (!inst->codec_info) in wave5_vpu_dec_init_seq()
561 return -EINVAL; in wave5_vpu_dec_init_seq()
563 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); in wave5_vpu_dec_init_seq()
564 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_dec_init_seq()
566 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_dec_init_seq()
568 vpu_write_reg(inst->dev, W5_COMMAND_OPTION, cmd_option); in wave5_vpu_dec_init_seq()
569 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); in wave5_vpu_dec_init_seq()
575 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_init_seq()
576 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_init_seq()
578 dev_dbg(inst->dev->dev, "%s: init seq sent (queue %u : %u)\n", __func__, in wave5_vpu_dec_init_seq()
579 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_init_seq()
588 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_get_dec_seq_result()
590 p_dec_info->stream_rd_ptr = wave5_dec_get_rd_ptr(inst); in wave5_get_dec_seq_result()
591 info->rd_ptr = p_dec_info->stream_rd_ptr; in wave5_get_dec_seq_result()
593 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_get_dec_seq_result()
595 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); in wave5_get_dec_seq_result()
596 info->pic_width = ((reg_val >> 16) & 0xffff); in wave5_get_dec_seq_result()
597 info->pic_height = (reg_val & 0xffff); in wave5_get_dec_seq_result()
598 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_DEC_NUM_REQUIRED_FB); in wave5_get_dec_seq_result()
600 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_LEFT_RIGHT); in wave5_get_dec_seq_result()
601 info->pic_crop_rect.left = (reg_val >> 16) & 0xffff; in wave5_get_dec_seq_result()
602 info->pic_crop_rect.right = reg_val & 0xffff; in wave5_get_dec_seq_result()
603 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_CROP_TOP_BOTTOM); in wave5_get_dec_seq_result()
604 info->pic_crop_rect.top = (reg_val >> 16) & 0xffff; in wave5_get_dec_seq_result()
605 info->pic_crop_rect.bottom = reg_val & 0xffff; in wave5_get_dec_seq_result()
607 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_COLOR_SAMPLE_INFO); in wave5_get_dec_seq_result()
608 info->luma_bitdepth = reg_val & 0xf; in wave5_get_dec_seq_result()
609 info->chroma_bitdepth = (reg_val >> 4) & 0xf; in wave5_get_dec_seq_result()
611 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_SEQ_PARAM); in wave5_get_dec_seq_result()
613 info->profile = (reg_val >> 24) & 0x1f; in wave5_get_dec_seq_result()
615 if (inst->std == W_HEVC_DEC) { in wave5_get_dec_seq_result()
617 if (!info->profile) { in wave5_get_dec_seq_result()
619 info->profile = HEVC_PROFILE_MAIN; /* main profile */ in wave5_get_dec_seq_result()
621 info->profile = HEVC_PROFILE_MAIN10; /* main10 profile */ in wave5_get_dec_seq_result()
624 info->profile = HEVC_PROFILE_STILLPICTURE; in wave5_get_dec_seq_result()
626 info->profile = HEVC_PROFILE_MAIN; /* for old version HM */ in wave5_get_dec_seq_result()
628 } else if (inst->std == W_AVC_DEC) { in wave5_get_dec_seq_result()
629 info->profile = FIELD_GET(SEQ_PARAM_PROFILE_MASK, reg_val); in wave5_get_dec_seq_result()
632 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); in wave5_get_dec_seq_result()
633 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); in wave5_get_dec_seq_result()
634 p_dec_info->vlc_buf_size = info->vlc_buf_size; in wave5_get_dec_seq_result()
635 p_dec_info->param_buf_size = info->param_buf_size; in wave5_get_dec_seq_result()
642 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_get_seq_info()
644 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); in wave5_vpu_dec_get_seq_info()
645 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); in wave5_vpu_dec_get_seq_info()
646 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_dec_get_seq_info()
649 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_dec_get_seq_info()
653 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_dec_get_seq_info()
655 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_get_seq_info()
656 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_get_seq_info()
658 dev_dbg(inst->dev->dev, "%s: init seq complete (queue %u : %u)\n", __func__, in wave5_vpu_dec_get_seq_info()
659 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_get_seq_info()
661 /* this is not a fatal error, set ret to -EIO but don't return immediately */ in wave5_vpu_dec_get_seq_info()
662 if (vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_SUCCESS) != 1) { in wave5_vpu_dec_get_seq_info()
663 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_DEC_ERR_INFO); in wave5_vpu_dec_get_seq_info()
664 ret = -EIO; in wave5_vpu_dec_get_seq_info()
676 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_register_framebuffer()
677 struct dec_initial_info *init_info = &p_dec_info->initial_info; in wave5_vpu_dec_register_framebuffer()
684 bool justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_dec_register_framebuffer() local
690 cbcr_interleave = inst->cbcr_interleave; in wave5_vpu_dec_register_framebuffer()
691 nv21 = inst->nv21; in wave5_vpu_dec_register_framebuffer()
700 switch (inst->std) { in wave5_vpu_dec_register_framebuffer()
702 mv_col_size = WAVE5_DEC_HEVC_BUF_SIZE(init_info->pic_width, in wave5_vpu_dec_register_framebuffer()
703 init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
706 mv_col_size = WAVE5_DEC_AVC_BUF_SIZE(init_info->pic_width, in wave5_vpu_dec_register_framebuffer()
707 init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
710 return -EINVAL; in wave5_vpu_dec_register_framebuffer()
713 if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { in wave5_vpu_dec_register_framebuffer()
715 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_mv, count, size); in wave5_vpu_dec_register_framebuffer()
720 frame_width = init_info->pic_width; in wave5_vpu_dec_register_framebuffer()
721 frame_height = init_info->pic_height; in wave5_vpu_dec_register_framebuffer()
726 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_y_tbl, count, size); in wave5_vpu_dec_register_framebuffer()
731 ret = wave5_vdi_allocate_array(inst->dev, p_dec_info->vb_fbc_c_tbl, count, size); in wave5_vpu_dec_register_framebuffer()
735 pic_size = (init_info->pic_width << 16) | (init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
737 vb_buf.size = (p_dec_info->vlc_buf_size * VLC_BUF_NUM) + in wave5_vpu_dec_register_framebuffer()
738 (p_dec_info->param_buf_size * COMMAND_QUEUE_DEPTH); in wave5_vpu_dec_register_framebuffer()
741 if (vb_buf.size != p_dec_info->vb_task.size) { in wave5_vpu_dec_register_framebuffer()
742 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); in wave5_vpu_dec_register_framebuffer()
743 ret = wave5_vdi_allocate_dma_memory(inst->dev, &vb_buf); in wave5_vpu_dec_register_framebuffer()
747 p_dec_info->vb_task = vb_buf; in wave5_vpu_dec_register_framebuffer()
750 vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, in wave5_vpu_dec_register_framebuffer()
751 p_dec_info->vb_task.daddr); in wave5_vpu_dec_register_framebuffer()
752 vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_buf.size); in wave5_vpu_dec_register_framebuffer()
754 pic_size = (init_info->pic_width << 16) | (init_info->pic_height); in wave5_vpu_dec_register_framebuffer()
756 if (inst->output_format == FORMAT_422) in wave5_vpu_dec_register_framebuffer()
759 vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); in wave5_vpu_dec_register_framebuffer()
763 (justified << 22) | in wave5_vpu_dec_register_framebuffer()
769 vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, reg_val); in wave5_vpu_dec_register_framebuffer()
775 reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); in wave5_vpu_dec_register_framebuffer()
776 vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); in wave5_vpu_dec_register_framebuffer()
778 end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; in wave5_vpu_dec_register_framebuffer()
780 vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); in wave5_vpu_dec_register_framebuffer()
786 vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), addr_y); in wave5_vpu_dec_register_framebuffer()
787 vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), addr_cb); in wave5_vpu_dec_register_framebuffer()
790 vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), in wave5_vpu_dec_register_framebuffer()
791 p_dec_info->vb_fbc_y_tbl[idx].daddr); in wave5_vpu_dec_register_framebuffer()
793 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), in wave5_vpu_dec_register_framebuffer()
794 p_dec_info->vb_fbc_c_tbl[idx].daddr); in wave5_vpu_dec_register_framebuffer()
795 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), in wave5_vpu_dec_register_framebuffer()
796 p_dec_info->vb_mv[idx].daddr); in wave5_vpu_dec_register_framebuffer()
798 vpu_write_reg(inst->dev, W5_ADDR_CR_BASE0 + (i << 4), addr_cr); in wave5_vpu_dec_register_framebuffer()
799 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), 0); in wave5_vpu_dec_register_framebuffer()
800 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), 0); in wave5_vpu_dec_register_framebuffer()
804 remain -= i; in wave5_vpu_dec_register_framebuffer()
811 reg_val = vpu_read_reg(inst->dev, W5_RET_SUCCESS); in wave5_vpu_dec_register_framebuffer()
813 ret = -EIO; in wave5_vpu_dec_register_framebuffer()
820 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_task); in wave5_vpu_dec_register_framebuffer()
823 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_c_tbl[i]); in wave5_vpu_dec_register_framebuffer()
826 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_fbc_y_tbl[i]); in wave5_vpu_dec_register_framebuffer()
829 wave5_vdi_free_dma_memory(inst->dev, &p_dec_info->vb_mv[i]); in wave5_vpu_dec_register_framebuffer()
836 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_decode()
839 vpu_write_reg(inst->dev, W5_BS_RD_PTR, p_dec_info->stream_rd_ptr); in wave5_vpu_decode()
840 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_decode()
842 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_decode()
845 reg_val = p_dec_info->sec_axi_info.use_bit_enable | in wave5_vpu_decode()
846 (p_dec_info->sec_axi_info.use_ip_enable << 9) | in wave5_vpu_decode()
847 (p_dec_info->sec_axi_info.use_lf_row_enable << 15); in wave5_vpu_decode()
848 vpu_write_reg(inst->dev, W5_USE_SEC_AXI, reg_val); in wave5_vpu_decode()
851 vpu_write_reg(inst->dev, W5_CMD_DEC_USER_MASK, p_dec_info->user_data_enable); in wave5_vpu_decode()
853 vpu_write_reg(inst->dev, W5_COMMAND_OPTION, DEC_PIC_NORMAL); in wave5_vpu_decode()
854 vpu_write_reg(inst->dev, W5_CMD_DEC_TEMPORAL_ID_PLUS1, in wave5_vpu_decode()
855 (p_dec_info->target_spatial_id << 9) | in wave5_vpu_decode()
856 (p_dec_info->temp_id_select_mode << 8) | p_dec_info->target_temp_id); in wave5_vpu_decode()
857 vpu_write_reg(inst->dev, W5_CMD_SEQ_CHANGE_ENABLE_FLAG, p_dec_info->seq_change_mask); in wave5_vpu_decode()
859 vpu_write_reg(inst->dev, W5_CMD_DEC_FORCE_FB_LATENCY_PLUS1, !p_dec_info->reorder_enable); in wave5_vpu_decode()
862 if (ret == -ETIMEDOUT) in wave5_vpu_decode()
865 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_decode()
866 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_decode()
868 dev_dbg(inst->dev->dev, "%s: dec pic sent (queue %u : %u)\n", __func__, in wave5_vpu_decode()
869 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_decode()
881 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_get_result()
882 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_dec_get_result()
884 vpu_write_reg(inst->dev, W5_CMD_DEC_ADDR_REPORT_BASE, p_dec_info->user_data_buf_addr); in wave5_vpu_dec_get_result()
885 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_SIZE, p_dec_info->user_data_buf_size); in wave5_vpu_dec_get_result()
886 vpu_write_reg(inst->dev, W5_CMD_DEC_REPORT_PARAM, REPORT_PARAM_ENDIANNESS_BIG_ENDIAN); in wave5_vpu_dec_get_result()
893 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_dec_get_result()
895 p_dec_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_dec_get_result()
896 p_dec_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_dec_get_result()
898 dev_dbg(inst->dev->dev, "%s: dec pic complete (queue %u : %u)\n", __func__, in wave5_vpu_dec_get_result()
899 p_dec_info->instance_queue_count, p_dec_info->report_queue_count); in wave5_vpu_dec_get_result()
901 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_TYPE); in wave5_vpu_dec_get_result()
905 if (inst->std == W_HEVC_DEC) { in wave5_vpu_dec_get_result()
907 result->pic_type = PIC_TYPE_B; in wave5_vpu_dec_get_result()
909 result->pic_type = PIC_TYPE_P; in wave5_vpu_dec_get_result()
911 result->pic_type = PIC_TYPE_I; in wave5_vpu_dec_get_result()
913 result->pic_type = PIC_TYPE_MAX; in wave5_vpu_dec_get_result()
914 if ((nal_unit_type == 19 || nal_unit_type == 20) && result->pic_type == PIC_TYPE_I) in wave5_vpu_dec_get_result()
916 result->pic_type = PIC_TYPE_IDR; in wave5_vpu_dec_get_result()
917 } else if (inst->std == W_AVC_DEC) { in wave5_vpu_dec_get_result()
919 result->pic_type = PIC_TYPE_B; in wave5_vpu_dec_get_result()
921 result->pic_type = PIC_TYPE_P; in wave5_vpu_dec_get_result()
923 result->pic_type = PIC_TYPE_I; in wave5_vpu_dec_get_result()
925 result->pic_type = PIC_TYPE_MAX; in wave5_vpu_dec_get_result()
926 if (nal_unit_type == 5 && result->pic_type == PIC_TYPE_I) in wave5_vpu_dec_get_result()
927 result->pic_type = PIC_TYPE_IDR; in wave5_vpu_dec_get_result()
929 index = vpu_read_reg(inst->dev, W5_RET_DEC_DISPLAY_INDEX); in wave5_vpu_dec_get_result()
930 result->index_frame_display = index; in wave5_vpu_dec_get_result()
931 index = vpu_read_reg(inst->dev, W5_RET_DEC_DECODED_INDEX); in wave5_vpu_dec_get_result()
932 result->index_frame_decoded = index; in wave5_vpu_dec_get_result()
933 result->index_frame_decoded_for_tiled = index; in wave5_vpu_dec_get_result()
935 sub_layer_info = vpu_read_reg(inst->dev, W5_RET_DEC_SUB_LAYER_INFO); in wave5_vpu_dec_get_result()
936 result->temporal_id = sub_layer_info & 0x7; in wave5_vpu_dec_get_result()
938 if (inst->std == W_HEVC_DEC || inst->std == W_AVC_DEC) { in wave5_vpu_dec_get_result()
939 result->decoded_poc = -1; in wave5_vpu_dec_get_result()
940 if (result->index_frame_decoded >= 0 || in wave5_vpu_dec_get_result()
941 result->index_frame_decoded == DECODED_IDX_FLAG_SKIP) in wave5_vpu_dec_get_result()
942 result->decoded_poc = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_POC); in wave5_vpu_dec_get_result()
945 result->sequence_changed = vpu_read_reg(inst->dev, W5_RET_DEC_NOTIFICATION); in wave5_vpu_dec_get_result()
946 reg_val = vpu_read_reg(inst->dev, W5_RET_DEC_PIC_SIZE); in wave5_vpu_dec_get_result()
947 result->dec_pic_width = reg_val >> 16; in wave5_vpu_dec_get_result()
948 result->dec_pic_height = reg_val & 0xffff; in wave5_vpu_dec_get_result()
950 if (result->sequence_changed) { in wave5_vpu_dec_get_result()
951 memcpy((void *)&p_dec_info->new_seq_info, (void *)&p_dec_info->initial_info, in wave5_vpu_dec_get_result()
953 wave5_get_dec_seq_result(inst, &p_dec_info->new_seq_info); in wave5_vpu_dec_get_result()
956 result->dec_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_DEC_HOST_CMD_TICK); in wave5_vpu_dec_get_result()
957 result->dec_decode_end_tick = vpu_read_reg(inst->dev, W5_RET_DEC_DECODING_ENC_TICK); in wave5_vpu_dec_get_result()
959 if (!p_dec_info->first_cycle_check) { in wave5_vpu_dec_get_result()
960 result->frame_cycle = in wave5_vpu_dec_get_result()
961 (result->dec_decode_end_tick - result->dec_host_cmd_tick) * in wave5_vpu_dec_get_result()
962 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
963 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; in wave5_vpu_dec_get_result()
964 p_dec_info->first_cycle_check = true; in wave5_vpu_dec_get_result()
965 } else if (result->index_frame_decoded_for_tiled != -1) { in wave5_vpu_dec_get_result()
966 result->frame_cycle = in wave5_vpu_dec_get_result()
967 (result->dec_decode_end_tick - vpu_dev->last_performance_cycles) * in wave5_vpu_dec_get_result()
968 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
969 vpu_dev->last_performance_cycles = result->dec_decode_end_tick; in wave5_vpu_dec_get_result()
970 if (vpu_dev->last_performance_cycles < result->dec_host_cmd_tick) in wave5_vpu_dec_get_result()
971 result->frame_cycle = in wave5_vpu_dec_get_result()
972 (result->dec_decode_end_tick - result->dec_host_cmd_tick) * in wave5_vpu_dec_get_result()
973 p_dec_info->cycle_per_tick; in wave5_vpu_dec_get_result()
977 if (p_dec_info->instance_queue_count == 0 && p_dec_info->report_queue_count == 0) in wave5_vpu_dec_get_result()
978 p_dec_info->first_cycle_check = false; in wave5_vpu_dec_get_result()
992 common_vb = &vpu_dev->common_mem; in wave5_vpu_re_init()
994 code_base = common_vb->daddr; in wave5_vpu_re_init()
998 return -EINVAL; in wave5_vpu_re_init()
999 temp_base = common_vb->daddr + WAVE5_TEMPBUF_OFFSET; in wave5_vpu_re_init()
1009 dev_err(vpu_dev->dev, in wave5_vpu_re_init()
1018 dev_err(vpu_dev->dev, "VPU init, Resetting the VPU, fail: %d\n", ret); in wave5_vpu_re_init()
1066 dev_err(vpu_dev->dev, "VPU reinit(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_re_init()
1111 common_vb = &vpu_dev->common_mem; in wave5_vpu_sleep_wake()
1113 code_base = common_vb->daddr; in wave5_vpu_sleep_wake()
1118 return -EINVAL; in wave5_vpu_sleep_wake()
1167 dev_err(vpu_dev->dev, "VPU wakeup(W5_VPU_REMAP_CORE_START) timeout\n"); in wave5_vpu_sleep_wake()
1182 struct vpu_attr *p_attr = &vpu_dev->attr; in wave5_vpu_reset()
1194 p_attr->support_backbone = true; in wave5_vpu_reset()
1196 p_attr->support_vcore_backbone = true; in wave5_vpu_reset()
1198 p_attr->support_vcpu_backbone = true; in wave5_vpu_reset()
1201 if (p_attr->support_backbone) { in wave5_vpu_reset()
1204 if (p_attr->support_vcore_backbone) { in wave5_vpu_reset()
1205 if (p_attr->support_vcpu_backbone) { in wave5_vpu_reset()
1223 return -EBUSY; in wave5_vpu_reset()
1232 return -EBUSY; in wave5_vpu_reset()
1255 return -EINVAL; in wave5_vpu_reset()
1269 if (p_attr->support_backbone) { in wave5_vpu_reset()
1270 if (p_attr->support_vcore_backbone) { in wave5_vpu_reset()
1271 if (p_attr->support_vcpu_backbone) in wave5_vpu_reset()
1293 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_vpu_dec_set_bitstream_flag()
1295 p_dec_info->stream_endflag = eos ? 1 : 0; in wave5_vpu_dec_set_bitstream_flag()
1296 vpu_write_reg(inst->dev, W5_BS_OPTION, get_bitstream_options(p_dec_info)); in wave5_vpu_dec_set_bitstream_flag()
1297 vpu_write_reg(inst->dev, W5_BS_WR_PTR, p_dec_info->stream_wr_ptr); in wave5_vpu_dec_set_bitstream_flag()
1304 struct dec_info *p_dec_info = &inst->codec_info->dec_info; in wave5_dec_clr_disp_flag()
1307 vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, BIT(index)); in wave5_dec_clr_disp_flag()
1308 vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, 0); in wave5_dec_clr_disp_flag()
1310 ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); in wave5_dec_clr_disp_flag()
1314 p_dec_info->frame_display_flag = vpu_read_reg(inst->dev, W5_RET_DEC_DISP_IDC); in wave5_dec_clr_disp_flag()
1323 vpu_write_reg(inst->dev, W5_CMD_DEC_CLR_DISP_IDC, 0); in wave5_dec_set_disp_flag()
1324 vpu_write_reg(inst->dev, W5_CMD_DEC_SET_DISP_IDC, BIT(index)); in wave5_dec_set_disp_flag()
1326 ret = wave5_send_query(inst->dev, inst, UPDATE_DISP_FLAG); in wave5_dec_set_disp_flag()
1337 interrupt_reason = vpu_read_reg(inst->dev, W5_VPU_VINT_REASON_USR); in wave5_vpu_clear_interrupt()
1339 vpu_write_reg(inst->dev, W5_VPU_VINT_REASON_USR, interrupt_reason); in wave5_vpu_clear_interrupt()
1348 ret = wave5_send_query(inst->dev, inst, GET_BS_RD_PTR); in wave5_dec_get_rd_ptr()
1350 return inst->codec_info->dec_info.stream_rd_ptr; in wave5_dec_get_rd_ptr()
1352 return vpu_read_reg(inst->dev, W5_RET_QUERY_DEC_BS_RD_PTR); in wave5_dec_get_rd_ptr()
1359 vpu_write_reg(inst->dev, W5_RET_QUERY_DEC_SET_BS_RD_PTR, addr); in wave5_dec_set_rd_ptr()
1361 ret = wave5_send_query(inst->dev, inst, SET_BS_RD_PTR); in wave5_dec_set_rd_ptr()
1374 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_build_up_enc_param()
1380 p_enc_info->cycle_per_tick = 256; in wave5_vpu_build_up_enc_param()
1381 if (vpu_dev->sram_buf.size) { in wave5_vpu_build_up_enc_param()
1382 p_enc_info->sec_axi_info.use_enc_rdo_enable = 1; in wave5_vpu_build_up_enc_param()
1383 p_enc_info->sec_axi_info.use_enc_lf_enable = 1; in wave5_vpu_build_up_enc_param()
1386 p_enc_info->vb_work.size = WAVE521ENC_WORKBUF_SIZE; in wave5_vpu_build_up_enc_param()
1387 ret = wave5_vdi_allocate_dma_memory(vpu_dev, &p_enc_info->vb_work); in wave5_vpu_build_up_enc_param()
1389 memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); in wave5_vpu_build_up_enc_param()
1393 wave5_vdi_clear_memory(vpu_dev, &p_enc_info->vb_work); in wave5_vpu_build_up_enc_param()
1395 vpu_write_reg(inst->dev, W5_ADDR_WORK_BASE, p_enc_info->vb_work.daddr); in wave5_vpu_build_up_enc_param()
1396 vpu_write_reg(inst->dev, W5_WORK_SIZE, p_enc_info->vb_work.size); in wave5_vpu_build_up_enc_param()
1398 vpu_write_reg(inst->dev, W5_CMD_ADDR_SEC_AXI, vpu_dev->sram_buf.daddr); in wave5_vpu_build_up_enc_param()
1399 vpu_write_reg(inst->dev, W5_CMD_SEC_AXI_SIZE, vpu_dev->sram_buf.size); in wave5_vpu_build_up_enc_param()
1401 reg_val = (open_param->line_buf_int_en << 6) | BITSTREAM_ENDIANNESS_BIG_ENDIAN; in wave5_vpu_build_up_enc_param()
1402 vpu_write_reg(inst->dev, W5_CMD_BS_PARAM, reg_val); in wave5_vpu_build_up_enc_param()
1403 vpu_write_reg(inst->dev, W5_CMD_EXT_ADDR, 0); in wave5_vpu_build_up_enc_param()
1404 vpu_write_reg(inst->dev, W5_CMD_NUM_CQ_DEPTH_M1, (COMMAND_QUEUE_DEPTH - 1)); in wave5_vpu_build_up_enc_param()
1407 vpu_write_reg(inst->dev, W5_CMD_ENC_SRC_OPTIONS, 0); in wave5_vpu_build_up_enc_param()
1408 vpu_write_reg(inst->dev, W5_CMD_ENC_VCORE_INFO, 1); in wave5_vpu_build_up_enc_param()
1414 buffer_addr = open_param->bitstream_buffer; in wave5_vpu_build_up_enc_param()
1415 buffer_size = open_param->bitstream_buffer_size; in wave5_vpu_build_up_enc_param()
1416 p_enc_info->stream_rd_ptr = buffer_addr; in wave5_vpu_build_up_enc_param()
1417 p_enc_info->stream_wr_ptr = buffer_addr; in wave5_vpu_build_up_enc_param()
1418 p_enc_info->line_buf_int_en = open_param->line_buf_int_en; in wave5_vpu_build_up_enc_param()
1419 p_enc_info->stream_buf_start_addr = buffer_addr; in wave5_vpu_build_up_enc_param()
1420 p_enc_info->stream_buf_size = buffer_size; in wave5_vpu_build_up_enc_param()
1421 p_enc_info->stream_buf_end_addr = buffer_addr + buffer_size; in wave5_vpu_build_up_enc_param()
1422 p_enc_info->stride = 0; in wave5_vpu_build_up_enc_param()
1423 p_enc_info->initial_info_obtained = false; in wave5_vpu_build_up_enc_param()
1424 p_enc_info->product_code = vpu_read_reg(inst->dev, W5_PRODUCT_NUMBER); in wave5_vpu_build_up_enc_param()
1428 if (wave5_vdi_free_dma_memory(vpu_dev, &p_enc_info->vb_work)) in wave5_vpu_build_up_enc_param()
1429 memset(&p_enc_info->vb_work, 0, sizeof(p_enc_info->vb_work)); in wave5_vpu_build_up_enc_param()
1446 pad_right = aligned_width - src_width; in wave5_set_enc_crop_info()
1447 pad_bot = aligned_height - src_height; in wave5_set_enc_crop_info()
1449 if (param->conf_win_right > 0) in wave5_set_enc_crop_info()
1450 crop_right = param->conf_win_right + pad_right; in wave5_set_enc_crop_info()
1454 if (param->conf_win_bot > 0) in wave5_set_enc_crop_info()
1455 crop_bot = param->conf_win_bot + pad_bot; in wave5_set_enc_crop_info()
1459 crop_top = param->conf_win_top; in wave5_set_enc_crop_info()
1460 crop_left = param->conf_win_left; in wave5_set_enc_crop_info()
1462 param->conf_win_top = crop_top; in wave5_set_enc_crop_info()
1463 param->conf_win_left = crop_left; in wave5_set_enc_crop_info()
1464 param->conf_win_bot = crop_bot; in wave5_set_enc_crop_info()
1465 param->conf_win_right = crop_right; in wave5_set_enc_crop_info()
1472 param->conf_win_top = crop_right; in wave5_set_enc_crop_info()
1473 param->conf_win_left = crop_top; in wave5_set_enc_crop_info()
1474 param->conf_win_bot = crop_left; in wave5_set_enc_crop_info()
1475 param->conf_win_right = crop_bot; in wave5_set_enc_crop_info()
1479 param->conf_win_top = crop_bot; in wave5_set_enc_crop_info()
1480 param->conf_win_left = crop_right; in wave5_set_enc_crop_info()
1481 param->conf_win_bot = crop_top; in wave5_set_enc_crop_info()
1482 param->conf_win_right = crop_left; in wave5_set_enc_crop_info()
1486 param->conf_win_top = crop_left; in wave5_set_enc_crop_info()
1487 param->conf_win_left = crop_bot; in wave5_set_enc_crop_info()
1488 param->conf_win_bot = crop_right; in wave5_set_enc_crop_info()
1489 param->conf_win_right = crop_top; in wave5_set_enc_crop_info()
1493 param->conf_win_top = crop_bot; in wave5_set_enc_crop_info()
1494 param->conf_win_bot = crop_top; in wave5_set_enc_crop_info()
1498 param->conf_win_left = crop_right; in wave5_set_enc_crop_info()
1499 param->conf_win_right = crop_left; in wave5_set_enc_crop_info()
1503 param->conf_win_top = crop_left; in wave5_set_enc_crop_info()
1504 param->conf_win_left = crop_top; in wave5_set_enc_crop_info()
1505 param->conf_win_bot = crop_right; in wave5_set_enc_crop_info()
1506 param->conf_win_right = crop_bot; in wave5_set_enc_crop_info()
1510 param->conf_win_top = crop_right; in wave5_set_enc_crop_info()
1511 param->conf_win_left = crop_bot; in wave5_set_enc_crop_info()
1512 param->conf_win_bot = crop_left; in wave5_set_enc_crop_info()
1513 param->conf_win_right = crop_top; in wave5_set_enc_crop_info()
1516 WARN(1, "Invalid prp_mode: %d, must be in range of 1 - 15\n", prp_mode); in wave5_set_enc_crop_info()
1523 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_init_seq()
1524 struct enc_open_param *p_open_param = &p_enc_info->open_param; in wave5_vpu_enc_init_seq()
1525 struct enc_wave_param *p_param = &p_open_param->wave_param; in wave5_vpu_enc_init_seq()
1532 if (p_enc_info->rotation_enable) { in wave5_vpu_enc_init_seq()
1533 switch (p_enc_info->rotation_angle) { in wave5_vpu_enc_init_seq()
1549 if (p_enc_info->mirror_enable) { in wave5_vpu_enc_init_seq()
1550 switch (p_enc_info->mirror_direction) { in wave5_vpu_enc_init_seq()
1566 wave5_set_enc_crop_info(inst->std, p_param, rot_mir_mode, p_open_param->pic_width, in wave5_vpu_enc_init_seq()
1567 p_open_param->pic_height); in wave5_vpu_enc_init_seq()
1570 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SET_PARAM_OPTION, OPT_COMMON); in wave5_vpu_enc_init_seq()
1571 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SRC_SIZE, p_open_param->pic_height << 16 in wave5_vpu_enc_init_seq()
1572 | p_open_param->pic_width); in wave5_vpu_enc_init_seq()
1573 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MAP_ENDIAN, VDI_LITTLE_ENDIAN); in wave5_vpu_enc_init_seq()
1575 reg_val = p_param->profile | in wave5_vpu_enc_init_seq()
1576 (p_param->level << 3) | in wave5_vpu_enc_init_seq()
1577 (p_param->internal_bit_depth << 14); in wave5_vpu_enc_init_seq()
1578 if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1579 reg_val |= (p_param->tier << 12) | in wave5_vpu_enc_init_seq()
1580 (p_param->tmvp_enable << 23) | in wave5_vpu_enc_init_seq()
1581 (p_param->sao_enable << 24) | in wave5_vpu_enc_init_seq()
1582 (p_param->skip_intra_trans << 25) | in wave5_vpu_enc_init_seq()
1583 (p_param->strong_intra_smooth_enable << 27) | in wave5_vpu_enc_init_seq()
1584 (p_param->en_still_picture << 30); in wave5_vpu_enc_init_seq()
1585 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_SPS_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1587 reg_val = (p_param->lossless_enable) | in wave5_vpu_enc_init_seq()
1588 (p_param->const_intra_pred_flag << 1) | in wave5_vpu_enc_init_seq()
1589 (p_param->lf_cross_slice_boundary_enable << 2) | in wave5_vpu_enc_init_seq()
1590 (p_param->wpp_enable << 4) | in wave5_vpu_enc_init_seq()
1591 (p_param->disable_deblk << 5) | in wave5_vpu_enc_init_seq()
1592 ((p_param->beta_offset_div2 & 0xF) << 6) | in wave5_vpu_enc_init_seq()
1593 ((p_param->tc_offset_div2 & 0xF) << 10) | in wave5_vpu_enc_init_seq()
1594 ((p_param->chroma_cb_qp_offset & 0x1F) << 14) | in wave5_vpu_enc_init_seq()
1595 ((p_param->chroma_cr_qp_offset & 0x1F) << 19) | in wave5_vpu_enc_init_seq()
1596 (p_param->transform8x8_enable << 29) | in wave5_vpu_enc_init_seq()
1597 (p_param->entropy_coding_mode << 30); in wave5_vpu_enc_init_seq()
1598 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_PPS_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1600 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_GOP_PARAM, p_param->gop_preset_idx); in wave5_vpu_enc_init_seq()
1602 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1603 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, p_param->intra_qp | in wave5_vpu_enc_init_seq()
1604 ((p_param->intra_period & 0x7ff) << 6) | in wave5_vpu_enc_init_seq()
1605 ((p_param->avc_idr_period & 0x7ff) << 17)); in wave5_vpu_enc_init_seq()
1606 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1607 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_PARAM, in wave5_vpu_enc_init_seq()
1608 p_param->decoding_refresh_type | (p_param->intra_qp << 3) | in wave5_vpu_enc_init_seq()
1609 (p_param->intra_period << 16)); in wave5_vpu_enc_init_seq()
1611 reg_val = (p_param->rdo_skip << 2) | in wave5_vpu_enc_init_seq()
1612 (p_param->lambda_scaling_enable << 3) | in wave5_vpu_enc_init_seq()
1614 (p_param->intra_nx_n_enable << 8) | in wave5_vpu_enc_init_seq()
1615 (p_param->max_num_merge << 18); in wave5_vpu_enc_init_seq()
1617 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RDO_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1619 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1620 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, in wave5_vpu_enc_init_seq()
1621 p_param->intra_mb_refresh_arg << 16 | p_param->intra_mb_refresh_mode); in wave5_vpu_enc_init_seq()
1622 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1623 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INTRA_REFRESH, in wave5_vpu_enc_init_seq()
1624 p_param->intra_refresh_arg << 16 | p_param->intra_refresh_mode); in wave5_vpu_enc_init_seq()
1626 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_FRAME_RATE, p_open_param->frame_rate_info); in wave5_vpu_enc_init_seq()
1627 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_TARGET_RATE, p_open_param->bit_rate); in wave5_vpu_enc_init_seq()
1629 reg_val = p_open_param->rc_enable | in wave5_vpu_enc_init_seq()
1630 (p_param->hvs_qp_enable << 2) | in wave5_vpu_enc_init_seq()
1631 (p_param->hvs_qp_scale << 4) | in wave5_vpu_enc_init_seq()
1632 ((p_param->initial_rc_qp & 0x3F) << 14) | in wave5_vpu_enc_init_seq()
1633 (p_open_param->vbv_buffer_size << 20); in wave5_vpu_enc_init_seq()
1634 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1635 reg_val |= (p_param->mb_level_rc_enable << 1); in wave5_vpu_enc_init_seq()
1636 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1637 reg_val |= (p_param->cu_level_rc_enable << 1); in wave5_vpu_enc_init_seq()
1638 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_PARAM, reg_val); in wave5_vpu_enc_init_seq()
1640 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_WEIGHT_PARAM, in wave5_vpu_enc_init_seq()
1641 p_param->rc_weight_buf << 8 | p_param->rc_weight_param); in wave5_vpu_enc_init_seq()
1643 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_MIN_MAX_QP, p_param->min_qp_i | in wave5_vpu_enc_init_seq()
1644 (p_param->max_qp_i << 6) | (p_param->hvs_max_delta_qp << 12)); in wave5_vpu_enc_init_seq()
1646 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_INTER_MIN_MAX_QP, p_param->min_qp_p | in wave5_vpu_enc_init_seq()
1647 (p_param->max_qp_p << 6) | (p_param->min_qp_b << 12) | in wave5_vpu_enc_init_seq()
1648 (p_param->max_qp_b << 18)); in wave5_vpu_enc_init_seq()
1650 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_0_3, 0); in wave5_vpu_enc_init_seq()
1651 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_RC_BIT_RATIO_LAYER_4_7, 0); in wave5_vpu_enc_init_seq()
1652 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_ROT_PARAM, rot_mir_mode); in wave5_vpu_enc_init_seq()
1654 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_BG_PARAM, 0); in wave5_vpu_enc_init_seq()
1655 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_LAMBDA_ADDR, 0); in wave5_vpu_enc_init_seq()
1656 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_TOP_BOT, in wave5_vpu_enc_init_seq()
1657 p_param->conf_win_bot << 16 | p_param->conf_win_top); in wave5_vpu_enc_init_seq()
1658 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CONF_WIN_LEFT_RIGHT, in wave5_vpu_enc_init_seq()
1659 p_param->conf_win_right << 16 | p_param->conf_win_left); in wave5_vpu_enc_init_seq()
1661 if (inst->std == W_AVC_ENC) in wave5_vpu_enc_init_seq()
1662 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1663 p_param->avc_slice_arg << 16 | p_param->avc_slice_mode); in wave5_vpu_enc_init_seq()
1664 else if (inst->std == W_HEVC_ENC) in wave5_vpu_enc_init_seq()
1665 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_INDEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1666 p_param->independ_slice_mode_arg << 16 | in wave5_vpu_enc_init_seq()
1667 p_param->independ_slice_mode); in wave5_vpu_enc_init_seq()
1669 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_USER_SCALING_LIST_ADDR, 0); in wave5_vpu_enc_init_seq()
1670 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_UNITS_IN_TICK, 0); in wave5_vpu_enc_init_seq()
1671 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_TIME_SCALE, 0); in wave5_vpu_enc_init_seq()
1672 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NUM_TICKS_POC_DIFF_ONE, 0); in wave5_vpu_enc_init_seq()
1674 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_init_seq()
1675 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU04, 0); in wave5_vpu_enc_init_seq()
1676 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU08, 0); in wave5_vpu_enc_init_seq()
1677 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU16, 0); in wave5_vpu_enc_init_seq()
1678 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_PU32, 0); in wave5_vpu_enc_init_seq()
1679 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU08, 0); in wave5_vpu_enc_init_seq()
1680 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU16, 0); in wave5_vpu_enc_init_seq()
1681 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_CUSTOM_MD_CU32, 0); in wave5_vpu_enc_init_seq()
1682 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_DEPENDENT_SLICE, in wave5_vpu_enc_init_seq()
1683 p_param->depend_slice_mode_arg << 16 | p_param->depend_slice_mode); in wave5_vpu_enc_init_seq()
1685 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_PARAM, 0); in wave5_vpu_enc_init_seq()
1687 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_NR_WEIGHT, in wave5_vpu_enc_init_seq()
1688 p_param->nr_intra_weight_y | in wave5_vpu_enc_init_seq()
1689 (p_param->nr_intra_weight_cb << 5) | in wave5_vpu_enc_init_seq()
1690 (p_param->nr_intra_weight_cr << 10) | in wave5_vpu_enc_init_seq()
1691 (p_param->nr_inter_weight_y << 15) | in wave5_vpu_enc_init_seq()
1692 (p_param->nr_inter_weight_cb << 20) | in wave5_vpu_enc_init_seq()
1693 (p_param->nr_inter_weight_cr << 25)); in wave5_vpu_enc_init_seq()
1695 vpu_write_reg(inst->dev, W5_CMD_ENC_SEQ_VUI_HRD_PARAM, 0); in wave5_vpu_enc_init_seq()
1704 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_get_seq_info()
1707 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_enc_get_seq_info()
1711 dev_dbg(inst->dev->dev, "%s: init seq\n", __func__); in wave5_vpu_enc_get_seq_info()
1713 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_enc_get_seq_info()
1715 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_enc_get_seq_info()
1716 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_enc_get_seq_info()
1718 if (vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS) != 1) { in wave5_vpu_enc_get_seq_info()
1719 info->seq_init_err_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); in wave5_vpu_enc_get_seq_info()
1720 ret = -EIO; in wave5_vpu_enc_get_seq_info()
1722 info->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); in wave5_vpu_enc_get_seq_info()
1725 info->min_frame_buffer_count = vpu_read_reg(inst->dev, W5_RET_ENC_NUM_REQUIRED_FB); in wave5_vpu_enc_get_seq_info()
1726 info->min_src_frame_count = vpu_read_reg(inst->dev, W5_RET_ENC_MIN_SRC_BUF_NUM); in wave5_vpu_enc_get_seq_info()
1727 info->vlc_buf_size = vpu_read_reg(inst->dev, W5_RET_VLC_BUF_SIZE); in wave5_vpu_enc_get_seq_info()
1728 info->param_buf_size = vpu_read_reg(inst->dev, W5_RET_PARAM_BUF_SIZE); in wave5_vpu_enc_get_seq_info()
1729 p_enc_info->vlc_buf_size = info->vlc_buf_size; in wave5_vpu_enc_get_seq_info()
1730 p_enc_info->param_buf_size = info->param_buf_size; in wave5_vpu_enc_get_seq_info()
1759 bool avc_encoding = (inst->std == W_AVC_ENC); in wave5_vpu_enc_register_framebuffer()
1766 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_register_framebuffer()
1768 p_open_param = &p_enc_info->open_param; in wave5_vpu_enc_register_framebuffer()
1772 stride = p_enc_info->stride; in wave5_vpu_enc_register_framebuffer()
1773 bit_depth = p_open_param->wave_param.internal_bit_depth; in wave5_vpu_enc_register_framebuffer()
1776 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1777 buf_height = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1779 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
1780 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
1781 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
1782 buf_width = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1783 buf_height = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1786 if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { in wave5_vpu_enc_register_framebuffer()
1787 buf_width = ALIGN(p_open_param->pic_height, 16); in wave5_vpu_enc_register_framebuffer()
1788 buf_height = ALIGN(p_open_param->pic_width, 16); in wave5_vpu_enc_register_framebuffer()
1791 buf_width = ALIGN(p_open_param->pic_width, 8); in wave5_vpu_enc_register_framebuffer()
1792 buf_height = ALIGN(p_open_param->pic_height, 8); in wave5_vpu_enc_register_framebuffer()
1794 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
1795 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
1796 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
1797 buf_width = ALIGN(p_open_param->pic_width, 32); in wave5_vpu_enc_register_framebuffer()
1798 buf_height = ALIGN(p_open_param->pic_height, 32); in wave5_vpu_enc_register_framebuffer()
1801 if (p_enc_info->rotation_angle == 90 || p_enc_info->rotation_angle == 270) { in wave5_vpu_enc_register_framebuffer()
1802 buf_width = ALIGN(p_open_param->pic_height, 32); in wave5_vpu_enc_register_framebuffer()
1803 buf_height = ALIGN(p_open_param->pic_width, 32); in wave5_vpu_enc_register_framebuffer()
1824 p_enc_info->vb_mv = vb_mv; in wave5_vpu_enc_register_framebuffer()
1835 p_enc_info->vb_fbc_y_tbl = vb_fbc_y_tbl; in wave5_vpu_enc_register_framebuffer()
1843 p_enc_info->vb_fbc_c_tbl = vb_fbc_c_tbl; in wave5_vpu_enc_register_framebuffer()
1855 p_enc_info->vb_sub_sam_buf = vb_sub_sam_buf; in wave5_vpu_enc_register_framebuffer()
1857 vb_task.size = (p_enc_info->vlc_buf_size * VLC_BUF_NUM) + in wave5_vpu_enc_register_framebuffer()
1858 (p_enc_info->param_buf_size * COMMAND_QUEUE_DEPTH); in wave5_vpu_enc_register_framebuffer()
1860 if (p_enc_info->vb_task.size == 0) { in wave5_vpu_enc_register_framebuffer()
1865 p_enc_info->vb_task = vb_task; in wave5_vpu_enc_register_framebuffer()
1867 vpu_write_reg(inst->dev, W5_CMD_SET_FB_ADDR_TASK_BUF, in wave5_vpu_enc_register_framebuffer()
1868 p_enc_info->vb_task.daddr); in wave5_vpu_enc_register_framebuffer()
1869 vpu_write_reg(inst->dev, W5_CMD_SET_FB_TASK_BUF_SIZE, vb_task.size); in wave5_vpu_enc_register_framebuffer()
1872 /* set sub-sampled buffer base addr */ in wave5_vpu_enc_register_framebuffer()
1873 vpu_write_reg(inst->dev, W5_ADDR_SUB_SAMPLED_FB_BASE, vb_sub_sam_buf.daddr); in wave5_vpu_enc_register_framebuffer()
1874 /* set sub-sampled buffer size for one frame */ in wave5_vpu_enc_register_framebuffer()
1875 vpu_write_reg(inst->dev, W5_SUB_SAMPLED_ONE_FB_SIZE, sub_sampled_size); in wave5_vpu_enc_register_framebuffer()
1877 vpu_write_reg(inst->dev, W5_PIC_SIZE, pic_size); in wave5_vpu_enc_register_framebuffer()
1880 if ((p_enc_info->rotation_angle || p_enc_info->mirror_direction) && in wave5_vpu_enc_register_framebuffer()
1881 !(p_enc_info->rotation_angle == 180 && in wave5_vpu_enc_register_framebuffer()
1882 p_enc_info->mirror_direction == MIRDIR_HOR_VER)) { in wave5_vpu_enc_register_framebuffer()
1886 luma_stride = calculate_luma_stride(p_open_param->pic_width, bit_depth); in wave5_vpu_enc_register_framebuffer()
1887 chroma_stride = calculate_chroma_stride(p_open_param->pic_width / 2, bit_depth); in wave5_vpu_enc_register_framebuffer()
1890 vpu_write_reg(inst->dev, W5_FBC_STRIDE, luma_stride << 16 | chroma_stride); in wave5_vpu_enc_register_framebuffer()
1891 vpu_write_reg(inst->dev, W5_COMMON_PIC_INFO, stride); in wave5_vpu_enc_register_framebuffer()
1897 reg_val = (j == cnt_8_chunk - 1) << 4 | ((j == 0) << 3); in wave5_vpu_enc_register_framebuffer()
1898 vpu_write_reg(inst->dev, W5_SFB_OPTION, reg_val); in wave5_vpu_enc_register_framebuffer()
1900 end_no = start_no + ((remain >= 8) ? 8 : remain) - 1; in wave5_vpu_enc_register_framebuffer()
1902 vpu_write_reg(inst->dev, W5_SET_FB_NUM, (start_no << 8) | end_no); in wave5_vpu_enc_register_framebuffer()
1905 vpu_write_reg(inst->dev, W5_ADDR_LUMA_BASE0 + (i << 4), fb_arr[i + in wave5_vpu_enc_register_framebuffer()
1907 vpu_write_reg(inst->dev, W5_ADDR_CB_BASE0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
1910 vpu_write_reg(inst->dev, W5_ADDR_FBC_Y_OFFSET0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
1913 vpu_write_reg(inst->dev, W5_ADDR_FBC_C_OFFSET0 + (i << 4), in wave5_vpu_enc_register_framebuffer()
1916 vpu_write_reg(inst->dev, W5_ADDR_MV_COL0 + (i << 2), in wave5_vpu_enc_register_framebuffer()
1920 remain -= i; in wave5_vpu_enc_register_framebuffer()
1951 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_encode()
1952 struct frame_buffer *p_src_frame = option->source_frame; in wave5_vpu_encode()
1953 struct enc_open_param *p_open_param = &p_enc_info->open_param; in wave5_vpu_encode()
1954 bool justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode() local
1958 vpu_write_reg(inst->dev, W5_CMD_ENC_BS_START_ADDR, option->pic_stream_buffer_addr); in wave5_vpu_encode()
1959 vpu_write_reg(inst->dev, W5_CMD_ENC_BS_SIZE, option->pic_stream_buffer_size); in wave5_vpu_encode()
1960 p_enc_info->stream_buf_start_addr = option->pic_stream_buffer_addr; in wave5_vpu_encode()
1961 p_enc_info->stream_buf_size = option->pic_stream_buffer_size; in wave5_vpu_encode()
1962 p_enc_info->stream_buf_end_addr = in wave5_vpu_encode()
1963 option->pic_stream_buffer_addr + option->pic_stream_buffer_size; in wave5_vpu_encode()
1965 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_AXI_SEL, DEFAULT_SRC_AXI); in wave5_vpu_encode()
1967 reg_val = (p_enc_info->sec_axi_info.use_enc_rdo_enable << 11) | in wave5_vpu_encode()
1968 (p_enc_info->sec_axi_info.use_enc_lf_enable << 15); in wave5_vpu_encode()
1969 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_USE_SEC_AXI, reg_val); in wave5_vpu_encode()
1971 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_REPORT_PARAM, 0); in wave5_vpu_encode()
1977 if (option->code_option.implicit_header_encode) in wave5_vpu_encode()
1978 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, in wave5_vpu_encode()
1980 (option->code_option.encode_aud << 5) | in wave5_vpu_encode()
1981 (option->code_option.encode_eos << 6) | in wave5_vpu_encode()
1982 (option->code_option.encode_eob << 7)); in wave5_vpu_encode()
1984 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CODE_OPTION, in wave5_vpu_encode()
1985 option->code_option.implicit_header_encode | in wave5_vpu_encode()
1986 (option->code_option.encode_vcl << 1) | in wave5_vpu_encode()
1987 (option->code_option.encode_vps << 2) | in wave5_vpu_encode()
1988 (option->code_option.encode_sps << 3) | in wave5_vpu_encode()
1989 (option->code_option.encode_pps << 4) | in wave5_vpu_encode()
1990 (option->code_option.encode_aud << 5) | in wave5_vpu_encode()
1991 (option->code_option.encode_eos << 6) | in wave5_vpu_encode()
1992 (option->code_option.encode_eob << 7)); in wave5_vpu_encode()
1994 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PIC_PARAM, 0); in wave5_vpu_encode()
1996 if (option->src_end_flag) in wave5_vpu_encode()
1998 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, 0xFFFFFFFF); in wave5_vpu_encode()
2000 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_PIC_IDX, option->src_idx); in wave5_vpu_encode()
2002 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_Y, p_src_frame->buf_y); in wave5_vpu_encode()
2003 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_U, p_src_frame->buf_cb); in wave5_vpu_encode()
2004 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_ADDR_V, p_src_frame->buf_cr); in wave5_vpu_encode()
2006 switch (p_open_param->src_format) { in wave5_vpu_encode()
2013 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2015 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2016 (p_src_frame->stride / 2); in wave5_vpu_encode()
2017 src_stride_c = (p_open_param->src_format == FORMAT_422) ? src_stride_c * 2 : in wave5_vpu_encode()
2026 justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode()
2028 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2029 (p_src_frame->stride / 2); in wave5_vpu_encode()
2030 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2039 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2041 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2042 (p_src_frame->stride / 2); in wave5_vpu_encode()
2043 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2052 justified = WTL_RIGHT_JUSTIFIED; in wave5_vpu_encode()
2054 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2055 ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); in wave5_vpu_encode()
2056 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2065 justified = WTL_LEFT_JUSTIFIED; in wave5_vpu_encode()
2067 src_stride_c = inst->cbcr_interleave ? p_src_frame->stride : in wave5_vpu_encode()
2068 ALIGN(p_src_frame->stride / 2, 16) * BIT(inst->cbcr_interleave); in wave5_vpu_encode()
2069 src_stride_c = (p_open_param->src_format == in wave5_vpu_encode()
2073 return -EINVAL; in wave5_vpu_encode()
2076 src_frame_format = (inst->cbcr_interleave << 1) | (inst->nv21); in wave5_vpu_encode()
2077 switch (p_open_param->packed_format) { in wave5_vpu_encode()
2094 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_STRIDE, in wave5_vpu_encode()
2095 (p_src_frame->stride << 16) | src_stride_c); in wave5_vpu_encode()
2096 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SRC_FORMAT, src_frame_format | in wave5_vpu_encode()
2097 (format_no << 3) | (justified << 5) | (PIC_SRC_ENDIANNESS_BIG_ENDIAN << 6)); in wave5_vpu_encode()
2099 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_ADDR, 0); in wave5_vpu_encode()
2100 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_CUSTOM_MAP_OPTION_PARAM, 0); in wave5_vpu_encode()
2101 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_LONGTERM_PIC, 0); in wave5_vpu_encode()
2102 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_Y, 0); in wave5_vpu_encode()
2103 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_SIGMA_C, 0); in wave5_vpu_encode()
2104 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_Y, 0); in wave5_vpu_encode()
2105 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_WP_PIXEL_MEAN_C, 0); in wave5_vpu_encode()
2106 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_INFO, 0); in wave5_vpu_encode()
2107 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_PREFIX_SEI_NAL_ADDR, 0); in wave5_vpu_encode()
2108 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_INFO, 0); in wave5_vpu_encode()
2109 vpu_write_reg(inst->dev, W5_CMD_ENC_PIC_SUFFIX_SEI_NAL_ADDR, 0); in wave5_vpu_encode()
2112 if (ret == -ETIMEDOUT) in wave5_vpu_encode()
2115 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_encode()
2116 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_encode()
2129 struct enc_info *p_enc_info = &inst->codec_info->enc_info; in wave5_vpu_enc_get_result()
2130 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_enc_get_result()
2132 ret = wave5_send_query(inst->dev, inst, GET_RESULT); in wave5_vpu_enc_get_result()
2136 dev_dbg(inst->dev->dev, "%s: enc pic complete\n", __func__); in wave5_vpu_enc_get_result()
2138 reg_val = vpu_read_reg(inst->dev, W5_RET_QUEUE_STATUS); in wave5_vpu_enc_get_result()
2140 p_enc_info->instance_queue_count = (reg_val >> 16) & 0xff; in wave5_vpu_enc_get_result()
2141 p_enc_info->report_queue_count = (reg_val & QUEUE_REPORT_MASK); in wave5_vpu_enc_get_result()
2143 encoding_success = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_SUCCESS); in wave5_vpu_enc_get_result()
2145 result->error_reason = vpu_read_reg(inst->dev, W5_RET_ENC_ERR_INFO); in wave5_vpu_enc_get_result()
2146 return -EIO; in wave5_vpu_enc_get_result()
2149 result->warn_info = vpu_read_reg(inst->dev, W5_RET_ENC_WARN_INFO); in wave5_vpu_enc_get_result()
2151 reg_val = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_TYPE); in wave5_vpu_enc_get_result()
2152 result->pic_type = reg_val & 0xFFFF; in wave5_vpu_enc_get_result()
2154 result->enc_vcl_nut = vpu_read_reg(inst->dev, W5_RET_ENC_VCL_NUT); in wave5_vpu_enc_get_result()
2157 * inst->frame_buf in wave5_vpu_enc_get_result()
2159 result->recon_frame_index = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_IDX); in wave5_vpu_enc_get_result()
2160 result->enc_pic_byte = vpu_read_reg(inst->dev, W5_RET_ENC_PIC_BYTE); in wave5_vpu_enc_get_result()
2161 result->enc_src_idx = vpu_read_reg(inst->dev, W5_RET_ENC_USED_SRC_IDX); in wave5_vpu_enc_get_result()
2162 p_enc_info->stream_wr_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_WR_PTR); in wave5_vpu_enc_get_result()
2163 p_enc_info->stream_rd_ptr = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); in wave5_vpu_enc_get_result()
2165 result->bitstream_buffer = vpu_read_reg(inst->dev, W5_RET_ENC_RD_PTR); in wave5_vpu_enc_get_result()
2166 result->rd_ptr = p_enc_info->stream_rd_ptr; in wave5_vpu_enc_get_result()
2167 result->wr_ptr = p_enc_info->stream_wr_ptr; in wave5_vpu_enc_get_result()
2170 if (result->recon_frame_index == RECON_IDX_FLAG_HEADER_ONLY) in wave5_vpu_enc_get_result()
2171 result->bitstream_size = result->enc_pic_byte; in wave5_vpu_enc_get_result()
2172 else if (result->recon_frame_index < 0) in wave5_vpu_enc_get_result()
2173 result->bitstream_size = 0; in wave5_vpu_enc_get_result()
2175 result->bitstream_size = result->enc_pic_byte; in wave5_vpu_enc_get_result()
2177 result->enc_host_cmd_tick = vpu_read_reg(inst->dev, W5_RET_ENC_HOST_CMD_TICK); in wave5_vpu_enc_get_result()
2178 result->enc_encode_end_tick = vpu_read_reg(inst->dev, W5_RET_ENC_ENCODING_END_TICK); in wave5_vpu_enc_get_result()
2180 if (!p_enc_info->first_cycle_check) { in wave5_vpu_enc_get_result()
2181 result->frame_cycle = (result->enc_encode_end_tick - result->enc_host_cmd_tick) * in wave5_vpu_enc_get_result()
2182 p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2183 p_enc_info->first_cycle_check = true; in wave5_vpu_enc_get_result()
2185 result->frame_cycle = in wave5_vpu_enc_get_result()
2186 (result->enc_encode_end_tick - vpu_dev->last_performance_cycles) * in wave5_vpu_enc_get_result()
2187 p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2188 if (vpu_dev->last_performance_cycles < result->enc_host_cmd_tick) in wave5_vpu_enc_get_result()
2189 result->frame_cycle = (result->enc_encode_end_tick - in wave5_vpu_enc_get_result()
2190 result->enc_host_cmd_tick) * p_enc_info->cycle_per_tick; in wave5_vpu_enc_get_result()
2192 vpu_dev->last_performance_cycles = result->enc_encode_end_tick; in wave5_vpu_enc_get_result()
2206 struct enc_wave_param *param = &open_param->wave_param; in wave5_vpu_enc_check_common_param_valid()
2207 struct vpu_device *vpu_dev = inst->dev; in wave5_vpu_enc_check_common_param_valid()
2208 struct device *dev = vpu_dev->dev; in wave5_vpu_enc_check_common_param_valid()
2209 u32 num_ctu_row = (open_param->pic_height + 64 - 1) / 64; in wave5_vpu_enc_check_common_param_valid()
2210 u32 num_ctu_col = (open_param->pic_width + 64 - 1) / 64; in wave5_vpu_enc_check_common_param_valid()
2213 if (inst->std == W_HEVC_ENC && low_delay && in wave5_vpu_enc_check_common_param_valid()
2214 param->decoding_refresh_type == DEC_REFRESH_TYPE_CRA) { in wave5_vpu_enc_check_common_param_valid()
2218 param->decoding_refresh_type = 2; in wave5_vpu_enc_check_common_param_valid()
2221 if (param->wpp_enable && param->independ_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2222 unsigned int num_ctb_in_width = ALIGN(open_param->pic_width, 64) >> 6; in wave5_vpu_enc_check_common_param_valid()
2224 if (param->independ_slice_mode_arg % num_ctb_in_width) { in wave5_vpu_enc_check_common_param_valid()
2226 param->independ_slice_mode_arg, num_ctb_in_width); in wave5_vpu_enc_check_common_param_valid()
2231 /* multi-slice & wpp */ in wave5_vpu_enc_check_common_param_valid()
2232 if (param->wpp_enable && param->depend_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2237 if (!param->independ_slice_mode && param->depend_slice_mode) { in wave5_vpu_enc_check_common_param_valid()
2240 } else if (param->independ_slice_mode && in wave5_vpu_enc_check_common_param_valid()
2241 param->depend_slice_mode == DEPEND_SLICE_MODE_RECOMMENDED && in wave5_vpu_enc_check_common_param_valid()
2242 param->independ_slice_mode_arg < param->depend_slice_mode_arg) { in wave5_vpu_enc_check_common_param_valid()
2244 param->independ_slice_mode_arg, param->depend_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2248 if (param->independ_slice_mode && param->independ_slice_mode_arg > 65535) { in wave5_vpu_enc_check_common_param_valid()
2250 param->independ_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2254 if (param->depend_slice_mode && param->depend_slice_mode_arg > 65535) { in wave5_vpu_enc_check_common_param_valid()
2256 param->depend_slice_mode_arg); in wave5_vpu_enc_check_common_param_valid()
2260 if (param->conf_win_top % 2) { in wave5_vpu_enc_check_common_param_valid()
2261 dev_err(dev, "conf_win_top: %u, must be a multiple of 2\n", param->conf_win_top); in wave5_vpu_enc_check_common_param_valid()
2265 if (param->conf_win_bot % 2) { in wave5_vpu_enc_check_common_param_valid()
2266 dev_err(dev, "conf_win_bot: %u, must be a multiple of 2\n", param->conf_win_bot); in wave5_vpu_enc_check_common_param_valid()
2270 if (param->conf_win_left % 2) { in wave5_vpu_enc_check_common_param_valid()
2271 dev_err(dev, "conf_win_left: %u, must be a multiple of 2\n", param->conf_win_left); in wave5_vpu_enc_check_common_param_valid()
2275 if (param->conf_win_right % 2) { in wave5_vpu_enc_check_common_param_valid()
2277 param->conf_win_right); in wave5_vpu_enc_check_common_param_valid()
2281 if (param->lossless_enable && open_param->rc_enable) { in wave5_vpu_enc_check_common_param_valid()
2286 if (param->lossless_enable && !param->skip_intra_trans) { in wave5_vpu_enc_check_common_param_valid()
2292 if (param->intra_refresh_mode && param->intra_refresh_arg == 0) { in wave5_vpu_enc_check_common_param_valid()
2294 param->intra_refresh_mode, param->intra_refresh_arg); in wave5_vpu_enc_check_common_param_valid()
2297 switch (param->intra_refresh_mode) { in wave5_vpu_enc_check_common_param_valid()
2299 if (param->intra_mb_refresh_arg > num_ctu_row) in wave5_vpu_enc_check_common_param_valid()
2303 if (param->intra_refresh_arg > num_ctu_col) in wave5_vpu_enc_check_common_param_valid()
2307 if (param->intra_refresh_arg > ctu_sz) in wave5_vpu_enc_check_common_param_valid()
2311 if (param->intra_refresh_arg > ctu_sz) in wave5_vpu_enc_check_common_param_valid()
2313 if (param->lossless_enable) { in wave5_vpu_enc_check_common_param_valid()
2315 param->intra_refresh_mode); in wave5_vpu_enc_check_common_param_valid()
2323 param->intra_refresh_mode, param->intra_refresh_arg, in wave5_vpu_enc_check_common_param_valid()
2331 struct enc_wave_param *param = &open_param->wave_param; in wave5_vpu_enc_check_param_valid()
2333 if (open_param->rc_enable) { in wave5_vpu_enc_check_param_valid()
2334 if (param->min_qp_i > param->max_qp_i || param->min_qp_p > param->max_qp_p || in wave5_vpu_enc_check_param_valid()
2335 param->min_qp_b > param->max_qp_b) { in wave5_vpu_enc_check_param_valid()
2336 dev_err(vpu_dev->dev, "Configuration failed because min_qp is greater than max_qp\n"); in wave5_vpu_enc_check_param_valid()
2337 dev_err(vpu_dev->dev, "Suggested configuration parameters: min_qp = max_qp\n"); in wave5_vpu_enc_check_param_valid()
2341 if (open_param->bit_rate <= (int)open_param->frame_rate_info) { in wave5_vpu_enc_check_param_valid()
2342 dev_err(vpu_dev->dev, in wave5_vpu_enc_check_param_valid()
2344 open_param->bit_rate, (int)open_param->frame_rate_info); in wave5_vpu_enc_check_param_valid()
2356 s32 product_id = inst->dev->product; in wave5_vpu_enc_check_open_param()
2357 struct vpu_attr *p_attr = &inst->dev->attr; in wave5_vpu_enc_check_open_param()
2361 return -EINVAL; in wave5_vpu_enc_check_open_param()
2363 param = &open_param->wave_param; in wave5_vpu_enc_check_open_param()
2364 pic_width = open_param->pic_width; in wave5_vpu_enc_check_open_param()
2365 pic_height = open_param->pic_height; in wave5_vpu_enc_check_open_param()
2367 if (inst->id >= MAX_NUM_INSTANCE) { in wave5_vpu_enc_check_open_param()
2368 dev_err(inst->dev->dev, "Too many simultaneous instances: %d (max: %u)\n", in wave5_vpu_enc_check_open_param()
2369 inst->id, MAX_NUM_INSTANCE); in wave5_vpu_enc_check_open_param()
2370 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2373 if (inst->std != W_HEVC_ENC && in wave5_vpu_enc_check_open_param()
2374 !(inst->std == W_AVC_ENC && product_id == PRODUCT_ID_521)) { in wave5_vpu_enc_check_open_param()
2375 dev_err(inst->dev->dev, "Unsupported encoder-codec & product combination\n"); in wave5_vpu_enc_check_open_param()
2376 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2379 if (param->internal_bit_depth == 10) { in wave5_vpu_enc_check_open_param()
2380 if (inst->std == W_HEVC_ENC && !p_attr->support_hevc10bit_enc) { in wave5_vpu_enc_check_open_param()
2381 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2383 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2384 } else if (inst->std == W_AVC_ENC && !p_attr->support_avc10bit_enc) { in wave5_vpu_enc_check_open_param()
2385 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2387 return -EOPNOTSUPP; in wave5_vpu_enc_check_open_param()
2391 if (!open_param->frame_rate_info) { in wave5_vpu_enc_check_open_param()
2392 dev_err(inst->dev->dev, "No frame rate information.\n"); in wave5_vpu_enc_check_open_param()
2393 return -EINVAL; in wave5_vpu_enc_check_open_param()
2396 if (open_param->bit_rate > MAX_BIT_RATE) { in wave5_vpu_enc_check_open_param()
2397 dev_err(inst->dev->dev, "Invalid encoding bit-rate: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2398 open_param->bit_rate, MAX_BIT_RATE); in wave5_vpu_enc_check_open_param()
2399 return -EINVAL; in wave5_vpu_enc_check_open_param()
2404 dev_err(inst->dev->dev, "Invalid encoding dimension: %ux%u\n", in wave5_vpu_enc_check_open_param()
2406 return -EINVAL; in wave5_vpu_enc_check_open_param()
2409 if (param->profile) { in wave5_vpu_enc_check_open_param()
2410 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_check_open_param()
2411 if ((param->profile != HEVC_PROFILE_MAIN || in wave5_vpu_enc_check_open_param()
2412 (param->profile == HEVC_PROFILE_MAIN && in wave5_vpu_enc_check_open_param()
2413 param->internal_bit_depth > 8)) && in wave5_vpu_enc_check_open_param()
2414 (param->profile != HEVC_PROFILE_MAIN10 || in wave5_vpu_enc_check_open_param()
2415 (param->profile == HEVC_PROFILE_MAIN10 && in wave5_vpu_enc_check_open_param()
2416 param->internal_bit_depth < 10)) && in wave5_vpu_enc_check_open_param()
2417 param->profile != HEVC_PROFILE_STILLPICTURE) { in wave5_vpu_enc_check_open_param()
2418 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2419 "Invalid HEVC encoding profile: %u (bit-depth: %u)\n", in wave5_vpu_enc_check_open_param()
2420 param->profile, param->internal_bit_depth); in wave5_vpu_enc_check_open_param()
2421 return -EINVAL; in wave5_vpu_enc_check_open_param()
2423 } else if (inst->std == W_AVC_ENC) { in wave5_vpu_enc_check_open_param()
2424 if ((param->internal_bit_depth > 8 && in wave5_vpu_enc_check_open_param()
2425 param->profile != H264_PROFILE_HIGH10)) { in wave5_vpu_enc_check_open_param()
2426 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2427 "Invalid AVC encoding profile: %u (bit-depth: %u)\n", in wave5_vpu_enc_check_open_param()
2428 param->profile, param->internal_bit_depth); in wave5_vpu_enc_check_open_param()
2429 return -EINVAL; in wave5_vpu_enc_check_open_param()
2434 if (param->decoding_refresh_type > DEC_REFRESH_TYPE_IDR) { in wave5_vpu_enc_check_open_param()
2435 dev_err(inst->dev->dev, "Invalid decoding refresh type: %u (valid: 0-2)\n", in wave5_vpu_enc_check_open_param()
2436 param->decoding_refresh_type); in wave5_vpu_enc_check_open_param()
2437 return -EINVAL; in wave5_vpu_enc_check_open_param()
2440 if (param->intra_refresh_mode > REFRESH_MODE_CTUS) { in wave5_vpu_enc_check_open_param()
2441 dev_err(inst->dev->dev, "Invalid intra refresh mode: %d (valid: 0-4)\n", in wave5_vpu_enc_check_open_param()
2442 param->intra_refresh_mode); in wave5_vpu_enc_check_open_param()
2443 return -EINVAL; in wave5_vpu_enc_check_open_param()
2446 if (inst->std == W_HEVC_ENC && param->independ_slice_mode && in wave5_vpu_enc_check_open_param()
2447 param->depend_slice_mode > DEPEND_SLICE_MODE_BOOST) { in wave5_vpu_enc_check_open_param()
2448 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2450 return -EINVAL; in wave5_vpu_enc_check_open_param()
2453 if (!param->disable_deblk) { in wave5_vpu_enc_check_open_param()
2454 if (param->beta_offset_div2 < -6 || param->beta_offset_div2 > 6) { in wave5_vpu_enc_check_open_param()
2455 dev_err(inst->dev->dev, "Invalid beta offset: %d (valid: -6-6)\n", in wave5_vpu_enc_check_open_param()
2456 param->beta_offset_div2); in wave5_vpu_enc_check_open_param()
2457 return -EINVAL; in wave5_vpu_enc_check_open_param()
2460 if (param->tc_offset_div2 < -6 || param->tc_offset_div2 > 6) { in wave5_vpu_enc_check_open_param()
2461 dev_err(inst->dev->dev, "Invalid tc offset: %d (valid: -6-6)\n", in wave5_vpu_enc_check_open_param()
2462 param->tc_offset_div2); in wave5_vpu_enc_check_open_param()
2463 return -EINVAL; in wave5_vpu_enc_check_open_param()
2467 if (param->intra_qp > MAX_INTRA_QP) { in wave5_vpu_enc_check_open_param()
2468 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2469 "Invalid intra quantization parameter: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2470 param->intra_qp, MAX_INTRA_QP); in wave5_vpu_enc_check_open_param()
2471 return -EINVAL; in wave5_vpu_enc_check_open_param()
2474 if (open_param->rc_enable) { in wave5_vpu_enc_check_open_param()
2475 if (param->min_qp_i > MAX_INTRA_QP || param->max_qp_i > MAX_INTRA_QP || in wave5_vpu_enc_check_open_param()
2476 param->min_qp_p > MAX_INTRA_QP || param->max_qp_p > MAX_INTRA_QP || in wave5_vpu_enc_check_open_param()
2477 param->min_qp_b > MAX_INTRA_QP || param->max_qp_b > MAX_INTRA_QP) { in wave5_vpu_enc_check_open_param()
2478 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2480 "I: %u-%u, P: %u-%u, B: %u-%u (valid for each: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2481 param->min_qp_i, param->max_qp_i, param->min_qp_p, param->max_qp_p, in wave5_vpu_enc_check_open_param()
2482 param->min_qp_b, param->max_qp_b, MAX_INTRA_QP); in wave5_vpu_enc_check_open_param()
2483 return -EINVAL; in wave5_vpu_enc_check_open_param()
2486 if (param->hvs_qp_enable && param->hvs_max_delta_qp > MAX_HVS_MAX_DELTA_QP) { in wave5_vpu_enc_check_open_param()
2487 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2488 "Invalid HVS max delta quantization parameter: %u (valid: 0-%u)\n", in wave5_vpu_enc_check_open_param()
2489 param->hvs_max_delta_qp, MAX_HVS_MAX_DELTA_QP); in wave5_vpu_enc_check_open_param()
2490 return -EINVAL; in wave5_vpu_enc_check_open_param()
2493 if (open_param->vbv_buffer_size < MIN_VBV_BUFFER_SIZE || in wave5_vpu_enc_check_open_param()
2494 open_param->vbv_buffer_size > MAX_VBV_BUFFER_SIZE) { in wave5_vpu_enc_check_open_param()
2495 dev_err(inst->dev->dev, "VBV buffer size: %u (valid: %u-%u)\n", in wave5_vpu_enc_check_open_param()
2496 open_param->vbv_buffer_size, MIN_VBV_BUFFER_SIZE, in wave5_vpu_enc_check_open_param()
2498 return -EINVAL; in wave5_vpu_enc_check_open_param()
2503 return -EINVAL; in wave5_vpu_enc_check_open_param()
2505 if (!wave5_vpu_enc_check_param_valid(inst->dev, open_param)) in wave5_vpu_enc_check_open_param()
2506 return -EINVAL; in wave5_vpu_enc_check_open_param()
2508 if (param->chroma_cb_qp_offset < -12 || param->chroma_cb_qp_offset > 12) { in wave5_vpu_enc_check_open_param()
2509 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2510 "Invalid chroma Cb quantization parameter offset: %d (valid: -12-12)\n", in wave5_vpu_enc_check_open_param()
2511 param->chroma_cb_qp_offset); in wave5_vpu_enc_check_open_param()
2512 return -EINVAL; in wave5_vpu_enc_check_open_param()
2515 if (param->chroma_cr_qp_offset < -12 || param->chroma_cr_qp_offset > 12) { in wave5_vpu_enc_check_open_param()
2516 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2517 "Invalid chroma Cr quantization parameter offset: %d (valid: -12-12)\n", in wave5_vpu_enc_check_open_param()
2518 param->chroma_cr_qp_offset); in wave5_vpu_enc_check_open_param()
2519 return -EINVAL; in wave5_vpu_enc_check_open_param()
2522 if (param->intra_refresh_mode == REFRESH_MODE_CTU_STEP_SIZE && !param->intra_refresh_arg) { in wave5_vpu_enc_check_open_param()
2523 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2524 "Intra refresh mode CTU step-size requires an argument\n"); in wave5_vpu_enc_check_open_param()
2525 return -EINVAL; in wave5_vpu_enc_check_open_param()
2528 if (inst->std == W_HEVC_ENC) { in wave5_vpu_enc_check_open_param()
2529 if (param->nr_intra_weight_y > MAX_INTRA_WEIGHT || in wave5_vpu_enc_check_open_param()
2530 param->nr_intra_weight_cb > MAX_INTRA_WEIGHT || in wave5_vpu_enc_check_open_param()
2531 param->nr_intra_weight_cr > MAX_INTRA_WEIGHT) { in wave5_vpu_enc_check_open_param()
2532 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2534 param->nr_intra_weight_y, param->nr_intra_weight_cb, in wave5_vpu_enc_check_open_param()
2535 param->nr_intra_weight_cr, MAX_INTRA_WEIGHT); in wave5_vpu_enc_check_open_param()
2536 return -EINVAL; in wave5_vpu_enc_check_open_param()
2539 if (param->nr_inter_weight_y > MAX_INTER_WEIGHT || in wave5_vpu_enc_check_open_param()
2540 param->nr_inter_weight_cb > MAX_INTER_WEIGHT || in wave5_vpu_enc_check_open_param()
2541 param->nr_inter_weight_cr > MAX_INTER_WEIGHT) { in wave5_vpu_enc_check_open_param()
2542 dev_err(inst->dev->dev, in wave5_vpu_enc_check_open_param()
2544 param->nr_inter_weight_y, param->nr_inter_weight_cb, in wave5_vpu_enc_check_open_param()
2545 param->nr_inter_weight_cr, MAX_INTER_WEIGHT); in wave5_vpu_enc_check_open_param()
2546 return -EINVAL; in wave5_vpu_enc_check_open_param()