Lines Matching +full:dphy +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Cadence MIPI-CSI2 RX Controller v1.3
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
91 struct phy *dphy; member
146 csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
148 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_reset()
150 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_reset()
156 writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
157 for (i = 0; i < csi2rx->max_streams; i++) in csi2rx_reset()
158 writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_reset()
173 ret = v4l2_subdev_call_state_active(&csi2rx->subdev, pad, get_fmt, in csi2rx_configure_ext_dphy()
180 link_freq = v4l2_get_link_freq(csi2rx->source_subdev->ctrl_handler, in csi2rx_configure_ext_dphy()
181 fmt->bpp, 2 * csi2rx->num_lanes); in csi2rx_configure_ext_dphy()
186 csi2rx->num_lanes, cfg); in csi2rx_configure_ext_dphy()
190 ret = phy_power_on(csi2rx->dphy); in csi2rx_configure_ext_dphy()
194 ret = phy_configure(csi2rx->dphy, &opts); in csi2rx_configure_ext_dphy()
196 phy_power_off(csi2rx->dphy); in csi2rx_configure_ext_dphy()
210 ret = clk_prepare_enable(csi2rx->p_clk); in csi2rx_start()
214 reset_control_deassert(csi2rx->p_rst); in csi2rx_start()
217 reg = csi2rx->num_lanes << 8; in csi2rx_start()
218 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
219 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]); in csi2rx_start()
220 set_bit(csi2rx->lanes[i], &lanes_used); in csi2rx_start()
229 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start()
231 csi2rx->max_lanes); in csi2rx_start()
236 writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG); in csi2rx_start()
238 ret = v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true); in csi2rx_start()
242 /* Enable DPHY clk and data lanes. */ in csi2rx_start()
243 if (csi2rx->dphy) { in csi2rx_start()
245 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
246 reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1); in csi2rx_start()
247 reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1); in csi2rx_start()
250 writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); in csi2rx_start()
263 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_start()
264 ret = clk_prepare_enable(csi2rx->pixel_clk[i]); in csi2rx_start()
268 reset_control_deassert(csi2rx->pixel_rst[i]); in csi2rx_start()
271 csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); in csi2rx_start()
278 csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); in csi2rx_start()
281 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_start()
284 ret = clk_prepare_enable(csi2rx->sys_clk); in csi2rx_start()
288 reset_control_deassert(csi2rx->sys_rst); in csi2rx_start()
290 if (csi2rx->dphy) { in csi2rx_start()
293 dev_err(csi2rx->dev, in csi2rx_start()
294 "Failed to configure external DPHY: %d\n", ret); in csi2rx_start()
299 clk_disable_unprepare(csi2rx->p_clk); in csi2rx_start()
304 clk_disable_unprepare(csi2rx->sys_clk); in csi2rx_start()
306 for (; i > 0; i--) { in csi2rx_start()
307 reset_control_assert(csi2rx->pixel_rst[i - 1]); in csi2rx_start()
308 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); in csi2rx_start()
312 clk_disable_unprepare(csi2rx->p_clk); in csi2rx_start()
323 clk_prepare_enable(csi2rx->p_clk); in csi2rx_stop()
324 reset_control_assert(csi2rx->sys_rst); in csi2rx_stop()
325 clk_disable_unprepare(csi2rx->sys_clk); in csi2rx_stop()
327 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_stop()
329 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_stop()
331 ret = readl_relaxed_poll_timeout(csi2rx->base + in csi2rx_stop()
337 dev_warn(csi2rx->dev, in csi2rx_stop()
340 reset_control_assert(csi2rx->pixel_rst[i]); in csi2rx_stop()
341 clk_disable_unprepare(csi2rx->pixel_clk[i]); in csi2rx_stop()
344 reset_control_assert(csi2rx->p_rst); in csi2rx_stop()
345 clk_disable_unprepare(csi2rx->p_clk); in csi2rx_stop()
347 if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) in csi2rx_stop()
348 dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); in csi2rx_stop()
350 if (csi2rx->dphy) { in csi2rx_stop()
351 writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); in csi2rx_stop()
353 if (phy_power_off(csi2rx->dphy)) in csi2rx_stop()
354 dev_warn(csi2rx->dev, "Couldn't power off DPHY\n"); in csi2rx_stop()
363 mutex_lock(&csi2rx->lock); in csi2rx_s_stream()
370 if (!csi2rx->count) { in csi2rx_s_stream()
376 csi2rx->count++; in csi2rx_s_stream()
378 csi2rx->count--; in csi2rx_s_stream()
383 if (!csi2rx->count) in csi2rx_s_stream()
388 mutex_unlock(&csi2rx->lock); in csi2rx_s_stream()
400 if (format->pad != CSI2RX_PAD_SINK) in csi2rx_set_fmt()
403 if (!csi2rx_get_fmt_by_code(format->format.code)) in csi2rx_set_fmt()
404 format->format.code = formats[0].code; in csi2rx_set_fmt()
406 format->format.field = V4L2_FIELD_NONE; in csi2rx_set_fmt()
409 fmt = v4l2_subdev_state_get_format(state, format->pad); in csi2rx_set_fmt()
410 *fmt = format->format; in csi2rx_set_fmt()
415 *fmt = format->format; in csi2rx_set_fmt()
467 struct v4l2_subdev *subdev = notifier->sd; in csi2rx_async_bound()
470 csi2rx->source_pad = media_entity_get_fwnode_pad(&s_subdev->entity, in csi2rx_async_bound()
471 s_subdev->fwnode, in csi2rx_async_bound()
473 if (csi2rx->source_pad < 0) { in csi2rx_async_bound()
474 dev_err(csi2rx->dev, "Couldn't find output pad for subdev %s\n", in csi2rx_async_bound()
475 s_subdev->name); in csi2rx_async_bound()
476 return csi2rx->source_pad; in csi2rx_async_bound()
479 csi2rx->source_subdev = s_subdev; in csi2rx_async_bound()
481 dev_dbg(csi2rx->dev, "Bound %s pad: %d\n", s_subdev->name, in csi2rx_async_bound()
482 csi2rx->source_pad); in csi2rx_async_bound()
484 return media_create_pad_link(&csi2rx->source_subdev->entity, in csi2rx_async_bound()
485 csi2rx->source_pad, in csi2rx_async_bound()
486 &csi2rx->subdev.entity, 0, in csi2rx_async_bound()
502 csi2rx->base = devm_platform_ioremap_resource(pdev, 0); in csi2rx_get_resources()
503 if (IS_ERR(csi2rx->base)) in csi2rx_get_resources()
504 return PTR_ERR(csi2rx->base); in csi2rx_get_resources()
506 csi2rx->sys_clk = devm_clk_get(&pdev->dev, "sys_clk"); in csi2rx_get_resources()
507 if (IS_ERR(csi2rx->sys_clk)) { in csi2rx_get_resources()
508 dev_err(&pdev->dev, "Couldn't get sys clock\n"); in csi2rx_get_resources()
509 return PTR_ERR(csi2rx->sys_clk); in csi2rx_get_resources()
512 csi2rx->p_clk = devm_clk_get(&pdev->dev, "p_clk"); in csi2rx_get_resources()
513 if (IS_ERR(csi2rx->p_clk)) { in csi2rx_get_resources()
514 dev_err(&pdev->dev, "Couldn't get P clock\n"); in csi2rx_get_resources()
515 return PTR_ERR(csi2rx->p_clk); in csi2rx_get_resources()
518 csi2rx->sys_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, in csi2rx_get_resources()
520 if (IS_ERR(csi2rx->sys_rst)) in csi2rx_get_resources()
521 return PTR_ERR(csi2rx->sys_rst); in csi2rx_get_resources()
523 csi2rx->p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, in csi2rx_get_resources()
525 if (IS_ERR(csi2rx->p_rst)) in csi2rx_get_resources()
526 return PTR_ERR(csi2rx->p_rst); in csi2rx_get_resources()
528 csi2rx->dphy = devm_phy_optional_get(&pdev->dev, "dphy"); in csi2rx_get_resources()
529 if (IS_ERR(csi2rx->dphy)) { in csi2rx_get_resources()
530 dev_err(&pdev->dev, "Couldn't get external D-PHY\n"); in csi2rx_get_resources()
531 return PTR_ERR(csi2rx->dphy); in csi2rx_get_resources()
534 ret = clk_prepare_enable(csi2rx->p_clk); in csi2rx_get_resources()
536 dev_err(&pdev->dev, "Couldn't prepare and enable P clock\n"); in csi2rx_get_resources()
540 dev_cfg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG); in csi2rx_get_resources()
541 clk_disable_unprepare(csi2rx->p_clk); in csi2rx_get_resources()
543 csi2rx->max_lanes = dev_cfg & 7; in csi2rx_get_resources()
544 if (csi2rx->max_lanes > CSI2RX_LANES_MAX) { in csi2rx_get_resources()
545 dev_err(&pdev->dev, "Invalid number of lanes: %u\n", in csi2rx_get_resources()
546 csi2rx->max_lanes); in csi2rx_get_resources()
547 return -EINVAL; in csi2rx_get_resources()
550 csi2rx->max_streams = (dev_cfg >> 4) & 7; in csi2rx_get_resources()
551 if (csi2rx->max_streams > CSI2RX_STREAMS_MAX) { in csi2rx_get_resources()
552 dev_err(&pdev->dev, "Invalid number of streams: %u\n", in csi2rx_get_resources()
553 csi2rx->max_streams); in csi2rx_get_resources()
554 return -EINVAL; in csi2rx_get_resources()
557 csi2rx->has_internal_dphy = dev_cfg & BIT(3) ? true : false; in csi2rx_get_resources()
560 * FIXME: Once we'll have internal D-PHY support, the check in csi2rx_get_resources()
563 if (!csi2rx->dphy && csi2rx->has_internal_dphy) { in csi2rx_get_resources()
564 dev_err(&pdev->dev, "Internal D-PHY not supported yet\n"); in csi2rx_get_resources()
565 return -EINVAL; in csi2rx_get_resources()
568 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_get_resources()
572 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name); in csi2rx_get_resources()
573 if (IS_ERR(csi2rx->pixel_clk[i])) { in csi2rx_get_resources()
574 dev_err(&pdev->dev, "Couldn't get clock %s\n", name); in csi2rx_get_resources()
575 return PTR_ERR(csi2rx->pixel_clk[i]); in csi2rx_get_resources()
579 csi2rx->pixel_rst[i] = in csi2rx_get_resources()
580 devm_reset_control_get_optional_exclusive(&pdev->dev, in csi2rx_get_resources()
582 if (IS_ERR(csi2rx->pixel_rst[i])) in csi2rx_get_resources()
583 return PTR_ERR(csi2rx->pixel_rst[i]); in csi2rx_get_resources()
597 ep = of_graph_get_endpoint_by_regs(csi2rx->dev->of_node, 0, 0); in csi2rx_parse_dt()
599 return -EINVAL; in csi2rx_parse_dt()
604 dev_err(csi2rx->dev, "Could not parse v4l2 endpoint\n"); in csi2rx_parse_dt()
610 dev_err(csi2rx->dev, "Unsupported media bus type: 0x%x\n", in csi2rx_parse_dt()
613 return -EINVAL; in csi2rx_parse_dt()
616 memcpy(csi2rx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes, in csi2rx_parse_dt()
617 sizeof(csi2rx->lanes)); in csi2rx_parse_dt()
618 csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2rx_parse_dt()
619 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt()
620 dev_err(csi2rx->dev, "Unsupported number of data-lanes: %d\n", in csi2rx_parse_dt()
621 csi2rx->num_lanes); in csi2rx_parse_dt()
623 return -EINVAL; in csi2rx_parse_dt()
626 v4l2_async_subdev_nf_init(&csi2rx->notifier, &csi2rx->subdev); in csi2rx_parse_dt()
628 asd = v4l2_async_nf_add_fwnode_remote(&csi2rx->notifier, fwh, in csi2rx_parse_dt()
632 v4l2_async_nf_cleanup(&csi2rx->notifier); in csi2rx_parse_dt()
636 csi2rx->notifier.ops = &csi2rx_notifier_ops; in csi2rx_parse_dt()
638 ret = v4l2_async_nf_register(&csi2rx->notifier); in csi2rx_parse_dt()
640 v4l2_async_nf_cleanup(&csi2rx->notifier); in csi2rx_parse_dt()
653 return -ENOMEM; in csi2rx_probe()
655 csi2rx->dev = &pdev->dev; in csi2rx_probe()
656 mutex_init(&csi2rx->lock); in csi2rx_probe()
666 csi2rx->subdev.owner = THIS_MODULE; in csi2rx_probe()
667 csi2rx->subdev.dev = &pdev->dev; in csi2rx_probe()
668 v4l2_subdev_init(&csi2rx->subdev, &csi2rx_subdev_ops); in csi2rx_probe()
669 csi2rx->subdev.internal_ops = &csi2rx_internal_ops; in csi2rx_probe()
670 v4l2_set_subdevdata(&csi2rx->subdev, &pdev->dev); in csi2rx_probe()
671 snprintf(csi2rx->subdev.name, sizeof(csi2rx->subdev.name), in csi2rx_probe()
672 "%s.%s", KBUILD_MODNAME, dev_name(&pdev->dev)); in csi2rx_probe()
675 csi2rx->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; in csi2rx_probe()
676 csi2rx->pads[CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; in csi2rx_probe()
678 csi2rx->pads[i].flags = MEDIA_PAD_FL_SOURCE; in csi2rx_probe()
679 csi2rx->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; in csi2rx_probe()
680 csi2rx->subdev.entity.ops = &csi2rx_media_ops; in csi2rx_probe()
682 ret = media_entity_pads_init(&csi2rx->subdev.entity, CSI2RX_PAD_MAX, in csi2rx_probe()
683 csi2rx->pads); in csi2rx_probe()
687 ret = v4l2_subdev_init_finalize(&csi2rx->subdev); in csi2rx_probe()
691 ret = v4l2_async_register_subdev(&csi2rx->subdev); in csi2rx_probe()
695 dev_info(&pdev->dev, in csi2rx_probe()
696 "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n", in csi2rx_probe()
697 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, in csi2rx_probe()
698 csi2rx->dphy ? "external" : in csi2rx_probe()
699 csi2rx->has_internal_dphy ? "internal" : "no"); in csi2rx_probe()
704 v4l2_subdev_cleanup(&csi2rx->subdev); in csi2rx_probe()
706 v4l2_async_nf_unregister(&csi2rx->notifier); in csi2rx_probe()
707 v4l2_async_nf_cleanup(&csi2rx->notifier); in csi2rx_probe()
708 media_entity_cleanup(&csi2rx->subdev.entity); in csi2rx_probe()
718 v4l2_async_nf_unregister(&csi2rx->notifier); in csi2rx_remove()
719 v4l2_async_nf_cleanup(&csi2rx->notifier); in csi2rx_remove()
720 v4l2_async_unregister_subdev(&csi2rx->subdev); in csi2rx_remove()
721 v4l2_subdev_cleanup(&csi2rx->subdev); in csi2rx_remove()
722 media_entity_cleanup(&csi2rx->subdev.entity); in csi2rx_remove()
727 { .compatible = "starfive,jh7110-csi2rx" },
738 .name = "cdns-csi2rx",
744 MODULE_DESCRIPTION("Cadence CSI2-RX controller");