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1 /* SPDX-License-Identifier: GPL-2.0-or-later */
3 * TW5864 driver - registers description
8 /* According to TW5864_datasheet_0.6d.pdf, tw5864b1-ds.pdf */
10 /* Register Description - Direct Map Space */
11 /* 0x0000 ~ 0x1ffc - H264 Register Map */
20 #define TW5864_EMU_EN_ME BIT(1)
26 #define TW5864_EMU_EN_LPF BIT(4)
47 #define TW5864_MAS_SLICE_END BIT(4)
53 * pointer for the last encoded frame of the corresponding channel.
72 * 1: Decode
76 * 0->3 4 VLC data buffer in DDR (1M each)
77 * 0->7 8 VLC data buffer in DDR (512k each)
81 * 0 4CIF in 1 MB
82 * 1 1CIF in 1 MB
86 * 0 2 falf D1 in 1 MB
87 * 1 1 half D1 in 1 MB
101 /* Org Buffer Base for Chroma (default 4) */
103 /* Maximum Number of Buffers (default 4) */
115 /* Ref Buffer Base for Chroma (default 4) */
117 /* Maximum Number of Buffers (default 4) */
132 * 1 DDRA
135 /* VLC Flow Control: 1 for enable */
139 * If DSP_MB_DELAY == 1, MB delay is DSP_MB_DELAY * 128
147 /* DDR-DPR Burst Read Enable */
152 * 1 Select DDRB
157 * 0 Single R/W Access (Host <-> DDR)
158 * 1 Burst R/W Access (Host <-> DPR)
175 * Each two bits are the buffer pointer for the last encoded frame of a channel
181 * [1:0] CH0_MV_PTR, ..., [15:14] CH7_MV_PTR
185 * [1:0] CH8_MV_PTR, ..., [15:14] CH15_MV_PTR
196 * Inter_Mode Start. 2-nd bit? A guess. Missing in datasheet. Without this bit
199 #define TW5864_DSP_INTER_ST BIT(1)
203 * De-interlacer Mode
204 * 1 Shuffled frame
205 * 0 Normal Un-Shuffled Frame
210 * 11: Un-used
211 * 10: down-sample to 1/4
212 * 01: down-sample to 1/2
213 * 00: down-sample disabled
215 #define TW5864_DSP_DWN_X (3 << 4)
218 * 11: Un-used
219 * 10: down-sample to 1/4
220 * 01: down-sample to 1/2
221 * 00: down-sample disabled
225 * 1 Dual Stream
232 /* Number of reference frame (Default 1 for TW5864B) */
242 * 1 DSP_SKIP_OFFSET value is used in HW
253 #define TW5864_HPEL_EN BIT(1)
259 #define TW5864_SKIP_EN BIT(4)
284 /* Number of bits to shift with TW5864_DSP_ENC_ORG_PTR */
287 /* DDR base address of OSD rectangle attribute data */
292 /* 0x0280 ~ 0x029c - Motion Vector for 1st 4x4 Block, e.g., 80 (X), 84 (Y) */
294 /* 0x02a0 ~ 0x02bc - Motion Vector for 2nd 4x4 Block, e.g., A0 (X), A4 (Y) */
296 /* 0x02c0 ~ 0x02dc - Motion Vector for 3rd 4x4 Block, e.g., C0 (X), C4 (Y) */
298 /* 0x02e0 ~ 0x02fc - Motion Vector for 4th 4x4 Block, e.g., E0 (X), E4 (Y) */
311 * [6:4]
312 * 0x5 Only 4x4
314 * 0x7 16x16 & 4x4
317 #define TW5864_DSP_INTRA_MODE_SHIFT 4
318 #define TW5864_DSP_INTRA_MODE_MASK (7 << 4)
336 /* 0x0800 ~ 0x09ff - Quantization TABLE Values */
341 (0x0c00 | (channel << 4) | (frame << 2))
345 * 1 Progressive in part A in bus n
350 * 1 Progressive in part B in bus n
353 #define TW5864_PROG_B BIT(1)
355 * 1 Frame Mode in bus n
360 * 0 4CIF in bus n
361 * 1 1D1 + 4 CIF in bus n
365 /* Bus 1 goes in TW5864_FRAME_BUS1 in [4:0] */
368 /* Bus 3 goes in TW5864_FRAME_BUS2 in [4:0] */
369 /* Bus 4 goes in TW5864_FRAME_BUS2 in [12:8] */
378 * 0x15f: 4 CIF
379 * 0x2cf: 1 D1 + 3 CIF
382 * 0x15f: 4 CIF
383 * 0x2cf: 1 D1 + 3 CIF
386 * 0x11f: 4CIF (PAL)
387 * 0x23f: 1D1 + 3CIF (PAL)
389 * 0x0ef: 4CIF (NTSC)
390 * 0x1df: 1D1 + 3CIF (NTSC)
393 * 0x11f: 4CIF (PAL)
394 * 0x23f: 1D1 + 3CIF (PAL)
396 * 0x0ef: 4CIF (NTSC)
397 * 0x1df: 1D1 + 3CIF (NTSC)
406 * 1: the bus mapped Channel n Full D1
413 * 1 The bus mapped Channel select partB Mode
422 * Swap byte order of VLC stream in d-word.
423 * 1 Normal (VLC output= [31:0])
429 /* Number of bit for VLC bit Align */
434 * 1 CDC_VLCS_MAS read VLC stream
441 * 1 PCI Master Mode
447 * 1 Disable Adding 03 to VLC header of "00000001"
451 * Status of VLC stream in DDR (one bit for each buffer)
452 * 1 VLC is ready in buffer n (HW set)
458 /* Total number of bit in the slice */
460 /* Total number of bit in the residue */
465 /* VLC BK0 full status, write '1' to clear */
467 /* VLC BK1 full status, write '1' to clear */
468 #define TW5864_VLC_BK1_FULL BIT(1)
469 /* VLC end slice status, write '1' to clear */
471 /* VLC Buffer overflow status, write '1' to clear */
473 /* VLC string length in either buffer 0 or 1 at end of frame */
474 #define TW5864_VLC_STREAM_LEN_SHIFT 4
475 #define TW5864_VLC_STREAM_LEN_MASK (0x1ff << 4)
479 /* [0] VLC Encoder Interrupt. Write '1' to clear */
487 * 1 Read VLC lookup Memory
492 * 1 Read VLC Stream Memory in burst mode
495 #define TW5864_VLC_RD_BRST BIT(1)
497 /* 0x2000 ~ 0x2ffc - H264 Stream Memory Map */
499 * A word is 4 bytes. I.e.,
501 * VLC_STREAM_MEM[1] address: 0x2004
507 #define TW5864_VLC_STREAM_MEM(offset) (TW5864_VLC_STREAM_MEM_START + 4 * offset)
509 /* 0x4000 ~ 0x4ffc - Audio Register Map */
510 /* [31:0] config 1ms cnt = Realtime clk/1000 */
518 #define TW5864_ADPCM_IN_DATA BIT(1)
530 * 1 8bit
542 * 1 16K
552 * 1 PCI Initiator Mode
598 /* [3:0] rd ch0, [7:4] rd ch1, [11:8] wr ch0, [15:12] wr ch1 */
604 * Bit[7:4] ch1
642 * or ADPCM(1) audio data sent to PC. One bit for each channel
649 * 1 Flow control enabled
658 /* [1:0] CS valid to data valid CLK cycles when writing operation */
667 * 1 vlc stream to ddr buffers
672 * 1 SYNC Address sampled on Falling edge
675 #define TW5864_VLC_STR_DELAY_SHIFT 1
678 * 1 One system clock delay
682 #define TW5864_VLC_STR_DELAY (3 << 1)
685 * 1 Falling edge output
690 * [1:0]
699 * The system / DDR clock (166 MHz) is generated with an on-chip system clock
700 * PLL (SYSPLL) using input crystal clock of 27 MHz. The system clock PLL
702 * CLK_OUT = CLK_IN * (M+1) / ((N+1) * P)
712 /* [2:0]: SYSPLL_M[10:8], [7:3]: SYSPLL_N[4:0] */
720 * [1:0]: SYSPLL_N[6:5], [3:2]: SYSPLL_P, [4]: SYSPLL_IREF, [7:5]: SYSPLL_CP_SEL
730 * 1 30% higher current
732 #define TW5864_SYSPLL_IREF BIT(4)
735 * 0 1,5 uA
736 * 1 4 uA
739 * 4 39 uA
748 * [1:0]: SYSPLL_VCO, [3:2]: SYSPLL_LP_X8, [5:4]: SYSPLL_ICP_SEL,
765 * 1 6.6K ohms (default)
770 #define TW5864_SYSPLL_ICP_SEL_SHIFT 4
778 #define TW5864_SYSPLL_ICP_SEL (0x03 << 4)
782 * 1 5pF added
788 * 1 Rising edge
792 /* [0]: SYSPLL_RST, [4]: SYSPLL_PD */
798 #define TW5864_SYSPLL_PD BIT(4)
805 * LOAD register bit is also set to 1.
811 * LOAD register bit is also set to 1.
817 * the LOAD register bit is also set to 1.
819 #define TW5864_SPLL_CFG BIT(4)
829 /* 0x8800 ~ 0x88fc - Interrupt Register Map */
831 * Trigger mode of interrupt source 0 ~ 15
832 * 1 Edge trigger mode
836 /* Trigger mode of interrupt source 16 ~ 31 */
838 /* Enable of interrupt source 0 ~ 15 */
840 /* Enable of interrupt source 16 ~ 31 */
842 /* Clear interrupt command of interrupt source 0 ~ 15 */
844 /* Clear interrupt command of interrupt source 16 ~ 31 */
847 * Assertion of interrupt source 0 ~ 15
848 * 1 High level or pos-edge is assertion
849 * 0 Low level or neg-edge is assertion
852 /* Assertion of interrupt source 16 ~ 31 */
855 * Output level of interrupt
856 * 1 Interrupt output is high assertion
861 * Status of interrupt source 0 ~ 15
862 * Bit[0]: VLC 4k RAM interrupt
863 * Bit[1]: BURST DDR RAM interrupt
866 * Bit[4]: gpio 0 interrupt
867 * Bit[5]: gpio 1 interrupt
870 * Bit[8]: gpio 4 interrupt
879 * Status of interrupt source 16 ~ 31
881 * Bit[1]: VLC done interrupt
884 * Bit[4]: Preview eof interrupt
895 /* Defines of interrupt bits, united for both low and high word registers */
897 #define TW5864_INTR_BURST BIT(1)
901 #define TW5864_INTR_GPIO(n) (1 << (4 + n))
912 /* 0x9000 ~ 0x920c - Video Capture (VIF) Register Map */
914 * H264EN_CH_STATUS[n] Status of Vsync synchronized H264EN_CH_EN (Read Only)
915 * 1 Channel Enabled
921 * 1 Channel Enabled
928 * 1 Downscale Y to 1/2
934 * 1 Progressive (Not valid for TW5864)
940 * H264 Encoding Path maximum number of channel on BUS n
941 * 0 Max 4 channels
942 * 1 Max 2 channels
954 * [4:0] H264EN_RATE_MAX_LINE_0
959 * [4:0] H264EN_RATE_MAX_LINE_2
965 * H264EN_CHn_FMT H264 Encoding Path Format configuration of Channel n
969 * 11 D1 with 1/2 size in X (for CIF frame)
973 * [1:0]: H264EN_CH0_FMT,
978 * [1:0]: H264EN_CH8_FMT (?),
992 * H264EN_BUSm_MAP_CHn The 16-to-1 MUX configuration register for each encoding
993 * channel (total of 16 channels). Four bits for each channel.
1006 /* GPIO DATA of Group n */
1009 /* GPIO Output Enable of Group n */
1012 /* 0xa000 ~ 0xa8ff - DDR Controller Register Map */
1024 * Tras value, the minimum cycle of active to precharge command period,
1029 * Trfc value, the minimum cycle of refresh to active or refresh command period,
1030 * default is 4"hf
1035 * Trcd value, the minimum cycle of active to internal read/write command
1036 * period, default is 4"h2
1038 #define TW5864_TCD_CNT_MAX_SHIFT 4
1039 #define TW5864_TCD_CNT_MAX (0x0f << 4)
1040 /* Twr value, write recovery time, default is 4"h3 */
1046 * availability of the first bit of output data, default is 3
1055 * DDR_ON_CHIP_MAP [1:0]
1057 * 1 512M DDR on board
1058 * 2 1G DDR on board
1061 * 1 Two DDR chips
1068 * 1 DDR self-test mode
1072 * 0 DDR self-test single read/write
1073 * 1 DDR self-test burst read/write
1075 #define TW5864_SINGLE_PROC BIT(1)
1077 * 0 DDR self-test write command
1078 * 1 DDR self-test read command
1081 #define TW5864_DATA_MODE_SHIFT 4
1084 * 1 write 32'hffffffff to DDR
1088 #define TW5864_DATA_MODE (0x3 << 4)
1090 /* [7:0] The maximum data of one burst in DDR self-test mode */
1092 /* [15:0] The maximum burst counter (bit 15~0) in DDR self-test mode */
1094 /* The maximum burst counter (bit 31~16) in DDR self-test mode */
1096 /* [0]: Start one DDR self-test */
1098 /* The maximum error counter (bit 15 ~ 0) in DDR self-test */
1103 /* The maximum error counter (bit 30 ~ 16) in DDR self-test */
1105 /* DDR self-test end flag */
1114 /* 0xb004 ~ 0xb018 - HW version/ARB12 Register Map */
1120 /* Audio data in to DDR enable (default 1) */
1122 /* Audio encode request to DDR enable (default 1) */
1123 #define TW5864_AUD_ENC_REQ_ENB BIT(1)
1124 /* Audio decode request0 to DDR enable (default 1) */
1126 /* Audio decode request1 to DDR enable (default 1) */
1128 /* VLC stream request to DDR enable (default 1) */
1129 #define TW5864_VLC_STRM_REQ_ENB BIT(4)
1130 /* H264 MV request to DDR enable (default 1) */
1132 /* mux_core MVD request to DDR enable (default 1) */
1134 /* mux_core MVD temp data request to DDR enable (default 1) */
1136 /* JPEG request to DDR enable (default 1) */
1138 /* mv_flag request to DDR enable (default 1) */
1143 /* ARB12 Enable (default 1) */
1145 /* ARB12 maximum value of time out counter (default 15"h1FF) */
1148 /* 0xb800 ~ 0xb80c - Indirect Access Register Map */
1157 * (1) Write IND_DATA at 0xb804 ~ 0xb807
1159 * (3) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "1", ENABLE to "1"
1161 * (1) Read BUSY flag from 0xb803. Wait until BUSY signal is 0.
1162 * (2) Write IND_ADDR at 0xb800 ~ 0xb801. Set R/W to "0", ENABLE to "1"
1164 * (4) Read IND_DATA from 0xb804 ~ 0xb807
1180 /* 0xc000 ~ 0xc7fc - Preview Register Map */
1183 * [15:0] Status of Vsync Synchronized PCI_PV_CH_EN (Read Only)
1184 * 1 Channel Enabled
1190 * 1 Channel Enable
1195 /* 0xc800 ~ 0xc804 - JPEG Capture Register Map */
1197 /* 0xd000 ~ 0xd0fc - JPEG Control Register Map */
1200 /* 0xe000 ~ 0xfc04 - Motion Vector Register Map */
1205 #define TW5864_ME_MV_VEC(offset) (TW5864_ME_MV_VEC_START + 4 * offset)
1209 /* mv bank0 full status , write "1" to clear */
1211 /* mv bank1 full status , write "1" to clear */
1212 #define TW5864_MV_BK1_FULL BIT(1)
1213 /* slice end status; write "1" to clear */
1215 /* mv encode interrupt status; write "1" to clear */
1217 /* mv write memory overflow, write "1" to clear */
1218 #define TW5864_DSP_WR_OF BIT(4)
1222 /* The configured status bit written into bit 15 of 0xfc04 */
1230 * 1 MV is saved in DDR
1234 /* 0x18000 ~ 0x181fc - PCI Master/Slave Control Map */
1238 #define TW5864_VLC_DONE_INTR BIT(1)
1242 #define TW5864_PREV_EOF_INTR BIT(4)
1263 #define TW5864_PREV_MAST_ENB BIT(4)
1281 /* ddr burst enable (1 enable, and must set DDR_BRST_EN) */
1287 * interrupt status register. OR operating of the PREV_INTR_REG is
1288 * PREV_EOF_INTR, OR operating of the AU_INTR_REG bits is AUDIO_EOF_INTR
1301 #define TW5864_PCI_VLC_INTR_ENB BIT(1)
1303 #define TW5864_PCI_PREV_INTR_ENB BIT(4)
1312 * Every channel of preview and audio have ping-pong buffers in system memory,
1331 /* rd/wr flag rd=1,wr=0 */
1338 * bit to 1. Then poll this bit, value 1 indicate iic transaction have
1358 /* vlc length of one frame */
1374 * Configuration register for 9[or 10] CIFs or 1D1+15QCIF Preview mode.
1375 * PREV_PCI_ENB_CHN[0] Enable 9th preview channel (9CIF prev) or 1D1 channel in
1376 * (1D1+15QCIF prev)
1377 * PREV_PCI_ENB_CHN[1] Enable 10th preview channel
1386 * 0 1ms
1387 * 1 2ms
1388 * 2 4ms
1407 /* 0x80000 ~ 0x87fff - DDR Burst RW Register Map */
1411 /* Length of 32-bit data burst */
1416 * 1 Write Burst to DDR
1427 /* Enable Interrupt for End of DDR Burst Access */
1438 /* [27:0] DDR Access Address. Bit [1:0] has to be 0 */
1440 /* DDR Access Internal Buffer Address. Bit [1:0] has to be 0 */
1444 /* 0x84000 - 0x87ffc */
1454 /* Read-only register */
1458 * 1 Video not present. (sync is not detected in number of consecutive line
1464 * 1 Horizontal sync PLL is locked to the incoming video source.
1469 * 1 Sub-carrier PLL is locked to the incoming video source.
1470 * 0 Sub-carrier PLL is not locked.
1474 * 1 Even field is being decoded.
1477 #define TW5864_INDIR_VIN_0_FLD BIT(4)
1479 * 1 Vertical logic is locked to the incoming video source.
1484 * 1 No color burst signal detected.
1487 #define TW5864_INDIR_VIN_0_MONO BIT(1)
1490 * 1 50Hz source detected
1497 /* VCR signal indicator. Read-only. */
1499 /* Weak signal indicator 2. Read-only. */
1501 /* Weak signal indicator controlled by WKTH. Read-only. */
1504 * 1 = Standard signal
1505 * 0 = Non-standard signal
1506 * Read-only
1508 #define TW5864_INDIR_VIN_1_VSTD BIT(4)
1510 * 1 = Non-interlaced signal
1512 * Read-only
1537 #define TW5864_INDIR_VIN_6_VDELAY_XY_HI BIT(4)
1541 * HDELAY_XY This 10bit register defines the starting location of horizontal
1542 * active pixel for display / record path. A unit is 1 pixel. The default value
1545 * HACTIVE_XY This 10bit register defines the number of horizontal active pixel
1546 * for display / record path. A unit is 1 pixel. The default value is decimal
1549 * VDELAY_XY This 9bit register defines the starting location of vertical
1550 * active for display / record path. A unit is 1 line. The default value is
1553 * VACTIVE_XY This 9bit register defines the number of vertical active lines
1554 * for display / record path. A unit is 1 line. The default value is decimal
1559 * value from +36o (7Fh) to -36o (80h) with an increment of 2.8o. The 2 LSB has
1569 * This bit controls the center frequency of the peaking filter.
1572 * 1 center
1575 /* CTI level selection. The default is 1.
1579 #define TW5864_INDIR_VIN_8_CTI_SHIFT 4
1580 #define TW5864_INDIR_VIN_8_CTI (0x03 << 4)
1583 * These bits control the amount of sharpness enhancement on the luminance
1584 * signals. There are 16 levels of control with "0" having no effect on the
1585 * output image. 1 through 15 provides sharpness enhancement with "F" being the
1586 * strongest. The default is 1.
1591 * These bits control the luminance contrast gain. A value of 100 (64h) has a
1592 * gain of 1. The range adjustment is from 0% to 255% at 1% per step. The
1598 * These bits control the brightness. They have value of -128 to 127 in 2's
1605 * These bits control the digital gain adjustment to the U (or Cb) component of
1609 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1610 * gain of 100%. The default is 80h.
1615 * These bits control the digital gain adjustment to the V (or Cr) component of
1619 * flexibility. The range of adjustment is 0 to 200%. A value of 128 (80h) has
1620 * gain of 100%. The default is 80h.
1624 /* Read-only */
1627 /* Macrovision color stripe detection may be un-reliable */
1632 #define TW5864_INDIR_VIN_D_CSTRIPE BIT(1)
1635 * CSTRIPE=1,
1636 * 1 Type 2 color stripe protection
1641 /* Read-only */
1645 * Read-only.
1647 * 1 Detection in progress
1653 * 1 PAL (B, D, G, H, I)
1656 * 4 PAL (M)
1661 #define TW5864_INDIR_VIN_E_STDNOW_SHIFT 4
1662 #define TW5864_INDIR_VIN_E_STDNOW (0x07 << 4)
1665 * 1 Disable the shadow registers
1673 * 1 PAL (B, D, G, H, I)
1676 * 4 PAL (M)
1686 * 1 Writing 1 to this bit will manually initiate the auto format detection
1687 * process. This bit is a self-clearing bit
1688 * 0 Manual initiation of auto format detection is done. (Default)
1691 /* Enable recognition of PAL60 (Default) */
1693 /* Enable recognition of PAL (CN). (Default) */
1695 /* Enable recognition of PAL (M). (Default) */
1696 #define TW5864_INDIR_VIN_F_PALMEN BIT(4)
1697 /* Enable recognition of NTSC 4.43. (Default) */
1699 /* Enable recognition of SECAM. (Default) */
1701 /* Enable recognition of PAL (B, D, G, H, I). (Default) */
1702 #define TW5864_INDIR_VIN_F_PALBEN BIT(1)
1703 /* Enable recognition of NTSC (M). (Default) */
1708 /* Use falling edge to sample VD1-VD4 from 54 MHz to 108 MHz */
1711 #define TW5864_INDIR_VD_108_POL_VD34 BIT(1)
1720 * 1 0.31
1723 * 4 0.50
1736 /* [3:0] channel 0, [7:4] channel 1 */
1738 /* [3:0] channel 2, [7:4] channel 3 */
1746 * LAWMD Select u-Law/A-Law/PCM/SB data output format on ADATR and ADATM pin.
1748 * 1 SB (Signed MSB bit in PCM data is inverted) output
1749 * 2 u-Law output
1750 * 3 A-Law output
1757 * 1 Apply nominal value for all audio commonly
1762 * only for mixing. When n = 4, it enable the mute function of the playback
1765 * 1 Muted (default)
1774 * ADATP signal is coming from external ADPCM decoder, instead of on-chip ADPCM
1783 * 1 Inversed
1789 * 1 Inversed
1791 #define TW5864_INDIR_AIN_0x0E3_ACLKPPOLI BIT(4)
1794 * This mode is only effective when ACLKRMASTER=1
1796 * 1 ACKI control is automatically set up by AFMD register values
1802 * 1 16kHz setting
1805 * 4 48kHz setting
1814 * 1 One continuous packed output equal to DSP output format.
1820 * 1 Almost duty 50-50% clock output on ACLKR pin. If this mode is selected, two
1822 * AFAUTO=1, ACKI control is automatically set up even if MASCKMD=1.
1825 /* Playback ACLKP/ASYNP/ADATP input data MSB-LSB swapping */
1830 * 1 Add one 27MHz period delay in ASYNR signal input
1832 #define TW5864_INDIR_AIN_0x0E4_ASYNRDLY BIT(4)
1836 * 1 add one 27MHz period delay in ASYNP signal input
1841 * 0 No delay (Default). This is for I2S type 1T delay input interface.
1842 * 1 Add 1 ACLKP clock delay in ADATP input data. This is for left-justified
1847 * Select u-Law/A-Law/PCM/SB data input format on ADATP pin.
1849 * 1 SB (Signed MSB bit in PCM data is inverted) input
1850 * 2 u-Law input
1851 * 3 A-Law input
1856 * Enable state register updating and interrupt request of audio AIN5 detection
1869 #define TW5864_INDIR_IN_PIC_WIDTH(channel) (0x200 + 4 * channel)
1870 #define TW5864_INDIR_IN_PIC_HEIGHT(channel) (0x201 + 4 * channel)
1871 #define TW5864_INDIR_OUT_PIC_WIDTH(channel) (0x202 + 4 * channel)
1872 #define TW5864_INDIR_OUT_PIC_HEIGHT(channel) (0x203 + 4 * channel)
1882 * Interrupt status register from the front-end. Write "1" to each bit to clear
1913 * bit 1: interrupt occurs in 0x2d1 & 0x2d9
1916 * bit 4: interrupt occurs in 0x2d4 & 0x2dc
1934 * 1 Disable motion and blind detection
1940 * 1 Request to start motion detection
1944 * Select the trigger mode of motion detection
1945 * 0 Automatic trigger mode of motion detection (default)
1946 * 1 Manual trigger mode for motion detection
1950 * Define the threshold of cell for blind detection.
1960 * Control the temporal sensitivity of motion detector.
1965 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS_SHIFT 4
1966 #define TW5864_INDIR_DETECTION_CTL1_MD_TMPSENS (0x0f << 4)
1978 * Control the updating time of reference field for motion detection.
1980 * 1 Update reference field according to MD_SPEED
1986 * 1 Detecting motion for only even field
1993 * Control the level sensitivity of motion detector.
2003 * Define the threshold of sub-cell number for motion detection.
2004 * 0 Motion is detected if 1 sub-cell has motion (More sensitive) (default)
2005 * 1 Motion is detected if 2 sub-cells have motion
2006 * 2 Motion is detected if 3 sub-cells have motion
2007 * 3 Motion is detected if 4 sub-cells have motion (Less sensitive)
2012 * Control the velocity of motion detector.
2014 * In MD_DUAL_EN = 1, MD_SPEED should be limited to 0 ~ 31.
2015 * 0 1 field intervals (default)
2016 * 1 2 field intervals
2027 * Control the spatial sensitivity of motion detector.
2032 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS_SHIFT 4
2033 #define TW5864_INDIR_DETECTION_CTL4_MD_SPSENS (0x0f << 4)
2035 * Define the threshold of level for blind detection.
2044 * Define the threshold of temporal sensitivity for night detection.
2049 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS_SHIFT 4
2050 #define TW5864_INDIR_DETECTION_CTL5_ND_TMPSENS (0x0f << 4)
2052 * Define the threshold of level for night detection.
2060 * [11:0] The base address of the motion detection buffer. This address is in
2061 * unit of 64K bytes. The generated DDR address will be {MD_BASE_ADDR,
2067 * This controls the channel of the motion detection result shown in register
2083 /* 192 bit motion flag of the channel specified by RGR_MOTION_SEL in 0x382 */
2088 * [9:0] The motion cell count of a specific channel selected by 0x382. This is
2097 /* 192 bit motion mask of the channel specified by MASK_CH_SEL in 0x3fe */
2101 /* [4:0] The channel selection to access masks in 0x3e0 ~ 0x3f7 */
2124 #define TW5864_INDIR_PV_VD_CK_POL_VD(channel) BIT(channel + 4)
2131 #define TW5864_INDIR_CLK0_SEL_PV2_SHIFT 4
2132 #define TW5864_INDIR_CLK0_SEL_PV2_MASK (0x3 << 4)