Lines Matching +full:com +full:- +full:mode
1 // SPDX-License-Identifier: GPL-2.0-only
5 * Copyright (C) 2005-2007 Micronas
7 * Copyright (C) 2008-2009 Ralph Metzler <rjkm@metzlerbros.de>
9 * support for EEPROM-copying,
10 * support for new dual DVB-S2 card prototype
41 #define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr))
42 #define ngwritel(dat, adr) writel((dat), dev->iomem + (adr))
43 #define ngwriteb(dat, adr) writeb((dat), dev->iomem + (adr))
44 #define ngreadl(adr) readl(dev->iomem + (adr))
45 #define ngreadb(adr) readb(dev->iomem + (adr))
46 #define ngcpyto(adr, src, count) memcpy_toio(dev->iomem + (adr), (src), (count))
47 #define ngcpyfrom(dst, adr, count) memcpy_fromio((dst), dev->iomem + (adr), (count))
57 while (dev->EventQueueReadIndex != dev->EventQueueWriteIndex) { in event_tasklet()
59 dev->EventQueue[dev->EventQueueReadIndex]; in event_tasklet()
60 dev->EventQueueReadIndex = in event_tasklet()
61 (dev->EventQueueReadIndex + 1) & (EVENT_QUEUE_SIZE - 1); in event_tasklet()
63 if ((Event.UARTStatus & 0x01) && (dev->TxEventNotify)) in event_tasklet()
64 dev->TxEventNotify(dev, Event.TimeStamp); in event_tasklet()
65 if ((Event.UARTStatus & 0x02) && (dev->RxEventNotify)) in event_tasklet()
66 dev->RxEventNotify(dev, Event.TimeStamp, in event_tasklet()
74 struct device *pdev = &chan->dev->pci_dev->dev; in demux_tasklet()
75 struct SBufferHeader *Cur = chan->nextBuffer; in demux_tasklet()
77 spin_lock_irq(&chan->state_lock); in demux_tasklet()
79 while (Cur->ngeneBuffer.SR.Flags & 0x80) { in demux_tasklet()
80 if (chan->mode & NGENE_IO_TSOUT) { in demux_tasklet()
81 u32 Flags = chan->DataFormatFlags; in demux_tasklet()
82 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_tasklet()
84 if (chan->pBufferExchange) { in demux_tasklet()
85 if (!chan->pBufferExchange(chan, in demux_tasklet()
86 Cur->Buffer1, in demux_tasklet()
87 chan->Capture1Length, in demux_tasklet()
88 Cur->ngeneBuffer.SR. in demux_tasklet()
101 if (chan->HWState == HWSTATE_RUN) { in demux_tasklet()
102 Cur->ngeneBuffer.SR.Flags &= in demux_tasklet()
110 chan->HWState = HWSTATE_RUN; in demux_tasklet()
114 if (chan->HWState == HWSTATE_RUN) { in demux_tasklet()
115 Cur->ngeneBuffer.SR.Flags &= ~0x40; in demux_tasklet()
119 if (chan->AudioDTOUpdated) { in demux_tasklet()
121 chan->AudioDTOValue); in demux_tasklet()
122 Cur->ngeneBuffer.SR.DTOUpdate = in demux_tasklet()
123 chan->AudioDTOValue; in demux_tasklet()
124 chan->AudioDTOUpdated = 0; in demux_tasklet()
127 if (chan->HWState == HWSTATE_RUN) { in demux_tasklet()
128 u32 Flags = chan->DataFormatFlags; in demux_tasklet()
129 IBufferExchange *exch1 = chan->pBufferExchange; in demux_tasklet()
130 IBufferExchange *exch2 = chan->pBufferExchange2; in demux_tasklet()
131 if (Cur->ngeneBuffer.SR.Flags & 0x01) in demux_tasklet()
133 if (Cur->ngeneBuffer.SR.Flags & 0x20) in demux_tasklet()
135 spin_unlock_irq(&chan->state_lock); in demux_tasklet()
137 exch1(chan, Cur->Buffer1, in demux_tasklet()
138 chan->Capture1Length, in demux_tasklet()
139 Cur->ngeneBuffer.SR.Clock, in demux_tasklet()
142 exch2(chan, Cur->Buffer2, in demux_tasklet()
143 chan->Capture2Length, in demux_tasklet()
144 Cur->ngeneBuffer.SR.Clock, in demux_tasklet()
146 spin_lock_irq(&chan->state_lock); in demux_tasklet()
147 } else if (chan->HWState != HWSTATE_STOP) in demux_tasklet()
148 chan->HWState = HWSTATE_RUN; in demux_tasklet()
150 Cur->ngeneBuffer.SR.Flags = 0x00; in demux_tasklet()
151 Cur = Cur->Next; in demux_tasklet()
153 chan->nextBuffer = Cur; in demux_tasklet()
155 spin_unlock_irq(&chan->state_lock); in demux_tasklet()
161 struct device *pdev = &dev->pci_dev->dev; in irq_handler()
167 if (dev->BootFirmware) { in irq_handler()
169 if (icounts != dev->icounts) { in irq_handler()
171 dev->cmd_done = 1; in irq_handler()
172 wake_up(&dev->cmd_wq); in irq_handler()
173 dev->icounts = icounts; in irq_handler()
181 spin_lock(&dev->cmd_lock); in irq_handler()
182 tmpCmdDoneByte = dev->CmdDoneByte; in irq_handler()
185 (dev->ngenetohost[0] == 1 && dev->ngenetohost[1] != 0))) { in irq_handler()
186 dev->CmdDoneByte = NULL; in irq_handler()
187 dev->cmd_done = 1; in irq_handler()
188 wake_up(&dev->cmd_wq); in irq_handler()
191 spin_unlock(&dev->cmd_lock); in irq_handler()
193 if (dev->EventBuffer->EventStatus & 0x80) { in irq_handler()
195 (dev->EventQueueWriteIndex + 1) & in irq_handler()
196 (EVENT_QUEUE_SIZE - 1); in irq_handler()
197 if (nextWriteIndex != dev->EventQueueReadIndex) { in irq_handler()
198 dev->EventQueue[dev->EventQueueWriteIndex] = in irq_handler()
199 *(dev->EventBuffer); in irq_handler()
200 dev->EventQueueWriteIndex = nextWriteIndex; in irq_handler()
203 dev->EventQueueOverflowCount += 1; in irq_handler()
204 dev->EventQueueOverflowFlag = 1; in irq_handler()
206 dev->EventBuffer->EventStatus &= ~0x80; in irq_handler()
207 tasklet_schedule(&dev->event_tasklet); in irq_handler()
212 i--; in irq_handler()
213 spin_lock(&dev->channel[i].state_lock); in irq_handler()
214 /* if (dev->channel[i].State>=KSSTATE_RUN) { */ in irq_handler()
215 if (dev->channel[i].nextBuffer) { in irq_handler()
216 if ((dev->channel[i].nextBuffer-> in irq_handler()
218 dev->channel[i].nextBuffer-> in irq_handler()
221 &dev->channel[i].demux_tasklet); in irq_handler()
225 spin_unlock(&dev->channel[i].state_lock); in irq_handler()
238 struct device *pdev = &dev->pci_dev->dev; in dump_command_io()
247 b = dev->hosttongene; in dump_command_io()
248 dev_err(pdev, "dev->hosttongene (%p): %*ph\n", b, 8, b); in dump_command_io()
250 b = dev->ngenetohost; in dump_command_io()
251 dev_err(pdev, "dev->ngenetohost (%p): %*ph\n", b, 8, b); in dump_command_io()
254 static int ngene_command_mutex(struct ngene *dev, struct ngene_command *com) in ngene_command_mutex() argument
256 struct device *pdev = &dev->pci_dev->dev; in ngene_command_mutex()
260 dev->cmd_done = 0; in ngene_command_mutex()
262 if (com->cmd.hdr.Opcode == CMD_FWLOAD_PREPARE) { in ngene_command_mutex()
263 dev->BootFirmware = 1; in ngene_command_mutex()
264 dev->icounts = ngreadl(NGENE_INT_COUNTS); in ngene_command_mutex()
271 } else if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) { in ngene_command_mutex()
272 u64 fwio = dev->PAFWInterfaceBuffer; in ngene_command_mutex()
282 memcpy(dev->FWInterfaceBuffer, com->cmd.raw8, com->in_len + 2); in ngene_command_mutex()
284 if (dev->BootFirmware) in ngene_command_mutex()
285 ngcpyto(HOST_TO_NGENE, com->cmd.raw8, com->in_len + 2); in ngene_command_mutex()
287 spin_lock_irq(&dev->cmd_lock); in ngene_command_mutex()
288 tmpCmdDoneByte = dev->ngenetohost + com->out_len; in ngene_command_mutex()
289 if (!com->out_len) in ngene_command_mutex()
292 dev->ngenetohost[0] = 0; in ngene_command_mutex()
293 dev->ngenetohost[1] = 0; in ngene_command_mutex()
294 dev->CmdDoneByte = tmpCmdDoneByte; in ngene_command_mutex()
295 spin_unlock_irq(&dev->cmd_lock); in ngene_command_mutex()
300 ret = wait_event_timeout(dev->cmd_wq, dev->cmd_done == 1, 2 * HZ); in ngene_command_mutex()
305 com->cmd.hdr.Opcode, dev->prev_cmd); in ngene_command_mutex()
307 return -1; in ngene_command_mutex()
309 if (com->cmd.hdr.Opcode == CMD_FWLOAD_FINISH) in ngene_command_mutex()
310 dev->BootFirmware = 0; in ngene_command_mutex()
312 dev->prev_cmd = com->cmd.hdr.Opcode; in ngene_command_mutex()
314 if (!com->out_len) in ngene_command_mutex()
317 memcpy(com->cmd.raw8, dev->ngenetohost, com->out_len); in ngene_command_mutex()
322 int ngene_command(struct ngene *dev, struct ngene_command *com) in ngene_command() argument
326 mutex_lock(&dev->cmd_mutex); in ngene_command()
327 result = ngene_command_mutex(dev, com); in ngene_command()
328 mutex_unlock(&dev->cmd_mutex); in ngene_command()
338 struct ngene_command com; in ngene_command_load_firmware() local
340 com.cmd.hdr.Opcode = CMD_FWLOAD_PREPARE; in ngene_command_load_firmware()
341 com.cmd.hdr.Length = 0; in ngene_command_load_firmware()
342 com.in_len = 0; in ngene_command_load_firmware()
343 com.out_len = 0; in ngene_command_load_firmware()
345 ngene_command(dev, &com); in ngene_command_load_firmware()
350 cleft - FIRSTCHUNK); in ngene_command_load_firmware()
355 memset(&com, 0, sizeof(struct ngene_command)); in ngene_command_load_firmware()
356 com.cmd.hdr.Opcode = CMD_FWLOAD_FINISH; in ngene_command_load_firmware()
357 com.cmd.hdr.Length = 4; in ngene_command_load_firmware()
358 com.cmd.FWLoadFinish.Address = DATA_FIFO_AREA; in ngene_command_load_firmware()
359 com.cmd.FWLoadFinish.Length = (unsigned short)cleft; in ngene_command_load_firmware()
360 com.in_len = 4; in ngene_command_load_firmware()
361 com.out_len = 0; in ngene_command_load_firmware()
363 return ngene_command(dev, &com); in ngene_command_load_firmware()
369 struct ngene_command com; in ngene_command_config_buf() local
371 com.cmd.hdr.Opcode = CMD_CONFIGURE_BUFFER; in ngene_command_config_buf()
372 com.cmd.hdr.Length = 1; in ngene_command_config_buf()
373 com.cmd.ConfigureBuffers.config = config; in ngene_command_config_buf()
374 com.in_len = 1; in ngene_command_config_buf()
375 com.out_len = 0; in ngene_command_config_buf()
377 if (ngene_command(dev, &com) < 0) in ngene_command_config_buf()
378 return -EIO; in ngene_command_config_buf()
384 struct ngene_command com; in ngene_command_config_free_buf() local
386 com.cmd.hdr.Opcode = CMD_CONFIGURE_FREE_BUFFER; in ngene_command_config_free_buf()
387 com.cmd.hdr.Length = 6; in ngene_command_config_free_buf()
388 memcpy(&com.cmd.ConfigureFreeBuffers.config, config, 6); in ngene_command_config_free_buf()
389 com.in_len = 6; in ngene_command_config_free_buf()
390 com.out_len = 0; in ngene_command_config_free_buf()
392 if (ngene_command(dev, &com) < 0) in ngene_command_config_free_buf()
393 return -EIO; in ngene_command_config_free_buf()
400 struct ngene_command com; in ngene_command_gpio_set() local
402 com.cmd.hdr.Opcode = CMD_SET_GPIO_PIN; in ngene_command_gpio_set()
403 com.cmd.hdr.Length = 1; in ngene_command_gpio_set()
404 com.cmd.SetGpioPin.select = select | (level << 7); in ngene_command_gpio_set()
405 com.in_len = 1; in ngene_command_gpio_set()
406 com.out_len = 0; in ngene_command_gpio_set()
408 return ngene_command(dev, &com); in ngene_command_gpio_set()
419 6 0-AUX,1-TS
420 5 0-par,1-ser
421 4 0-lsb/1-msb
423 1,0 0-no sync, 1-use ext. start, 2-use 0x47, 3-both
424 1: FD_CTL2 has 3-valid must be hi, 2-use valid, 1-edge
425 2: FD_STA is read-only. 0-sync
428 5: FD_MAXBYTE1 is low-order of bytes per packet.
429 6: FD_MAXBYTE2 is high-order of bytes per packet.
453 /* Set NGENE I2S Config to transport stream compatible mode */
492 Length -= 188; in FillTSBuffer()
503 spin_lock_irq(&chan->state_lock); in flush_buffers()
504 val = chan->nextBuffer->ngeneBuffer.SR.Flags & 0x80; in flush_buffers()
505 spin_unlock_irq(&chan->state_lock); in flush_buffers()
511 struct SBufferHeader *Cur = chan->nextBuffer; in clear_buffers()
514 memset(&Cur->ngeneBuffer.SR, 0, sizeof(Cur->ngeneBuffer.SR)); in clear_buffers()
515 if (chan->mode & NGENE_IO_TSOUT) in clear_buffers()
516 FillTSBuffer(Cur->Buffer1, in clear_buffers()
517 chan->Capture1Length, in clear_buffers()
518 chan->DataFormatFlags); in clear_buffers()
519 Cur = Cur->Next; in clear_buffers()
520 } while (Cur != chan->nextBuffer); in clear_buffers()
522 if (chan->mode & NGENE_IO_TSOUT) { in clear_buffers()
523 chan->nextBuffer->ngeneBuffer.SR.DTOUpdate = in clear_buffers()
524 chan->AudioDTOValue; in clear_buffers()
525 chan->AudioDTOUpdated = 0; in clear_buffers()
527 Cur = chan->TSIdleBuffer.Head; in clear_buffers()
530 memset(&Cur->ngeneBuffer.SR, 0, in clear_buffers()
531 sizeof(Cur->ngeneBuffer.SR)); in clear_buffers()
532 FillTSBuffer(Cur->Buffer1, in clear_buffers()
533 chan->Capture1Length, in clear_buffers()
534 chan->DataFormatFlags); in clear_buffers()
535 Cur = Cur->Next; in clear_buffers()
536 } while (Cur != chan->TSIdleBuffer.Head); in clear_buffers()
541 u8 control, u8 mode, u8 flags) in ngene_command_stream_control() argument
543 struct device *pdev = &dev->pci_dev->dev; in ngene_command_stream_control()
544 struct ngene_channel *chan = &dev->channel[stream]; in ngene_command_stream_control()
545 struct ngene_command com; in ngene_command_stream_control() local
551 memset(&com, 0, sizeof(com)); in ngene_command_stream_control()
552 com.cmd.hdr.Opcode = CMD_CONTROL; in ngene_command_stream_control()
553 com.cmd.hdr.Length = sizeof(struct FW_STREAM_CONTROL) - 2; in ngene_command_stream_control()
554 com.cmd.StreamControl.Stream = stream | (control ? 8 : 0); in ngene_command_stream_control()
555 if (chan->mode & NGENE_IO_TSOUT) in ngene_command_stream_control()
556 com.cmd.StreamControl.Stream |= 0x07; in ngene_command_stream_control()
557 com.cmd.StreamControl.Control = control | in ngene_command_stream_control()
559 com.cmd.StreamControl.Mode = mode; in ngene_command_stream_control()
560 com.in_len = sizeof(struct FW_STREAM_CONTROL); in ngene_command_stream_control()
561 com.out_len = 0; in ngene_command_stream_control()
563 dev_dbg(pdev, "Stream=%02x, Control=%02x, Mode=%02x\n", in ngene_command_stream_control()
564 com.cmd.StreamControl.Stream, com.cmd.StreamControl.Control, in ngene_command_stream_control()
565 com.cmd.StreamControl.Mode); in ngene_command_stream_control()
567 chan->Mode = mode; in ngene_command_stream_control()
570 spin_lock_irq(&chan->state_lock); in ngene_command_stream_control()
571 if (chan->State == KSSTATE_RUN) { in ngene_command_stream_control()
572 chan->State = KSSTATE_ACQUIRE; in ngene_command_stream_control()
573 chan->HWState = HWSTATE_STOP; in ngene_command_stream_control()
574 spin_unlock_irq(&chan->state_lock); in ngene_command_stream_control()
575 if (ngene_command(dev, &com) < 0) in ngene_command_stream_control()
576 return -1; in ngene_command_stream_control()
581 spin_unlock_irq(&chan->state_lock); in ngene_command_stream_control()
585 if (mode & SMODE_AUDIO_CAPTURE) { in ngene_command_stream_control()
586 com.cmd.StreamControl.CaptureBlockCount = in ngene_command_stream_control()
587 chan->Capture1Length / AUDIO_BLOCK_SIZE; in ngene_command_stream_control()
588 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; in ngene_command_stream_control()
589 } else if (mode & SMODE_TRANSPORT_STREAM) { in ngene_command_stream_control()
590 com.cmd.StreamControl.CaptureBlockCount = in ngene_command_stream_control()
591 chan->Capture1Length / TS_BLOCK_SIZE; in ngene_command_stream_control()
592 com.cmd.StreamControl.MaxLinesPerField = in ngene_command_stream_control()
593 chan->Capture1Length / TS_BLOCK_SIZE; in ngene_command_stream_control()
594 com.cmd.StreamControl.Buffer_Address = in ngene_command_stream_control()
595 chan->TSRingBuffer.PAHead; in ngene_command_stream_control()
596 if (chan->mode & NGENE_IO_TSOUT) { in ngene_command_stream_control()
597 com.cmd.StreamControl.BytesPerVBILine = in ngene_command_stream_control()
598 chan->Capture1Length / TS_BLOCK_SIZE; in ngene_command_stream_control()
599 com.cmd.StreamControl.Stream |= 0x07; in ngene_command_stream_control()
602 com.cmd.StreamControl.BytesPerVideoLine = chan->nBytesPerLine; in ngene_command_stream_control()
603 com.cmd.StreamControl.MaxLinesPerField = chan->nLines; in ngene_command_stream_control()
604 com.cmd.StreamControl.MinLinesPerField = 100; in ngene_command_stream_control()
605 com.cmd.StreamControl.Buffer_Address = chan->RingBuffer.PAHead; in ngene_command_stream_control()
607 if (mode & SMODE_VBI_CAPTURE) { in ngene_command_stream_control()
608 com.cmd.StreamControl.MaxVBILinesPerField = in ngene_command_stream_control()
609 chan->nVBILines; in ngene_command_stream_control()
610 com.cmd.StreamControl.MinVBILinesPerField = 0; in ngene_command_stream_control()
611 com.cmd.StreamControl.BytesPerVBILine = in ngene_command_stream_control()
612 chan->nBytesPerVBILine; in ngene_command_stream_control()
615 com.cmd.StreamControl.Stream |= 0x04; in ngene_command_stream_control()
618 spin_lock_irq(&chan->state_lock); in ngene_command_stream_control()
619 if (mode & SMODE_AUDIO_CAPTURE) { in ngene_command_stream_control()
620 chan->nextBuffer = chan->RingBuffer.Head; in ngene_command_stream_control()
621 if (mode & SMODE_AUDIO_SPDIF) { in ngene_command_stream_control()
622 com.cmd.StreamControl.SetupDataLen = in ngene_command_stream_control()
624 com.cmd.StreamControl.SetupDataAddr = BsSPI; in ngene_command_stream_control()
625 memcpy(com.cmd.StreamControl.SetupData, in ngene_command_stream_control()
628 com.cmd.StreamControl.SetupDataLen = 4; in ngene_command_stream_control()
629 com.cmd.StreamControl.SetupDataAddr = BsSDI; in ngene_command_stream_control()
630 memcpy(com.cmd.StreamControl.SetupData, in ngene_command_stream_control()
632 4 * dev->card_info->i2s[stream], 4); in ngene_command_stream_control()
634 } else if (mode & SMODE_TRANSPORT_STREAM) { in ngene_command_stream_control()
635 chan->nextBuffer = chan->TSRingBuffer.Head; in ngene_command_stream_control()
637 if (chan->mode & NGENE_IO_TSOUT) { in ngene_command_stream_control()
638 com.cmd.StreamControl.SetupDataLen = in ngene_command_stream_control()
640 com.cmd.StreamControl.SetupDataAddr = BsSDO; in ngene_command_stream_control()
641 memcpy(com.cmd.StreamControl.SetupData, in ngene_command_stream_control()
645 com.cmd.StreamControl.SetupDataLen = in ngene_command_stream_control()
647 com.cmd.StreamControl.SetupDataAddr = BsSDI; in ngene_command_stream_control()
648 memcpy(com.cmd.StreamControl.SetupData, in ngene_command_stream_control()
653 com.cmd.StreamControl.SetupDataLen = 8; in ngene_command_stream_control()
654 com.cmd.StreamControl.SetupDataAddr = BsUVI + 0x10; in ngene_command_stream_control()
655 memcpy(com.cmd.StreamControl.SetupData, in ngene_command_stream_control()
657 8 * dev->card_info->tsf[stream], 8); in ngene_command_stream_control()
660 chan->nextBuffer = chan->RingBuffer.Head; in ngene_command_stream_control()
661 com.cmd.StreamControl.SetupDataLen = in ngene_command_stream_control()
663 com.cmd.StreamControl.SetupDataAddr = BsUVI; in ngene_command_stream_control()
664 memcpy(com.cmd.StreamControl.SetupData, in ngene_command_stream_control()
665 ITUDecoderSetup[chan->itumode], 16); in ngene_command_stream_control()
666 memcpy(com.cmd.StreamControl.SetupData + 16, in ngene_command_stream_control()
670 chan->State = KSSTATE_RUN; in ngene_command_stream_control()
671 if (mode & SMODE_TRANSPORT_STREAM) in ngene_command_stream_control()
672 chan->HWState = HWSTATE_RUN; in ngene_command_stream_control()
674 chan->HWState = HWSTATE_STARTUP; in ngene_command_stream_control()
675 spin_unlock_irq(&chan->state_lock); in ngene_command_stream_control()
677 if (ngene_command(dev, &com) < 0) in ngene_command_stream_control()
678 return -1; in ngene_command_stream_control()
685 struct device *pdev = &chan->dev->pci_dev->dev; in set_transfer()
686 u8 control = 0, mode = 0, flags = 0; in set_transfer() local
687 struct ngene *dev = chan->dev; in set_transfer()
696 if (chan->running) { in set_transfer()
701 if (!chan->running) { in set_transfer()
707 if (dev->card_info->switch_ctrl) in set_transfer()
708 dev->card_info->switch_ctrl(chan, 1, state ^ 1); in set_transfer()
711 spin_lock_irq(&chan->state_lock); in set_transfer()
715 dvb_ringbuffer_flush(&dev->tsout_rbuf); in set_transfer()
717 if (chan->mode & (NGENE_IO_TSIN | NGENE_IO_TSOUT)) { in set_transfer()
718 chan->Capture1Length = 512 * 188; in set_transfer()
719 mode = SMODE_TRANSPORT_STREAM; in set_transfer()
721 if (chan->mode & NGENE_IO_TSOUT) { in set_transfer()
722 chan->pBufferExchange = tsout_exchange; in set_transfer()
724 chan->AudioDTOValue = 0x80000000; in set_transfer()
725 chan->AudioDTOUpdated = 1; in set_transfer()
727 if (chan->mode & NGENE_IO_TSIN) in set_transfer()
728 chan->pBufferExchange = tsin_exchange; in set_transfer()
729 spin_unlock_irq(&chan->state_lock); in set_transfer()
734 mutex_lock(&dev->stream_mutex); in set_transfer()
735 ret = ngene_command_stream_control(dev, chan->number, in set_transfer()
736 control, mode, flags); in set_transfer()
737 mutex_unlock(&dev->stream_mutex); in set_transfer()
740 chan->running = state; in set_transfer()
744 spin_lock_irq(&chan->state_lock); in set_transfer()
745 chan->pBufferExchange = NULL; in set_transfer()
746 dvb_ringbuffer_flush(&dev->tsout_rbuf); in set_transfer()
747 spin_unlock_irq(&chan->state_lock); in set_transfer()
758 struct SBufferHeader *Cur = rb->Head; in free_ringbuffer()
764 for (j = 0; j < rb->NumBuffers; j++, Cur = Cur->Next) { in free_ringbuffer()
765 if (Cur->Buffer1) in free_ringbuffer()
766 dma_free_coherent(&dev->pci_dev->dev, in free_ringbuffer()
767 rb->Buffer1Length, Cur->Buffer1, in free_ringbuffer()
768 Cur->scList1->Address); in free_ringbuffer()
770 if (Cur->Buffer2) in free_ringbuffer()
771 dma_free_coherent(&dev->pci_dev->dev, in free_ringbuffer()
772 rb->Buffer2Length, Cur->Buffer2, in free_ringbuffer()
773 Cur->scList2->Address); in free_ringbuffer()
776 if (rb->SCListMem) in free_ringbuffer()
777 dma_free_coherent(&dev->pci_dev->dev, rb->SCListMemSize, in free_ringbuffer()
778 rb->SCListMem, rb->PASCListMem); in free_ringbuffer()
780 dma_free_coherent(&dev->pci_dev->dev, rb->MemSize, rb->Head, in free_ringbuffer()
781 rb->PAHead); in free_ringbuffer()
789 struct SBufferHeader *Cur = tb->Head; in free_idlebuffer()
791 if (!rb->Head) in free_idlebuffer()
794 for (j = 0; j < tb->NumBuffers; j++, Cur = Cur->Next) { in free_idlebuffer()
795 Cur->Buffer2 = NULL; in free_idlebuffer()
796 Cur->scList2 = NULL; in free_idlebuffer()
797 Cur->ngeneBuffer.Address_of_first_entry_2 = 0; in free_idlebuffer()
798 Cur->ngeneBuffer.Number_of_entries_2 = 0; in free_idlebuffer()
808 chan = &dev->channel[i]; in free_common_buffers()
809 free_idlebuffer(dev, &chan->TSIdleBuffer, &chan->TSRingBuffer); in free_common_buffers()
810 free_ringbuffer(dev, &chan->RingBuffer); in free_common_buffers()
811 free_ringbuffer(dev, &chan->TSRingBuffer); in free_common_buffers()
814 if (dev->OverflowBuffer) in free_common_buffers()
815 dma_free_coherent(&dev->pci_dev->dev, OVERFLOW_BUFFER_SIZE, in free_common_buffers()
816 dev->OverflowBuffer, dev->PAOverflowBuffer); in free_common_buffers()
818 if (dev->FWInterfaceBuffer) in free_common_buffers()
819 dma_free_coherent(&dev->pci_dev->dev, 4096, in free_common_buffers()
820 dev->FWInterfaceBuffer, in free_common_buffers()
821 dev->PAFWInterfaceBuffer); in free_common_buffers()
840 descr->Head = NULL; in create_ring_buffer()
841 descr->MemSize = 0; in create_ring_buffer()
842 descr->PAHead = 0; in create_ring_buffer()
843 descr->NumBuffers = 0; in create_ring_buffer()
848 Head = dma_alloc_coherent(&pci_dev->dev, MemSize, &tmp, GFP_KERNEL); in create_ring_buffer()
852 return -ENOMEM; in create_ring_buffer()
857 for (i = 0; i < NumBuffers - 1; i++) { in create_ring_buffer()
861 Cur->Next = Next; in create_ring_buffer()
862 Cur->ngeneBuffer.Next = PARingBufferNext; in create_ring_buffer()
867 Cur->Next = Head; in create_ring_buffer()
868 Cur->ngeneBuffer.Next = PARingBufferHead; in create_ring_buffer()
870 descr->Head = Head; in create_ring_buffer()
871 descr->MemSize = MemSize; in create_ring_buffer()
872 descr->PAHead = PARingBufferHead; in create_ring_buffer()
873 descr->NumBuffers = NumBuffers; in create_ring_buffer()
885 u32 SCListMemSize = pRingBuffer->NumBuffers in AllocateRingBuffers()
899 SCListMem = dma_alloc_coherent(&pci_dev->dev, SCListMemSize, &tmp, in AllocateRingBuffers()
904 return -ENOMEM; in AllocateRingBuffers()
906 pRingBuffer->SCListMem = SCListMem; in AllocateRingBuffers()
907 pRingBuffer->PASCListMem = PASCListMem; in AllocateRingBuffers()
908 pRingBuffer->SCListMemSize = SCListMemSize; in AllocateRingBuffers()
909 pRingBuffer->Buffer1Length = Buffer1Length; in AllocateRingBuffers()
910 pRingBuffer->Buffer2Length = Buffer2Length; in AllocateRingBuffers()
914 Cur = pRingBuffer->Head; in AllocateRingBuffers()
916 for (i = 0; i < pRingBuffer->NumBuffers; i += 1, Cur = Cur->Next) { in AllocateRingBuffers()
919 void *Buffer = dma_alloc_coherent(&pci_dev->dev, in AllocateRingBuffers()
924 return -ENOMEM; in AllocateRingBuffers()
926 Cur->Buffer1 = Buffer; in AllocateRingBuffers()
928 SCListEntry->Address = PABuffer; in AllocateRingBuffers()
929 SCListEntry->Length = Buffer1Length; in AllocateRingBuffers()
931 Cur->scList1 = SCListEntry; in AllocateRingBuffers()
932 Cur->ngeneBuffer.Address_of_first_entry_1 = PASCListEntry; in AllocateRingBuffers()
933 Cur->ngeneBuffer.Number_of_entries_1 = in AllocateRingBuffers()
940 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j += 1) { in AllocateRingBuffers()
941 SCListEntry->Address = of; in AllocateRingBuffers()
942 SCListEntry->Length = OVERFLOW_BUFFER_SIZE; in AllocateRingBuffers()
952 Buffer = dma_alloc_coherent(&pci_dev->dev, Buffer2Length, in AllocateRingBuffers()
957 return -ENOMEM; in AllocateRingBuffers()
959 Cur->Buffer2 = Buffer; in AllocateRingBuffers()
961 SCListEntry->Address = PABuffer; in AllocateRingBuffers()
962 SCListEntry->Length = Buffer2Length; in AllocateRingBuffers()
964 Cur->scList2 = SCListEntry; in AllocateRingBuffers()
965 Cur->ngeneBuffer.Address_of_first_entry_2 = PASCListEntry; in AllocateRingBuffers()
966 Cur->ngeneBuffer.Number_of_entries_2 = in AllocateRingBuffers()
973 for (j = 0; j < NUM_SCATTER_GATHER_ENTRIES - 1; j++) { in AllocateRingBuffers()
974 SCListEntry->Address = of; in AllocateRingBuffers()
975 SCListEntry->Length = OVERFLOW_BUFFER_SIZE; in AllocateRingBuffers()
994 u32 n = pRingBuffer->NumBuffers; in FillTSIdleBuffer()
997 struct SBufferHeader *Cur = pRingBuffer->Head; in FillTSIdleBuffer()
1001 Cur->Buffer2 = pIdleBuffer->Head->Buffer1; in FillTSIdleBuffer()
1002 Cur->scList2 = pIdleBuffer->Head->scList1; in FillTSIdleBuffer()
1003 Cur->ngeneBuffer.Address_of_first_entry_2 = in FillTSIdleBuffer()
1004 pIdleBuffer->Head->ngeneBuffer. in FillTSIdleBuffer()
1006 Cur->ngeneBuffer.Number_of_entries_2 = in FillTSIdleBuffer()
1007 pIdleBuffer->Head->ngeneBuffer.Number_of_entries_1; in FillTSIdleBuffer()
1008 Cur = Cur->Next; in FillTSIdleBuffer()
1042 dev->FWInterfaceBuffer = dma_alloc_coherent(&dev->pci_dev->dev, 4096, in AllocCommonBuffers()
1043 &dev->PAFWInterfaceBuffer, in AllocCommonBuffers()
1045 if (!dev->FWInterfaceBuffer) in AllocCommonBuffers()
1046 return -ENOMEM; in AllocCommonBuffers()
1047 dev->hosttongene = dev->FWInterfaceBuffer; in AllocCommonBuffers()
1048 dev->ngenetohost = dev->FWInterfaceBuffer + 256; in AllocCommonBuffers()
1049 dev->EventBuffer = dev->FWInterfaceBuffer + 512; in AllocCommonBuffers()
1051 dev->OverflowBuffer = dma_alloc_coherent(&dev->pci_dev->dev, in AllocCommonBuffers()
1053 &dev->PAOverflowBuffer, GFP_KERNEL); in AllocCommonBuffers()
1054 if (!dev->OverflowBuffer) in AllocCommonBuffers()
1055 return -ENOMEM; in AllocCommonBuffers()
1058 int type = dev->card_info->io_type[i]; in AllocCommonBuffers()
1060 dev->channel[i].State = KSSTATE_STOP; in AllocCommonBuffers()
1063 status = create_ring_buffer(dev->pci_dev, in AllocCommonBuffers()
1064 &dev->channel[i].RingBuffer, in AllocCommonBuffers()
1070 status = AllocateRingBuffers(dev->pci_dev, in AllocCommonBuffers()
1071 dev-> in AllocCommonBuffers()
1073 &dev->channel[i]. in AllocCommonBuffers()
1080 status = AllocateRingBuffers(dev->pci_dev, in AllocCommonBuffers()
1081 dev-> in AllocCommonBuffers()
1083 &dev->channel[i]. in AllocCommonBuffers()
1094 status = create_ring_buffer(dev->pci_dev, in AllocCommonBuffers()
1095 &dev->channel[i]. in AllocCommonBuffers()
1100 status = AllocateRingBuffers(dev->pci_dev, in AllocCommonBuffers()
1101 dev->PAOverflowBuffer, in AllocCommonBuffers()
1102 &dev->channel[i]. in AllocCommonBuffers()
1110 status = create_ring_buffer(dev->pci_dev, in AllocCommonBuffers()
1111 &dev->channel[i]. in AllocCommonBuffers()
1115 status = AllocateRingBuffers(dev->pci_dev, in AllocCommonBuffers()
1116 dev->PAOverflowBuffer, in AllocCommonBuffers()
1117 &dev->channel[i]. in AllocCommonBuffers()
1122 FillTSIdleBuffer(&dev->channel[i].TSIdleBuffer, in AllocCommonBuffers()
1123 &dev->channel[i].TSRingBuffer); in AllocCommonBuffers()
1131 if (dev->iomem) in ngene_release_buffers()
1132 iounmap(dev->iomem); in ngene_release_buffers()
1134 vfree(dev->tsout_buf); in ngene_release_buffers()
1135 vfree(dev->tsin_buf); in ngene_release_buffers()
1136 vfree(dev->ain_buf); in ngene_release_buffers()
1137 vfree(dev->vin_buf); in ngene_release_buffers()
1144 return -ENOMEM; in ngene_get_buffers()
1145 if (dev->card_info->io_type[4] & NGENE_IO_TSOUT) { in ngene_get_buffers()
1146 dev->tsout_buf = vmalloc(TSOUT_BUF_SIZE); in ngene_get_buffers()
1147 if (!dev->tsout_buf) in ngene_get_buffers()
1148 return -ENOMEM; in ngene_get_buffers()
1149 dvb_ringbuffer_init(&dev->tsout_rbuf, in ngene_get_buffers()
1150 dev->tsout_buf, TSOUT_BUF_SIZE); in ngene_get_buffers()
1152 if (dev->card_info->io_type[2]&NGENE_IO_TSIN) { in ngene_get_buffers()
1153 dev->tsin_buf = vmalloc(TSIN_BUF_SIZE); in ngene_get_buffers()
1154 if (!dev->tsin_buf) in ngene_get_buffers()
1155 return -ENOMEM; in ngene_get_buffers()
1156 dvb_ringbuffer_init(&dev->tsin_rbuf, in ngene_get_buffers()
1157 dev->tsin_buf, TSIN_BUF_SIZE); in ngene_get_buffers()
1159 if (dev->card_info->io_type[2] & NGENE_IO_AIN) { in ngene_get_buffers()
1160 dev->ain_buf = vmalloc(AIN_BUF_SIZE); in ngene_get_buffers()
1161 if (!dev->ain_buf) in ngene_get_buffers()
1162 return -ENOMEM; in ngene_get_buffers()
1163 dvb_ringbuffer_init(&dev->ain_rbuf, dev->ain_buf, AIN_BUF_SIZE); in ngene_get_buffers()
1165 if (dev->card_info->io_type[0] & NGENE_IO_HDTV) { in ngene_get_buffers()
1166 dev->vin_buf = vmalloc(VIN_BUF_SIZE); in ngene_get_buffers()
1167 if (!dev->vin_buf) in ngene_get_buffers()
1168 return -ENOMEM; in ngene_get_buffers()
1169 dvb_ringbuffer_init(&dev->vin_rbuf, dev->vin_buf, VIN_BUF_SIZE); in ngene_get_buffers()
1171 dev->iomem = ioremap(pci_resource_start(dev->pci_dev, 0), in ngene_get_buffers()
1172 pci_resource_len(dev->pci_dev, 0)); in ngene_get_buffers()
1173 if (!dev->iomem) in ngene_get_buffers()
1174 return -ENOMEM; in ngene_get_buffers()
1181 struct device *pdev = &dev->pci_dev->dev; in ngene_init()
1184 tasklet_setup(&dev->event_tasklet, event_tasklet); in ngene_init()
1186 memset_io(dev->iomem + 0xc000, 0x00, 0x220); in ngene_init()
1187 memset_io(dev->iomem + 0xc400, 0x00, 0x100); in ngene_init()
1190 dev->channel[i].dev = dev; in ngene_init()
1191 dev->channel[i].number = i; in ngene_init()
1194 dev->fw_interface_version = 0; in ngene_init()
1198 dev->icounts = ngreadl(NGENE_INT_COUNTS); in ngene_init()
1200 dev->device_version = ngreadl(DEV_VER) & 0x0f; in ngene_init()
1201 dev_info(pdev, "Device version %d\n", dev->device_version); in ngene_init()
1206 struct device *pdev = &dev->pci_dev->dev; in ngene_load_firm()
1213 version = dev->card_info->fw_version; in ngene_load_firm()
1221 dev->cmd_timeout_workaround = true; in ngene_load_firm()
1226 dev->cmd_timeout_workaround = true; in ngene_load_firm()
1231 dev->cmd_timeout_workaround = true; in ngene_load_firm()
1239 if (request_firmware(&fw, fw_name, &dev->pci_dev->dev) < 0) { in ngene_load_firm()
1243 return -1; in ngene_load_firm()
1246 size = fw->size; in ngene_load_firm()
1247 if (size != fw->size) { in ngene_load_firm()
1249 err = -1; in ngene_load_firm()
1252 ngene_fw = (u8 *) fw->data; in ngene_load_firm()
1263 mutex_destroy(&dev->cmd_mutex); in ngene_stop()
1264 i2c_del_adapter(&(dev->channel[0].i2c_adapter)); in ngene_stop()
1265 i2c_del_adapter(&(dev->channel[1].i2c_adapter)); in ngene_stop()
1273 free_irq(dev->pci_dev->irq, dev); in ngene_stop()
1275 if (dev->msi_enabled) in ngene_stop()
1276 pci_disable_msi(dev->pci_dev); in ngene_stop()
1284 if (dev->card_info->fw_version >= 17) { in ngene_buffer_config()
1290 if (dev->card_info->io_type[2]&NGENE_IO_TSIN && in ngene_buffer_config()
1291 dev->card_info->io_type[3]&NGENE_IO_TSIN) { in ngene_buffer_config()
1293 if (dev->card_info->io_type[4]&NGENE_IO_TSOUT && in ngene_buffer_config()
1294 dev->ci.en) in ngene_buffer_config()
1301 if (dev->card_info->io_type[3] == NGENE_IO_TSIN) in ngene_buffer_config()
1314 pci_set_master(dev->pci_dev); in ngene_start()
1317 stat = request_irq(dev->pci_dev->irq, irq_handler, in ngene_start()
1323 init_waitqueue_head(&dev->cmd_wq); in ngene_start()
1324 init_waitqueue_head(&dev->tx_wq); in ngene_start()
1325 init_waitqueue_head(&dev->rx_wq); in ngene_start()
1326 mutex_init(&dev->cmd_mutex); in ngene_start()
1327 mutex_init(&dev->stream_mutex); in ngene_start()
1328 sema_init(&dev->pll_mutex, 1); in ngene_start()
1329 mutex_init(&dev->i2c_switch_mutex); in ngene_start()
1330 spin_lock_init(&dev->cmd_lock); in ngene_start()
1332 spin_lock_init(&dev->channel[i].state_lock); in ngene_start()
1343 if (pci_msi_enabled() && dev->card_info->msi_supported) { in ngene_start()
1344 struct device *pdev = &dev->pci_dev->dev; in ngene_start()
1348 free_irq(dev->pci_dev->irq, dev); in ngene_start()
1349 stat = pci_enable_msi(dev->pci_dev); in ngene_start()
1355 dev->msi_enabled = true; in ngene_start()
1357 stat = request_irq(dev->pci_dev->irq, irq_handler, in ngene_start()
1377 free_irq(dev->pci_dev->irq, dev); in ngene_start()
1380 if (dev->msi_enabled) in ngene_start()
1381 pci_disable_msi(dev->pci_dev); in ngene_start()
1392 struct dvb_demux *dvbdemux = &chan->demux; in release_channel()
1393 struct ngene *dev = chan->dev; in release_channel()
1395 if (chan->running) in release_channel()
1398 tasklet_kill(&chan->demux_tasklet); in release_channel()
1400 if (chan->ci_dev) { in release_channel()
1401 dvb_unregister_device(chan->ci_dev); in release_channel()
1402 chan->ci_dev = NULL; in release_channel()
1405 if (chan->fe2) in release_channel()
1406 dvb_unregister_frontend(chan->fe2); in release_channel()
1408 if (chan->fe) { in release_channel()
1409 dvb_unregister_frontend(chan->fe); in release_channel()
1412 if (chan->i2c_client_fe) { in release_channel()
1413 dvb_module_release(chan->i2c_client[0]); in release_channel()
1414 chan->i2c_client[0] = NULL; in release_channel()
1417 dvb_frontend_detach(chan->fe); in release_channel()
1418 chan->fe = NULL; in release_channel()
1421 if (chan->has_demux) { in release_channel()
1422 dvb_net_release(&chan->dvbnet); in release_channel()
1423 dvbdemux->dmx.close(&dvbdemux->dmx); in release_channel()
1424 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, in release_channel()
1425 &chan->hw_frontend); in release_channel()
1426 dvbdemux->dmx.remove_frontend(&dvbdemux->dmx, in release_channel()
1427 &chan->mem_frontend); in release_channel()
1428 dvb_dmxdev_release(&chan->dmxdev); in release_channel()
1429 dvb_dmx_release(&chan->demux); in release_channel()
1430 chan->has_demux = false; in release_channel()
1433 if (chan->has_adapter) { in release_channel()
1434 dvb_unregister_adapter(&dev->adapter[chan->number]); in release_channel()
1435 chan->has_adapter = false; in release_channel()
1441 int ret = 0, nr = chan->number; in init_channel()
1443 struct dvb_demux *dvbdemux = &chan->demux; in init_channel()
1444 struct ngene *dev = chan->dev; in init_channel()
1445 struct ngene_info *ni = dev->card_info; in init_channel()
1446 int io = ni->io_type[nr]; in init_channel()
1448 tasklet_setup(&chan->demux_tasklet, demux_tasklet); in init_channel()
1449 chan->users = 0; in init_channel()
1450 chan->type = io; in init_channel()
1451 chan->mode = chan->type; /* for now only one mode */ in init_channel()
1452 chan->i2c_client_fe = 0; /* be sure this is set to zero */ in init_channel()
1455 chan->fe = NULL; in init_channel()
1456 if (ni->demod_attach[nr]) { in init_channel()
1457 ret = ni->demod_attach[nr](chan); in init_channel()
1461 if (chan->fe && ni->tuner_attach[nr]) { in init_channel()
1462 ret = ni->tuner_attach[nr](chan); in init_channel()
1468 if (!dev->ci.en && (io & NGENE_IO_TSOUT)) in init_channel()
1473 chan->DataFormatFlags = DF_SWAP32; in init_channel()
1475 if (nr == 0 || !one_adapter || dev->first_adapter == NULL) { in init_channel()
1476 adapter = &dev->adapter[nr]; in init_channel()
1479 &chan->dev->pci_dev->dev, in init_channel()
1483 if (dev->first_adapter == NULL) in init_channel()
1484 dev->first_adapter = adapter; in init_channel()
1485 chan->has_adapter = true; in init_channel()
1487 adapter = dev->first_adapter; in init_channel()
1490 if (dev->ci.en && (io & NGENE_IO_TSOUT)) { in init_channel()
1491 dvb_ca_en50221_init(adapter, dev->ci.en, 0, 1); in init_channel()
1493 chan->dev->channel[2].DataFormatFlags = DF_SWAP32; in init_channel()
1494 set_transfer(&chan->dev->channel[2], 1); in init_channel()
1495 dvb_register_device(adapter, &chan->ci_dev, in init_channel()
1498 if (!chan->ci_dev) in init_channel()
1502 if (chan->fe) { in init_channel()
1503 if (dvb_register_frontend(adapter, chan->fe) < 0) in init_channel()
1505 chan->has_demux = true; in init_channel()
1507 if (chan->fe2) { in init_channel()
1508 if (dvb_register_frontend(adapter, chan->fe2) < 0) in init_channel()
1510 if (chan->fe) { in init_channel()
1511 chan->fe2->tuner_priv = chan->fe->tuner_priv; in init_channel()
1512 memcpy(&chan->fe2->ops.tuner_ops, in init_channel()
1513 &chan->fe->ops.tuner_ops, in init_channel()
1518 if (chan->has_demux) { in init_channel()
1522 ret = my_dvb_dmxdev_ts_card_init(&chan->dmxdev, &chan->demux, in init_channel()
1523 &chan->hw_frontend, in init_channel()
1524 &chan->mem_frontend, adapter); in init_channel()
1525 ret = dvb_net_init(adapter, &chan->dvbnet, &chan->demux.dmx); in init_channel()
1531 if (chan->fe) { in init_channel()
1532 dvb_frontend_detach(chan->fe); in init_channel()
1533 chan->fe = NULL; in init_channel()
1544 dev->channel[i].number = i; in init_channels()
1545 if (init_channel(&dev->channel[i]) < 0) { in init_channels()
1546 for (j = i - 1; j >= 0; j--) in init_channels()
1547 release_channel(&dev->channel[j]); in init_channels()
1548 return -1; in init_channels()
1562 struct device *pdev = &dev->pci_dev->dev; in cxd_attach()
1563 struct ngene_ci *ci = &dev->ci; in cxd_attach()
1570 ret = ngene_port_has_cxd2099(&dev->channel[0].i2c_adapter, &type); in cxd_attach()
1581 cxd_cfg.en = &ci->en; in cxd_attach()
1583 &dev->channel[0].i2c_adapter, in cxd_attach()
1588 ci->dev = dev; in cxd_attach()
1589 dev->channel[0].i2c_client[0] = client; in cxd_attach()
1599 struct ngene_ci *ci = &dev->ci; in cxd_detach()
1601 dvb_ca_en50221_release(ci->en); in cxd_detach()
1603 dvb_module_release(dev->channel[0].i2c_client[0]); in cxd_detach()
1604 dev->channel[0].i2c_client[0] = NULL; in cxd_detach()
1605 ci->en = NULL; in cxd_detach()
1614 struct ngene_command com; in ngene_unlink() local
1616 com.cmd.hdr.Opcode = CMD_MEM_WRITE; in ngene_unlink()
1617 com.cmd.hdr.Length = 3; in ngene_unlink()
1618 com.cmd.MemoryWrite.address = 0x910c; in ngene_unlink()
1619 com.cmd.MemoryWrite.data = 0xff; in ngene_unlink()
1620 com.in_len = 3; in ngene_unlink()
1621 com.out_len = 1; in ngene_unlink()
1623 mutex_lock(&dev->cmd_mutex); in ngene_unlink()
1625 ngene_command_mutex(dev, &com); in ngene_unlink()
1626 mutex_unlock(&dev->cmd_mutex); in ngene_unlink()
1636 dev_info(&pdev->dev, "shutdown workaround...\n"); in ngene_shutdown()
1650 tasklet_kill(&dev->event_tasklet); in ngene_remove()
1651 for (i = MAX_STREAM - 1; i >= 0; i--) in ngene_remove()
1652 release_channel(&dev->channel[i]); in ngene_remove()
1653 if (dev->ci.en) in ngene_remove()
1666 return -ENODEV; in ngene_probe()
1670 stat = -ENOMEM; in ngene_probe()
1674 dev->pci_dev = pci_dev; in ngene_probe()
1675 dev->card_info = (struct ngene_info *)id->driver_data; in ngene_probe()
1676 dev_info(&pci_dev->dev, "Found %s\n", dev->card_info->name); in ngene_probe()
1695 dev->i2c_current_bus = -1; in ngene_probe()