Lines Matching +full:0 +full:x0a60
32 #define VGXY61_REG_ADDR_MASK 0xffff
34 #define VGXY61_REG_MODEL_ID VGXY61_REG_16BIT(0x0000)
35 #define VG5661_MODEL_ID 0x5661
36 #define VG5761_MODEL_ID 0x5761
37 #define VGXY61_REG_REVISION VGXY61_REG_16BIT(0x0002)
38 #define VGXY61_REG_FWPATCH_REVISION VGXY61_REG_16BIT(0x0014)
39 #define VGXY61_REG_FWPATCH_START_ADDR VGXY61_REG_8BIT(0x2000)
40 #define VGXY61_REG_SYSTEM_FSM VGXY61_REG_8BIT(0x0020)
41 #define VGXY61_SYSTEM_FSM_SW_STBY 0x03
42 #define VGXY61_SYSTEM_FSM_STREAMING 0x04
43 #define VGXY61_REG_NVM VGXY61_REG_8BIT(0x0023)
44 #define VGXY61_NVM_OK 0x04
45 #define VGXY61_REG_STBY VGXY61_REG_8BIT(0x0201)
46 #define VGXY61_STBY_NO_REQ 0
48 #define VGXY61_REG_STREAMING VGXY61_REG_8BIT(0x0202)
49 #define VGXY61_STREAMING_NO_REQ 0
50 #define VGXY61_STREAMING_REQ_STOP BIT(0)
52 #define VGXY61_REG_EXT_CLOCK VGXY61_REG_32BIT(0x0220)
53 #define VGXY61_REG_CLK_PLL_PREDIV VGXY61_REG_8BIT(0x0224)
54 #define VGXY61_REG_CLK_SYS_PLL_MULT VGXY61_REG_8BIT(0x0225)
55 #define VGXY61_REG_GPIO_0_CTRL VGXY61_REG_8BIT(0x0236)
56 #define VGXY61_REG_GPIO_1_CTRL VGXY61_REG_8BIT(0x0237)
57 #define VGXY61_REG_GPIO_2_CTRL VGXY61_REG_8BIT(0x0238)
58 #define VGXY61_REG_GPIO_3_CTRL VGXY61_REG_8BIT(0x0239)
59 #define VGXY61_REG_SIGNALS_POLARITY_CTRL VGXY61_REG_8BIT(0x023b)
60 #define VGXY61_REG_LINE_LENGTH VGXY61_REG_16BIT(0x0300)
61 #define VGXY61_REG_ORIENTATION VGXY61_REG_8BIT(0x0302)
62 #define VGXY61_REG_VT_CTRL VGXY61_REG_8BIT(0x0304)
63 #define VGXY61_REG_FORMAT_CTRL VGXY61_REG_8BIT(0x0305)
64 #define VGXY61_REG_OIF_CTRL VGXY61_REG_16BIT(0x0306)
65 #define VGXY61_REG_OIF_ROI0_CTRL VGXY61_REG_8BIT(0x030a)
66 #define VGXY61_REG_ROI0_START_H VGXY61_REG_16BIT(0x0400)
67 #define VGXY61_REG_ROI0_START_V VGXY61_REG_16BIT(0x0402)
68 #define VGXY61_REG_ROI0_END_H VGXY61_REG_16BIT(0x0404)
69 #define VGXY61_REG_ROI0_END_V VGXY61_REG_16BIT(0x0406)
70 #define VGXY61_REG_PATGEN_CTRL VGXY61_REG_32BIT(0x0440)
72 #define VGXY61_PATGEN_SHORT_ENABLE BIT(0)
75 #define VGXY61_REG_FRAME_CONTENT_CTRL VGXY61_REG_8BIT(0x0478)
76 #define VGXY61_REG_COARSE_EXPOSURE_LONG VGXY61_REG_16BIT(0x0500)
77 #define VGXY61_REG_COARSE_EXPOSURE_SHORT VGXY61_REG_16BIT(0x0504)
78 #define VGXY61_REG_ANALOG_GAIN VGXY61_REG_8BIT(0x0508)
79 #define VGXY61_REG_DIGITAL_GAIN_LONG VGXY61_REG_16BIT(0x050a)
80 #define VGXY61_REG_DIGITAL_GAIN_SHORT VGXY61_REG_16BIT(0x0512)
81 #define VGXY61_REG_FRAME_LENGTH VGXY61_REG_16BIT(0x051a)
82 #define VGXY61_REG_SIGNALS_CTRL VGXY61_REG_16BIT(0x0522)
84 #define VGXY61_REG_READOUT_CTRL VGXY61_REG_8BIT(0x0530)
85 #define VGXY61_REG_HDR_CTRL VGXY61_REG_8BIT(0x0532)
86 #define VGXY61_REG_PATGEN_LONG_DATA_GR VGXY61_REG_16BIT(0x092c)
87 #define VGXY61_REG_PATGEN_LONG_DATA_R VGXY61_REG_16BIT(0x092e)
88 #define VGXY61_REG_PATGEN_LONG_DATA_B VGXY61_REG_16BIT(0x0930)
89 #define VGXY61_REG_PATGEN_LONG_DATA_GB VGXY61_REG_16BIT(0x0932)
90 #define VGXY61_REG_PATGEN_SHORT_DATA_GR VGXY61_REG_16BIT(0x0950)
91 #define VGXY61_REG_PATGEN_SHORT_DATA_R VGXY61_REG_16BIT(0x0952)
92 #define VGXY61_REG_PATGEN_SHORT_DATA_B VGXY61_REG_16BIT(0x0954)
93 #define VGXY61_REG_PATGEN_SHORT_DATA_GB VGXY61_REG_16BIT(0x0956)
94 #define VGXY61_REG_BYPASS_CTRL VGXY61_REG_8BIT(0x0a60)
116 #define VGXY61_FWPATCH_REVISION_MINOR 0
120 0xbf, 0x00, 0x05, 0x20, 0x06, 0x01, 0xe0, 0xe0, 0x04, 0x80, 0xe6, 0x45,
121 0xed, 0x6f, 0xfe, 0xff, 0x14, 0x80, 0x1f, 0x84, 0x10, 0x42, 0x05, 0x7c,
122 0x01, 0xc4, 0x1e, 0x80, 0xb6, 0x42, 0x00, 0xe0, 0x1e, 0x82, 0x1e, 0xc0,
123 0x93, 0xdd, 0xc3, 0xc1, 0x0c, 0x04, 0x00, 0xfa, 0x86, 0x0d, 0x70, 0xe1,
124 0x04, 0x98, 0x15, 0x00, 0x28, 0xe0, 0x14, 0x02, 0x08, 0xfc, 0x15, 0x40,
125 0x28, 0xe0, 0x98, 0x58, 0xe0, 0xef, 0x04, 0x98, 0x0e, 0x04, 0x00, 0xf0,
126 0x15, 0x00, 0x28, 0xe0, 0x19, 0xc8, 0x15, 0x40, 0x28, 0xe0, 0xc6, 0x41,
127 0xfc, 0xe0, 0x14, 0x80, 0x1f, 0x84, 0x14, 0x02, 0xa0, 0xfc, 0x1e, 0x80,
128 0x14, 0x80, 0x14, 0x02, 0x80, 0xfb, 0x14, 0x02, 0xe0, 0xfc, 0x1e, 0x80,
129 0x14, 0xc0, 0x1f, 0x84, 0x14, 0x02, 0xa4, 0xfc, 0x1e, 0xc0, 0x14, 0xc0,
130 0x14, 0x02, 0x80, 0xfb, 0x14, 0x02, 0xe4, 0xfc, 0x1e, 0xc0, 0x0c, 0x0c,
131 0x00, 0xf2, 0x93, 0xdd, 0x86, 0x00, 0xf8, 0xe0, 0x04, 0x80, 0xc6, 0x03,
132 0x70, 0xe1, 0x0e, 0x84, 0x93, 0xdd, 0xc3, 0xc1, 0x0c, 0x04, 0x00, 0xfa,
133 0x6b, 0x80, 0x06, 0x40, 0x6c, 0xe1, 0x04, 0x80, 0x09, 0x00, 0xe0, 0xe0,
134 0x0b, 0xa1, 0x95, 0x84, 0x05, 0x0c, 0x1c, 0xe0, 0x86, 0x02, 0xf9, 0x60,
135 0xe0, 0xcf, 0x78, 0x6e, 0x80, 0xef, 0x25, 0x0c, 0x18, 0xe0, 0x05, 0x4c,
136 0x1c, 0xe0, 0x86, 0x02, 0xf9, 0x60, 0xe0, 0xcf, 0x0b, 0x84, 0xd8, 0x6d,
137 0x80, 0xef, 0x05, 0x4c, 0x18, 0xe0, 0x04, 0xd8, 0x0b, 0xa5, 0x95, 0x84,
138 0x05, 0x0c, 0x2c, 0xe0, 0x06, 0x02, 0x01, 0x60, 0xe0, 0xce, 0x18, 0x6d,
139 0x80, 0xef, 0x25, 0x0c, 0x30, 0xe0, 0x05, 0x4c, 0x2c, 0xe0, 0x06, 0x02,
140 0x01, 0x60, 0xe0, 0xce, 0x0b, 0x84, 0x78, 0x6c, 0x80, 0xef, 0x05, 0x4c,
141 0x30, 0xe0, 0x0c, 0x0c, 0x00, 0xf2, 0x93, 0xdd, 0x46, 0x01, 0x70, 0xe1,
142 0x08, 0x80, 0x0b, 0xa1, 0x08, 0x5c, 0x00, 0xda, 0x06, 0x01, 0x68, 0xe1,
143 0x04, 0x80, 0x4a, 0x40, 0x84, 0xe0, 0x08, 0x5c, 0x00, 0x9a, 0x06, 0x01,
144 0xe0, 0xe0, 0x04, 0x80, 0x15, 0x00, 0x60, 0xe0, 0x19, 0xc4, 0x15, 0x40,
145 0x60, 0xe0, 0x15, 0x00, 0x78, 0xe0, 0x19, 0xc4, 0x15, 0x40, 0x78, 0xe0,
146 0x93, 0xdd, 0xc3, 0xc1, 0x46, 0x01, 0x70, 0xe1, 0x08, 0x80, 0x0b, 0xa1,
147 0x08, 0x5c, 0x00, 0xda, 0x06, 0x01, 0x68, 0xe1, 0x04, 0x80, 0x4a, 0x40,
148 0x84, 0xe0, 0x08, 0x5c, 0x00, 0x9a, 0x06, 0x01, 0xe0, 0xe0, 0x14, 0x80,
149 0x25, 0x02, 0x54, 0xe0, 0x29, 0xc4, 0x25, 0x42, 0x54, 0xe0, 0x24, 0x80,
150 0x35, 0x04, 0x6c, 0xe0, 0x39, 0xc4, 0x35, 0x44, 0x6c, 0xe0, 0x25, 0x02,
151 0x64, 0xe0, 0x29, 0xc4, 0x25, 0x42, 0x64, 0xe0, 0x04, 0x80, 0x15, 0x00,
152 0x7c, 0xe0, 0x19, 0xc4, 0x15, 0x40, 0x7c, 0xe0, 0x93, 0xdd, 0xc3, 0xc1,
153 0x4c, 0x04, 0x7c, 0xfa, 0x86, 0x40, 0x98, 0xe0, 0x14, 0x80, 0x1b, 0xa1,
154 0x06, 0x00, 0x00, 0xc0, 0x08, 0x42, 0x38, 0xdc, 0x08, 0x64, 0xa0, 0xef,
155 0x86, 0x42, 0x3c, 0xe0, 0x68, 0x49, 0x80, 0xef, 0x6b, 0x80, 0x78, 0x53,
156 0xc8, 0xef, 0xc6, 0x54, 0x6c, 0xe1, 0x7b, 0x80, 0xb5, 0x14, 0x0c, 0xf8,
157 0x05, 0x14, 0x14, 0xf8, 0x1a, 0xac, 0x8a, 0x80, 0x0b, 0x90, 0x38, 0x55,
158 0x80, 0xef, 0x1a, 0xae, 0x17, 0xc2, 0x03, 0x82, 0x88, 0x65, 0x80, 0xef,
159 0x1b, 0x80, 0x0b, 0x8e, 0x68, 0x65, 0x80, 0xef, 0x9b, 0x80, 0x0b, 0x8c,
160 0x08, 0x65, 0x80, 0xef, 0x6b, 0x80, 0x0b, 0x92, 0x1b, 0x8c, 0x98, 0x64,
161 0x80, 0xef, 0x1a, 0xec, 0x9b, 0x80, 0x0b, 0x90, 0x95, 0x54, 0x10, 0xe0,
162 0xa8, 0x53, 0x80, 0xef, 0x1a, 0xee, 0x17, 0xc2, 0x03, 0x82, 0xf8, 0x63,
163 0x80, 0xef, 0x1b, 0x80, 0x0b, 0x8e, 0xd8, 0x63, 0x80, 0xef, 0x1b, 0x8c,
164 0x68, 0x63, 0x80, 0xef, 0x6b, 0x80, 0x0b, 0x92, 0x65, 0x54, 0x14, 0xe0,
165 0x08, 0x65, 0x84, 0xef, 0x68, 0x63, 0x80, 0xef, 0x7b, 0x80, 0x0b, 0x8c,
166 0xa8, 0x64, 0x84, 0xef, 0x08, 0x63, 0x80, 0xef, 0x14, 0xe8, 0x46, 0x44,
167 0x94, 0xe1, 0x24, 0x88, 0x4a, 0x4e, 0x04, 0xe0, 0x14, 0xea, 0x1a, 0x04,
168 0x08, 0xe0, 0x0a, 0x40, 0x84, 0xed, 0x0c, 0x04, 0x00, 0xe2, 0x4a, 0x40,
169 0x04, 0xe0, 0x19, 0x16, 0xc0, 0xe0, 0x0a, 0x40, 0x84, 0xed, 0x21, 0x54,
170 0x60, 0xe0, 0x0c, 0x04, 0x00, 0xe2, 0x1b, 0xa5, 0x0e, 0xea, 0x01, 0x89,
171 0x21, 0x54, 0x64, 0xe0, 0x7e, 0xe8, 0x65, 0x82, 0x1b, 0xa7, 0x26, 0x00,
172 0x00, 0x80, 0xa5, 0x82, 0x1b, 0xa9, 0x65, 0x82, 0x1b, 0xa3, 0x01, 0x85,
173 0x16, 0x00, 0x00, 0xc0, 0x01, 0x54, 0x04, 0xf8, 0x06, 0xaa, 0x01, 0x83,
174 0x06, 0xa8, 0x65, 0x81, 0x06, 0xa8, 0x01, 0x54, 0x04, 0xf8, 0x01, 0x83,
175 0x06, 0xaa, 0x09, 0x14, 0x18, 0xf8, 0x0b, 0xa1, 0x05, 0x84, 0xc6, 0x42,
176 0xd4, 0xe0, 0x14, 0x84, 0x01, 0x83, 0x01, 0x54, 0x60, 0xe0, 0x01, 0x54,
177 0x64, 0xe0, 0x0b, 0x02, 0x90, 0xe0, 0x10, 0x02, 0x90, 0xe5, 0x01, 0x54,
178 0x88, 0xe0, 0xb5, 0x81, 0xc6, 0x40, 0xd4, 0xe0, 0x14, 0x80, 0x0b, 0x02,
179 0xe0, 0xe4, 0x10, 0x02, 0x31, 0x66, 0x02, 0xc0, 0x01, 0x54, 0x88, 0xe0,
180 0x1a, 0x84, 0x29, 0x14, 0x10, 0xe0, 0x1c, 0xaa, 0x2b, 0xa1, 0xf5, 0x82,
181 0x25, 0x14, 0x10, 0xf8, 0x2b, 0x04, 0xa8, 0xe0, 0x20, 0x44, 0x0d, 0x70,
182 0x03, 0xc0, 0x2b, 0xa1, 0x04, 0x00, 0x80, 0x9a, 0x02, 0x40, 0x84, 0x90,
183 0x03, 0x54, 0x04, 0x80, 0x4c, 0x0c, 0x7c, 0xf2, 0x93, 0xdd, 0x00, 0x00,
184 0x02, 0xa9, 0x00, 0x00, 0x64, 0x4a, 0x40, 0x00, 0x08, 0x2d, 0x58, 0xe0,
185 0xa8, 0x98, 0x40, 0x00, 0x28, 0x07, 0x34, 0xe0, 0x05, 0xb9, 0x00, 0x00,
186 0x28, 0x00, 0x41, 0x05, 0x88, 0x00, 0x41, 0x3c, 0x98, 0x00, 0x41, 0x52,
187 0x04, 0x01, 0x41, 0x79, 0x3c, 0x01, 0x41, 0x6a, 0x3d, 0xfe, 0x00, 0x00,
286 .left = 0,
287 .top = 0,
333 .left = 0,
334 .top = 0,
437 for (i = 0; i < ARRAY_SIZE(vgxy61_supported_codes); i++) { in get_bpp_by_code()
450 for (i = 0; i < ARRAY_SIZE(vgxy61_supported_codes); i++) { in get_data_type_by_code()
469 for (i = 0; i < ARRAY_SIZE(predivs); i++) { in compute_pll_parameters_by_freq()
519 u8 val[sizeof(u32)] = {0}; in vgxy61_read_multiple()
524 buf[0] = reg >> 8; in vgxy61_read_multiple()
525 buf[1] = reg & 0xff; in vgxy61_read_multiple()
527 msg[0].addr = client->addr; in vgxy61_read_multiple()
528 msg[0].flags = client->flags; in vgxy61_read_multiple()
529 msg[0].buf = buf; in vgxy61_read_multiple()
530 msg[0].len = sizeof(buf); in vgxy61_read_multiple()
538 if (ret < 0) { in vgxy61_read_multiple()
567 buf[0] = reg >> 8; in vgxy61_write_multiple()
568 buf[1] = reg & 0xff; in vgxy61_write_multiple()
569 for (i = 0; i < len; i++) in vgxy61_write_multiple()
578 if (ret < 0) { in vgxy61_write_multiple()
586 return 0; in vgxy61_write_multiple()
599 if (ret < 0) in vgxy61_write_array()
606 return 0; in vgxy61_write_array()
624 ((ret < 0) || (ret == poll_val)), in vgxy61_poll_reg()
657 return bit_per_line > max_bit_per_line ? -EINVAL : 0; in vgxy61_check_bw()
662 int ret = 0; in vgxy61_apply_exposure()
665 vgxy61_write_reg(sensor, VGXY61_REG_COARSE_EXPOSURE_SHORT, 0, &ret); in vgxy61_apply_exposure()
678 for (i = 0; i < ARRAY_SIZE(vgxy61_supply_name); i++) in vgxy61_get_regulators()
688 gpiod_set_value_cansleep(sensor->reset_gpio, 0); in vgxy61_apply_reset()
692 gpiod_set_value_cansleep(sensor->reset_gpio, 0); in vgxy61_apply_reset()
720 for (index = 0; index < ARRAY_SIZE(vgxy61_supported_codes); index++) { in vgxy61_try_fmt_internal()
725 index = 0; in vgxy61_try_fmt_internal()
736 return 0; in vgxy61_try_fmt_internal()
748 return 0; in vgxy61_get_selection()
752 sel->r.top = 0; in vgxy61_get_selection()
753 sel->r.left = 0; in vgxy61_get_selection()
756 return 0; in vgxy61_get_selection()
771 return 0; in vgxy61_enum_mbus_code()
792 return 0; in vgxy61_get_fmt()
822 return 0; in vgxy61_enum_frame_size()
832 return 0; in vgxy61_update_analog_gain()
838 int ret = 0; in vgxy61_apply_digital_gain()
859 return 0; in vgxy61_update_digital_gain()
865 0x0, 0x1, 0x2, 0x3, 0x10, 0x11, 0x12, 0x13 in vgxy61_apply_patgen()
882 return 0; in vgxy61_update_patgen()
889 static const u8 index2val[] = {0x0, 0x1, 0x3}; in vgxy61_apply_gpiox_strobe_mode()
893 if (reg < 0) in vgxy61_apply_gpiox_strobe_mode()
895 reg &= ~(0xf << (idx * VGXY61_SIGNALS_GPIO_ID_SHIFT)); in vgxy61_apply_gpiox_strobe_mode()
922 return 0; in vgxy61_update_gpios_strobe_mode()
924 for (i = 0; i < VGXY61_NB_GPIOS; i++) { in vgxy61_update_gpios_strobe_mode()
932 return 0; in vgxy61_update_gpios_strobe_mode()
938 int ret = 0; in vgxy61_update_gpios_strobe_polarity()
990 u16 new_expo_short = 0; in vgxy61_update_exposure()
991 u16 expo_short_max = 0; in vgxy61_update_exposure()
993 u16 expo_long_max = 0; in vgxy61_update_exposure()
1027 * As short expo is 0 here, only the second rule of thumb in vgxy61_update_exposure()
1055 return 0; in vgxy61_update_exposure()
1081 return 0; in vgxy61_update_vblank()
1087 static const u8 index2val[] = {0x1, 0x4, 0xa}; in vgxy61_apply_hdr()
1116 return 0; in vgxy61_update_hdr()
1153 for (i = 0; i < VGXY61_NB_GPIOS; i++) { in vgxy61_apply_settings()
1160 return 0; in vgxy61_apply_settings()
1167 int ret = 0; in vgxy61_stream_enable()
1216 return 0; in vgxy61_stream_enable()
1257 int ret = 0; in vgxy61_s_stream()
1292 fmt = v4l2_subdev_state_get_format(sd_state, 0); in vgxy61_set_fmt()
1312 0xffff - new_mode->crop.height, in vgxy61_set_fmt()
1330 struct v4l2_subdev_format fmt = { 0 }; in vgxy61_init_state()
1366 ret = 0; in vgxy61_s_ctrl()
1376 0xffff - cur_mode->crop.height, in vgxy61_s_ctrl()
1413 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN, 0, 0x1c, 1, in vgxy61_init_controls()
1415 v4l2_ctrl_new_std(hdl, ops, V4L2_CID_DIGITAL_GAIN, 0, 0xfff, 1, in vgxy61_init_controls()
1419 0, 0, vgxy61_test_pattern_menu); in vgxy61_init_controls()
1420 ctrl = v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK, 0, in vgxy61_init_controls()
1426 ARRAY_SIZE(link_freq) - 1, 0, link_freq); in vgxy61_init_controls()
1430 ARRAY_SIZE(vgxy61_hdr_mode_menu) - 1, 0, in vgxy61_init_controls()
1449 0xffff - cur_mode->crop.height, in vgxy61_init_controls()
1452 0, 1, 1, sensor->vflip); in vgxy61_init_controls()
1454 0, 1, 1, sensor->hflip); in vgxy61_init_controls()
1470 return 0; in vgxy61_init_controls()
1513 u32 log2phy[VGXY61_NB_POLARITIES] = {~0, ~0, ~0, ~0, ~0}; in vgxy61_tx_from_ep()
1514 u32 phy2log[VGXY61_NB_POLARITIES] = {~0, ~0, ~0, ~0, ~0}; in vgxy61_tx_from_ep()
1515 int polarities[VGXY61_NB_POLARITIES] = {0, 0, 0, 0, 0}; in vgxy61_tx_from_ep()
1531 log2phy[0] = ep.bus.mipi_csi2.clock_lane; in vgxy61_tx_from_ep()
1532 phy2log[log2phy[0]] = 0; in vgxy61_tx_from_ep()
1541 for (p = 0; p < VGXY61_NB_POLARITIES; p++) { in vgxy61_tx_from_ep()
1542 if (phy2log[p] != ~0) in vgxy61_tx_from_ep()
1548 for (l = 0; l < l_nb + 1; l++) in vgxy61_tx_from_ep()
1551 if (log2phy[0] != 0) { in vgxy61_tx_from_ep()
1552 dev_err(&client->dev, "clk lane must be map to physical lane 0\n"); in vgxy61_tx_from_ep()
1559 (polarities[0] << 3) + in vgxy61_tx_from_ep()
1564 for (i = 0; i < VGXY61_NB_POLARITIES; i++) { in vgxy61_tx_from_ep()
1569 dev_dbg(&client->dev, "oif_ctrl = 0x%04x\n", sensor->oif_ctrl); in vgxy61_tx_from_ep()
1573 return 0; in vgxy61_tx_from_ep()
1586 int ret = 0; in vgxy61_configure()
1596 if (line_length < 0) in vgxy61_configure()
1603 vgxy61_write_reg(sensor, VGXY61_REG_FRAME_CONTENT_CTRL, 0, &ret); in vgxy61_configure()
1609 vgxy61_write_reg(sensor, VGXY61_REG_PATGEN_LONG_DATA_GR, 0x800, &ret); in vgxy61_configure()
1610 vgxy61_write_reg(sensor, VGXY61_REG_PATGEN_LONG_DATA_R, 0x800, &ret); in vgxy61_configure()
1611 vgxy61_write_reg(sensor, VGXY61_REG_PATGEN_LONG_DATA_B, 0x800, &ret); in vgxy61_configure()
1612 vgxy61_write_reg(sensor, VGXY61_REG_PATGEN_LONG_DATA_GB, 0x800, &ret); in vgxy61_configure()
1613 vgxy61_write_reg(sensor, VGXY61_REG_PATGEN_SHORT_DATA_GR, 0x800, &ret); in vgxy61_configure()
1614 vgxy61_write_reg(sensor, VGXY61_REG_PATGEN_SHORT_DATA_R, 0x800, &ret); in vgxy61_configure()
1615 vgxy61_write_reg(sensor, VGXY61_REG_PATGEN_SHORT_DATA_B, 0x800, &ret); in vgxy61_configure()
1616 vgxy61_write_reg(sensor, VGXY61_REG_PATGEN_SHORT_DATA_GB, 0x800, &ret); in vgxy61_configure()
1620 return 0; in vgxy61_configure()
1633 ret = vgxy61_write_reg(sensor, VGXY61_REG_STBY, 0x10, NULL); in vgxy61_patch()
1637 ret = vgxy61_poll_reg(sensor, VGXY61_REG_STBY, 0, VGXY61_TIMEOUT_MS); in vgxy61_patch()
1642 if (patch < 0) in vgxy61_patch()
1652 patch >> 12, (patch >> 8) & 0x0f, patch & 0xff); in vgxy61_patch()
1656 patch >> 12, (patch >> 8) & 0x0f, patch & 0xff); in vgxy61_patch()
1658 return 0; in vgxy61_patch()
1667 if (device_rev < 0) in vgxy61_detect_cut_version()
1671 case 0xA: in vgxy61_detect_cut_version()
1675 case 0xB: in vgxy61_detect_cut_version()
1677 return 0; in vgxy61_detect_cut_version()
1678 case 0xC: in vgxy61_detect_cut_version()
1680 return 0; in vgxy61_detect_cut_version()
1690 int id = 0; in vgxy61_detect()
1694 if (id < 0) in vgxy61_detect()
1700 dev_dbg(&client->dev, "detected sensor id = 0x%04x\n", id); in vgxy61_detect()
1709 if (st < 0) in vgxy61_detect()
1718 return 0; in vgxy61_detect()
1768 return 0; in vgxy61_power_on()
1788 return 0; in vgxy61_power_off()
1829 sensor->expo_short = 0; in vgxy61_probe()
1832 sensor->analog_gain = 0; in vgxy61_probe()
1835 handle = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), 0, 0, 0); in vgxy61_probe()
1923 return 0; in vgxy61_probe()