Lines Matching +full:1 +full:a
87 /* Task A definition */
225 {R_00_CHIP_VERSION,1,
231 {R_01_INC_DELAY,1,
233 {R_02_INPUT_CNTL_1,1,
234 "Analog input control 1"},
235 {R_03_INPUT_CNTL_2,1,
237 {R_04_INPUT_CNTL_3,1,
239 {R_05_INPUT_CNTL_4,1,
243 {R_06_H_SYNC_START,1,
245 {R_07_H_SYNC_STOP,1,
247 {R_08_SYNC_CNTL,1,
249 {R_09_LUMA_CNTL,1,
251 {R_0A_LUMA_BRIGHT_CNTL,1,
253 {R_0B_LUMA_CONTRAST_CNTL,1,
255 {R_0C_CHROMA_SAT_CNTL,1,
257 {R_0D_CHROMA_HUE_CNTL,1,
259 {R_0E_CHROMA_CNTL_1,1,
260 "Chrominance control 1"},
261 {R_0F_CHROMA_GAIN_CNTL,1,
263 {R_10_CHROMA_CNTL_2,1,
265 {R_11_MODE_DELAY_CNTL,1,
267 {R_12_RT_SIGNAL_CNTL,1,
269 {R_13_RT_X_PORT_OUT_CNTL,1,
271 {R_14_ANAL_ADC_COMPAT_CNTL,1,
273 {R_15_VGATE_START_FID_CHG, 1,
275 {R_16_VGATE_STOP,1,
277 {R_17_MISC_VGATE_CONF_AND_MSB, 1,
279 {R_18_RAW_DATA_GAIN_CNTL,1,
281 {R_19_RAW_DATA_OFF_CNTL,1,
283 {R_1A_COLOR_KILL_LVL_CNTL,1,
285 { R_1B_MISC_TVVCRDET, 1,
287 { R_1C_ENHAN_COMB_CTRL1, 1,
289 { R_1D_ENHAN_COMB_CTRL2, 1,
291 {R_1E_STATUS_BYTE_1_VD_DEC,1,
292 "Status byte 1 video decoder"},
293 {R_1F_STATUS_BYTE_2_VD_DEC,1,
298 {R_23_INPUT_CNTL_5,1,
300 {R_24_INPUT_CNTL_6,1,
302 {R_25_INPUT_CNTL_7,1,
305 {R_29_COMP_DELAY,1,
307 {R_2A_COMP_BRIGHT_CNTL,1,
309 {R_2B_COMP_CONTRAST_CNTL,1,
311 {R_2C_COMP_SAT_CNTL,1,
313 {R_2D_INTERRUPT_MASK_1,1,
314 "Interrupt mask 1"},
315 {R_2E_INTERRUPT_MASK_2,1,
317 {R_2F_INTERRUPT_MASK_3,1,
327 {R_38_CLK_RATIO_AMXCLK_TO_ASCLK,1,
329 {R_39_CLK_RATIO_ASCLK_TO_ALRCLK,1,
331 {R_3A_AUD_CLK_GEN_BASIC_SETUP,1,
336 {R_40_SLICER_CNTL_1,1,
337 "Slicer control 1"},
340 {R_58_PROGRAM_FRAMING_CODE,1,
342 {R_59_H_OFF_FOR_SLICER,1,
344 {R_5A_V_OFF_FOR_SLICER,1,
346 {R_5B_FLD_OFF_AND_MSB_FOR_H_AND_V_OFF,1,
348 {R_5D_DID,1,
350 {R_5E_SDID,1,
352 {R_60_SLICER_STATUS_BYTE_0,1,
354 {R_61_SLICER_STATUS_BYTE_1,1,
355 "Slicer status byte 1"},
356 {R_62_SLICER_STATUS_BYTE_2,1,
362 {R_80_GLOBAL_CNTL_1,1,
363 "Global control 1"},
364 {R_81_V_SYNC_FLD_ID_SRC_SEL_AND_RETIMED_V_F,1,
367 {R_83_X_PORT_I_O_ENA_AND_OUT_CLK,1,
369 {R_84_I_PORT_SIGNAL_DEF,1,
371 {R_85_I_PORT_SIGNAL_POLAR,1,
373 {R_86_I_PORT_FIFO_FLAG_CNTL_AND_ARBIT,1,
375 {R_87_I_PORT_I_O_ENA_OUT_CLK_AND_GATED, 1,
377 {R_88_POWER_SAVE_ADC_PORT_CNTL,1,
380 {R_8F_STATUS_INFO_SCALER,1,
383 /* Task A definition: R_90_A_TASK_HANDLING_CNTL to R_BF_A_VERT_LUMA_PHASE_OFF_11 */
384 /* Task A: Basic settings and acquisition window definition */
385 {R_90_A_TASK_HANDLING_CNTL,1,
386 "Task A: Task handling control"},
387 {R_91_A_X_PORT_FORMATS_AND_CONF,1,
388 "Task A: X port formats and configuration"},
389 {R_92_A_X_PORT_INPUT_REFERENCE_SIGNAL,1,
390 "Task A: X port input reference signal definition"},
391 {R_93_A_I_PORT_OUTPUT_FORMATS_AND_CONF,1,
392 "Task A: I port output formats and configuration"},
394 "Task A: Horizontal input window start"},
396 "Task A: Horizontal input window length"},
398 "Task A: Vertical input window start"},
400 "Task A: Vertical input window length"},
402 "Task A: Horizontal output window length"},
404 "Task A: Vertical output window length"},
406 /* Task A: FIR filtering and prescaling */
407 {R_A0_A_HORIZ_PRESCALING,1,
408 "Task A: Horizontal prescaling"},
409 {R_A1_A_ACCUMULATION_LENGTH,1,
410 "Task A: Accumulation length"},
411 {R_A2_A_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
412 "Task A: Prescaler DC gain and FIR prefilter"},
414 {R_A4_A_LUMA_BRIGHTNESS_CNTL,1,
415 "Task A: Luminance brightness control"},
416 {R_A5_A_LUMA_CONTRAST_CNTL,1,
417 "Task A: Luminance contrast control"},
418 {R_A6_A_CHROMA_SATURATION_CNTL,1,
419 "Task A: Chrominance saturation control"},
422 /* Task A: Horizontal phase scaling */
424 "Task A: Horizontal luminance scaling increment"},
425 {R_AA_A_HORIZ_LUMA_PHASE_OFF,1,
426 "Task A: Horizontal luminance phase offset"},
429 "Task A: Horizontal chrominance scaling increment"},
430 {R_AE_A_HORIZ_CHROMA_PHASE_OFF,1,
431 "Task A: Horizontal chrominance phase offset"},
434 /* Task A: Vertical scaling */
436 "Task A: Vertical luminance scaling increment"},
438 "Task A: Vertical chrominance scaling increment"},
439 {R_B4_A_VERT_SCALING_MODE_CNTL,1,
440 "Task A: Vertical scaling mode control"},
442 {R_B8_A_VERT_CHROMA_PHASE_OFF_00,1,
443 "Task A: Vertical chrominance phase offset '00'"},
444 {R_B9_A_VERT_CHROMA_PHASE_OFF_01,1,
445 "Task A: Vertical chrominance phase offset '01'"},
446 {R_BA_A_VERT_CHROMA_PHASE_OFF_10,1,
447 "Task A: Vertical chrominance phase offset '10'"},
448 {R_BB_A_VERT_CHROMA_PHASE_OFF_11,1,
449 "Task A: Vertical chrominance phase offset '11'"},
450 {R_BC_A_VERT_LUMA_PHASE_OFF_00,1,
451 "Task A: Vertical luminance phase offset '00'"},
452 {R_BD_A_VERT_LUMA_PHASE_OFF_01,1,
453 "Task A: Vertical luminance phase offset '01'"},
454 {R_BE_A_VERT_LUMA_PHASE_OFF_10,1,
455 "Task A: Vertical luminance phase offset '10'"},
456 {R_BF_A_VERT_LUMA_PHASE_OFF_11,1,
457 "Task A: Vertical luminance phase offset '11'"},
461 {R_C0_B_TASK_HANDLING_CNTL,1,
463 {R_C1_B_X_PORT_FORMATS_AND_CONF,1,
465 {R_C2_B_INPUT_REFERENCE_SIGNAL_DEFINITION,1,
467 {R_C3_B_I_PORT_FORMATS_AND_CONF,1,
483 {R_D0_B_HORIZ_PRESCALING,1,
485 {R_D1_B_ACCUMULATION_LENGTH,1,
487 {R_D2_B_PRESCALER_DC_GAIN_AND_FIR_PREFILTER,1,
490 {R_D4_B_LUMA_BRIGHTNESS_CNTL,1,
492 {R_D5_B_LUMA_CONTRAST_CNTL,1,
494 {R_D6_B_CHROMA_SATURATION_CNTL,1,
501 {R_DA_B_HORIZ_LUMA_PHASE_OFF,1,
506 {R_DE_B_HORIZ_PHASE_OFFSET_CRHOMA,1,
515 {R_E4_B_VERT_SCALING_MODE_CNTL,1,
518 {R_E8_B_VERT_CHROMA_PHASE_OFF_00,1,
520 {R_E9_B_VERT_CHROMA_PHASE_OFF_01,1,
522 {R_EA_B_VERT_CHROMA_PHASE_OFF_10,1,
524 {R_EB_B_VERT_CHROMA_PHASE_OFF_11,1,
526 {R_EC_B_VERT_LUMA_PHASE_OFF_00,1,
528 {R_ED_B_VERT_LUMA_PHASE_OFF_01,1,
530 {R_EE_B_VERT_LUMA_PHASE_OFF_10,1,
532 {R_EF_B_VERT_LUMA_PHASE_OFF_11,1,
536 { R_F0_LFCO_PER_LINE, 1,
538 { R_F1_P_I_PARAM_SELECT,1,
540 { R_F2_NOMINAL_PLL2_DTO,1,
542 {R_F3_PLL_INCREMENT,1,
544 {R_F4_PLL2_STATUS,1,
546 {R_F5_PULSGEN_LINE_LENGTH,1,
548 {R_F6_PULSE_A_POS_LSB_AND_PULSEGEN_CONFIG,1,
549 "Pulse A Position, Pulsgen Resync., Pulsgen. H-Src., Pulsgen. line length"},
550 {R_F7_PULSE_A_POS_MSB,1,
551 "Pulse A Position"},
557 {R_FF_S_PLL_MAX_PHASE_ERR_THRESH_NUM_LINES,1,