Lines Matching +full:0 +full:x1801
38 #define MT9P031_CHIP_VERSION 0x00
39 #define MT9P031_CHIP_VERSION_VALUE 0x1801
40 #define MT9P031_ROW_START 0x01
41 #define MT9P031_ROW_START_MIN 0
44 #define MT9P031_COLUMN_START 0x02
45 #define MT9P031_COLUMN_START_MIN 0
48 #define MT9P031_WINDOW_HEIGHT 0x03
52 #define MT9P031_WINDOW_WIDTH 0x04
56 #define MT9P031_HORIZONTAL_BLANK 0x05
57 #define MT9P031_HORIZONTAL_BLANK_MIN 0
59 #define MT9P031_VERTICAL_BLANK 0x06
63 #define MT9P031_OUTPUT_CONTROL 0x07
66 #define MT9P031_OUTPUT_CONTROL_DEF 0x1f82
67 #define MT9P031_SHUTTER_WIDTH_UPPER 0x08
68 #define MT9P031_SHUTTER_WIDTH_LOWER 0x09
72 #define MT9P031_PLL_CONTROL 0x10
73 #define MT9P031_PLL_CONTROL_PWROFF 0x0050
74 #define MT9P031_PLL_CONTROL_PWRON 0x0051
75 #define MT9P031_PLL_CONTROL_USEPLL 0x0052
76 #define MT9P031_PLL_CONFIG_1 0x11
77 #define MT9P031_PLL_CONFIG_2 0x12
78 #define MT9P031_PIXEL_CLOCK_CONTROL 0x0a
81 #define MT9P031_PIXEL_CLOCK_DIVIDE(n) ((n) << 0)
82 #define MT9P031_RESTART 0x0b
84 #define MT9P031_FRAME_RESTART BIT(0)
85 #define MT9P031_SHUTTER_DELAY 0x0c
86 #define MT9P031_RST 0x0d
87 #define MT9P031_RST_ENABLE BIT(0)
88 #define MT9P031_READ_MODE_1 0x1e
89 #define MT9P031_READ_MODE_2 0x20
93 #define MT9P031_ROW_ADDRESS_MODE 0x22
94 #define MT9P031_COLUMN_ADDRESS_MODE 0x23
95 #define MT9P031_GLOBAL_GAIN 0x35
100 #define MT9P031_ROW_BLACK_TARGET 0x49
101 #define MT9P031_ROW_BLACK_DEF_OFFSET 0x4b
102 #define MT9P031_GREEN1_OFFSET 0x60
103 #define MT9P031_GREEN2_OFFSET 0x61
104 #define MT9P031_BLACK_LEVEL_CALIBRATION 0x62
105 #define MT9P031_BLC_MANUAL_BLC BIT(0)
106 #define MT9P031_RED_OFFSET 0x63
107 #define MT9P031_BLUE_OFFSET 0x64
108 #define MT9P031_TEST_PATTERN 0xa0
110 #define MT9P031_TEST_PATTERN_ENABLE BIT(0)
111 #define MT9P031_TEST_PATTERN_GREEN 0xa1
112 #define MT9P031_TEST_PATTERN_RED 0xa2
113 #define MT9P031_TEST_PATTERN_BLUE 0xa3
170 if (ret < 0) in mt9p031_set_output_control()
174 return 0; in mt9p031_set_output_control()
184 if (ret < 0) in mt9p031_set_mode2()
188 return 0; in mt9p031_set_mode2()
198 if (ret < 0) in mt9p031_reset()
200 ret = mt9p031_write(client, MT9P031_RST, 0); in mt9p031_reset()
201 if (ret < 0) in mt9p031_reset()
206 if (ret < 0) in mt9p031_reset()
210 0); in mt9p031_reset()
241 if (ret < 0) in mt9p031_clk_setup()
258 return 0; in mt9p031_clk_setup()
274 return 0; in mt9p031_pll_enable()
278 if (ret < 0) in mt9p031_pll_enable()
283 if (ret < 0) in mt9p031_pll_enable()
287 if (ret < 0) in mt9p031_pll_enable()
302 return 0; in mt9p031_pll_disable()
322 if (ret < 0) in mt9p031_power_on()
337 gpiod_set_value(mt9p031->reset, 0); in mt9p031_power_on()
346 return 0; in mt9p031_power_on()
369 return 0; in __mt9p031_set_power()
373 if (ret < 0) in __mt9p031_set_power()
377 if (ret < 0) { in __mt9p031_set_power()
386 if (ret < 0) in __mt9p031_set_power()
417 if (ret < 0) in mt9p031_set_params()
420 if (ret < 0) in mt9p031_set_params()
423 if (ret < 0) in mt9p031_set_params()
426 if (ret < 0) in mt9p031_set_params()
439 if (ret < 0) in mt9p031_set_params()
443 if (ret < 0) in mt9p031_set_params()
453 if (ret < 0) in mt9p031_set_params()
456 if (ret < 0) in mt9p031_set_params()
473 if (ret < 0) in mt9p031_s_stream()
479 if (ret < 0) in mt9p031_s_stream()
484 MT9P031_OUTPUT_CONTROL_CEN, 0); in mt9p031_s_stream()
485 if (ret < 0) in mt9p031_s_stream()
492 if (ret < 0) in mt9p031_s_stream()
496 ret = mt9p031_set_output_control(mt9p031, 0, in mt9p031_s_stream()
498 if (ret < 0) in mt9p031_s_stream()
508 if (ret < 0) in mt9p031_s_stream()
524 return 0; in mt9p031_enum_mbus_code()
542 return 0; in mt9p031_enum_frame_size()
583 return 0; in mt9p031_get_format()
621 return 0; in mt9p031_set_format()
636 return 0; in mt9p031_get_selection()
641 return 0; in mt9p031_get_selection()
696 return 0; in mt9p031_set_selection()
708 crop = __mt9p031_get_pad_crop(mt9p031, sd_state, 0, which); in mt9p031_init_state()
714 format = __mt9p031_get_pad_format(mt9p031, sd_state, 0, which); in mt9p031_init_state()
726 return 0; in mt9p031_init_state()
733 #define V4L2_CID_BLC_AUTO (V4L2_CID_USER_BASE | 0x1002)
734 #define V4L2_CID_BLC_TARGET_LEVEL (V4L2_CID_USER_BASE | 0x1003)
735 #define V4L2_CID_BLC_ANALOG_OFFSET (V4L2_CID_USER_BASE | 0x1004)
736 #define V4L2_CID_BLC_DIGITAL_OFFSET (V4L2_CID_USER_BASE | 0x1005)
743 if (mt9p031->blc_auto->cur.val != 0) { in mt9p031_restore_blc()
744 ret = mt9p031_set_mode2(mt9p031, 0, in mt9p031_restore_blc()
746 if (ret < 0) in mt9p031_restore_blc()
750 if (mt9p031->blc_offset->cur.val != 0) { in mt9p031_restore_blc()
753 if (ret < 0) in mt9p031_restore_blc()
757 return 0; in mt9p031_restore_blc()
769 return 0; in mt9p031_s_ctrl()
774 (ctrl->val >> 16) & 0xffff); in mt9p031_s_ctrl()
775 if (ret < 0) in mt9p031_s_ctrl()
779 ctrl->val & 0xffff); in mt9p031_s_ctrl()
811 0, MT9P031_READ_MODE_2_COL_MIR); in mt9p031_s_ctrl()
814 MT9P031_READ_MODE_2_COL_MIR, 0); in mt9p031_s_ctrl()
819 0, MT9P031_READ_MODE_2_ROW_MIR); in mt9p031_s_ctrl()
822 MT9P031_READ_MODE_2_ROW_MIR, 0); in mt9p031_s_ctrl()
830 v4l2_ctrl_activate(mt9p031->blc_auto, ctrl->val == 0); in mt9p031_s_ctrl()
831 v4l2_ctrl_activate(mt9p031->blc_offset, ctrl->val == 0); in mt9p031_s_ctrl()
836 if (ret < 0) in mt9p031_s_ctrl()
839 return mt9p031_write(client, MT9P031_TEST_PATTERN, 0); in mt9p031_s_ctrl()
842 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_GREEN, 0x05a0); in mt9p031_s_ctrl()
843 if (ret < 0) in mt9p031_s_ctrl()
845 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_RED, 0x0a50); in mt9p031_s_ctrl()
846 if (ret < 0) in mt9p031_s_ctrl()
848 ret = mt9p031_write(client, MT9P031_TEST_PATTERN_BLUE, 0x0aa0); in mt9p031_s_ctrl()
849 if (ret < 0) in mt9p031_s_ctrl()
854 0); in mt9p031_s_ctrl()
855 if (ret < 0) in mt9p031_s_ctrl()
858 ret = mt9p031_write(client, MT9P031_ROW_BLACK_DEF_OFFSET, 0); in mt9p031_s_ctrl()
859 if (ret < 0) in mt9p031_s_ctrl()
868 ctrl->val ? 0 : MT9P031_READ_MODE_2_ROW_BLC, in mt9p031_s_ctrl()
869 ctrl->val ? MT9P031_READ_MODE_2_ROW_BLC : 0); in mt9p031_s_ctrl()
870 if (ret < 0) in mt9p031_s_ctrl()
874 ctrl->val ? 0 : MT9P031_BLC_MANUAL_BLC); in mt9p031_s_ctrl()
884 if (ret < 0) in mt9p031_s_ctrl()
887 if (ret < 0) in mt9p031_s_ctrl()
890 if (ret < 0) in mt9p031_s_ctrl()
899 return 0; in mt9p031_s_ctrl()
925 .min = 0,
929 .flags = 0,
935 .min = 0,
939 .flags = 0,
949 .flags = 0,
959 .flags = 0,
970 int ret = 0; in mt9p031_set_power()
974 /* If the power count is modified from 0 to != 0 or from != 0 to 0, in mt9p031_set_power()
979 if (ret < 0) in mt9p031_set_power()
985 WARN_ON(mt9p031->power_count < 0); in mt9p031_set_power()
1004 if (ret < 0) { in mt9p031_registered()
1015 "0x%04x\n", data); in mt9p031_registered()
1019 dev_info(&client->dev, "MT9P031 detected at address 0x%02x\n", in mt9p031_registered()
1022 return 0; in mt9p031_registered()
1032 return mt9p031_set_power(subdev, 0); in mt9p031_close()
1085 if (v4l2_fwnode_endpoint_parse(of_fwnode_handle(np), &endpoint) < 0) in mt9p031_get_pdata()
1132 mt9p031->regulators[0].supply = "vdd"; in mt9p031_probe()
1137 if (ret < 0) { in mt9p031_probe()
1154 V4L2_CID_HFLIP, 0, 1, 1, 0); in mt9p031_probe()
1156 V4L2_CID_VFLIP, 0, 1, 1, 0); in mt9p031_probe()
1162 ARRAY_SIZE(mt9p031_test_pattern_menu) - 1, 0, in mt9p031_probe()
1163 0, mt9p031_test_pattern_menu); in mt9p031_probe()
1165 for (i = 0; i < ARRAY_SIZE(mt9p031_ctrls); ++i) in mt9p031_probe()
1187 if (ret < 0) in mt9p031_probe()
1206 if (ret < 0) { in mt9p031_probe()