Lines Matching +full:0 +full:x4e
8 …* Datasheet v1.0 available at http://files.pine64.org/doc/datasheet/PinebookPro/GC2145%20CSP%20Dat…
29 #define GC2145_CHIP_ID 0x2145
31 /* Page 0 */
32 #define GC2145_REG_EXPOSURE CCI_REG16(0x03)
33 #define GC2145_REG_HBLANK CCI_REG16(0x05)
34 #define GC2145_REG_VBLANK CCI_REG16(0x07)
35 #define GC2145_REG_ROW_START CCI_REG16(0x09)
36 #define GC2145_REG_COL_START CCI_REG16(0x0b)
37 #define GC2145_REG_WIN_HEIGHT CCI_REG16(0x0d)
38 #define GC2145_REG_WIN_WIDTH CCI_REG16(0x0f)
39 #define GC2145_REG_ANALOG_MODE1 CCI_REG8(0x17)
40 #define GC2145_REG_OUTPUT_FMT CCI_REG8(0x84)
41 #define GC2145_REG_SYNC_MODE CCI_REG8(0x86)
44 #define GC2145_REG_BYPASS_MODE CCI_REG8(0x89)
46 #define GC2145_REG_DEBUG_MODE2 CCI_REG8(0x8c)
47 #define GC2145_REG_DEBUG_MODE3 CCI_REG8(0x8d)
48 #define GC2145_REG_CROP_ENABLE CCI_REG8(0x90)
49 #define GC2145_REG_CROP_Y CCI_REG16(0x91)
50 #define GC2145_REG_CROP_X CCI_REG16(0x93)
51 #define GC2145_REG_CROP_HEIGHT CCI_REG16(0x95)
52 #define GC2145_REG_CROP_WIDTH CCI_REG16(0x97)
53 #define GC2145_REG_GLOBAL_GAIN CCI_REG8(0xb0)
54 #define GC2145_REG_CHIP_ID CCI_REG16(0xf0)
55 #define GC2145_REG_PAD_IO CCI_REG8(0xf2)
56 #define GC2145_REG_PAGE_SELECT CCI_REG8(0xfe)
58 #define GC2145_REG_DPHY_ANALOG_MODE1 CCI_REG8(0x01)
59 #define GC2145_DPHY_MODE_PHY_CLK_EN BIT(0)
63 #define GC2145_REG_DPHY_ANALOG_MODE2 CCI_REG8(0x02)
64 #define GC2145_DPHY_CLK_DIFF(a) ((a) & 0x07)
65 #define GC2145_DPHY_LANE0_DIFF(a) (((a) & 0x07) << 4)
66 #define GC2145_REG_DPHY_ANALOG_MODE3 CCI_REG8(0x03)
67 #define GC2145_DPHY_LANE1_DIFF(a) ((a) & 0x07)
71 #define GC2145_REG_FIFO_FULL_LVL_LOW CCI_REG8(0x04)
72 #define GC2145_REG_FIFO_FULL_LVL_HIGH CCI_REG8(0x05)
73 #define GC2145_REG_FIFO_MODE CCI_REG8(0x06)
76 #define GC2145_REG_BUF_CSI2_MODE CCI_REG8(0x10)
77 #define GC2145_CSI2_MODE_DOUBLE BIT(0)
81 #define GC2145_REG_MIPI_DT CCI_REG8(0x11)
82 #define GC2145_REG_LWC_LOW CCI_REG8(0x12)
83 #define GC2145_REG_LWC_HIGH CCI_REG8(0x13)
84 #define GC2145_REG_DPHY_MODE CCI_REG8(0x15)
86 #define GC2145_REG_FIFO_GATE_MODE CCI_REG8(0x17)
87 #define GC2145_REG_T_LPX CCI_REG8(0x21)
88 #define GC2145_REG_T_CLK_HS_PREPARE CCI_REG8(0x22)
89 #define GC2145_REG_T_CLK_ZERO CCI_REG8(0x23)
90 #define GC2145_REG_T_CLK_PRE CCI_REG8(0x24)
91 #define GC2145_REG_T_CLK_POST CCI_REG8(0x25)
92 #define GC2145_REG_T_CLK_TRAIL CCI_REG8(0x26)
93 #define GC2145_REG_T_HS_EXIT CCI_REG8(0x27)
94 #define GC2145_REG_T_WAKEUP CCI_REG8(0x28)
95 #define GC2145_REG_T_HS_PREPARE CCI_REG8(0x29)
96 #define GC2145_REG_T_HS_ZERO CCI_REG8(0x2a)
97 #define GC2145_REG_T_HS_TRAIL CCI_REG8(0x2b)
129 #define GC2145_DEFAULT_EXPOSURE 0x04e2
130 #define GC2145_DEFAULT_GLOBAL_GAIN 0x55
132 {GC2145_REG_PAGE_SELECT, 0x00},
134 {CCI_REG8(0x12), 0x2e},
136 {GC2145_REG_ANALOG_MODE1, 0x14},
138 {CCI_REG8(0x18), 0x22}, {CCI_REG8(0x19), 0x0e}, {CCI_REG8(0x1a), 0x01},
139 {CCI_REG8(0x1b), 0x4b}, {CCI_REG8(0x1c), 0x07}, {CCI_REG8(0x1d), 0x10},
140 {CCI_REG8(0x1e), 0x88}, {CCI_REG8(0x1f), 0x78}, {CCI_REG8(0x20), 0x03},
141 {CCI_REG8(0x21), 0x40}, {CCI_REG8(0x22), 0xa0}, {CCI_REG8(0x24), 0x16},
142 {CCI_REG8(0x25), 0x01}, {CCI_REG8(0x26), 0x10}, {CCI_REG8(0x2d), 0x60},
143 {CCI_REG8(0x30), 0x01}, {CCI_REG8(0x31), 0x90}, {CCI_REG8(0x33), 0x06},
144 {CCI_REG8(0x34), 0x01},
146 {CCI_REG8(0x80), 0x7f}, {CCI_REG8(0x81), 0x26}, {CCI_REG8(0x82), 0xfa},
147 {CCI_REG8(0x83), 0x00}, {CCI_REG8(0x84), 0x02}, {CCI_REG8(0x86), 0x02},
148 {CCI_REG8(0x88), 0x03},
149 {GC2145_REG_BYPASS_MODE, 0x03},
150 {CCI_REG8(0x85), 0x08}, {CCI_REG8(0x8a), 0x00}, {CCI_REG8(0x8b), 0x00},
152 {CCI_REG8(0xc3), 0x00}, {CCI_REG8(0xc4), 0x80}, {CCI_REG8(0xc5), 0x90},
153 {CCI_REG8(0xc6), 0x3b}, {CCI_REG8(0xc7), 0x46},
155 {GC2145_REG_PAGE_SELECT, 0x00},
156 {CCI_REG8(0x40), 0x42}, {CCI_REG8(0x41), 0x00}, {CCI_REG8(0x43), 0x5b},
157 {CCI_REG8(0x5e), 0x00}, {CCI_REG8(0x5f), 0x00}, {CCI_REG8(0x60), 0x00},
158 {CCI_REG8(0x61), 0x00}, {CCI_REG8(0x62), 0x00}, {CCI_REG8(0x63), 0x00},
159 {CCI_REG8(0x64), 0x00}, {CCI_REG8(0x65), 0x00}, {CCI_REG8(0x66), 0x20},
160 {CCI_REG8(0x67), 0x20}, {CCI_REG8(0x68), 0x20}, {CCI_REG8(0x69), 0x20},
161 {CCI_REG8(0x76), 0x00}, {CCI_REG8(0x6a), 0x08}, {CCI_REG8(0x6b), 0x08},
162 {CCI_REG8(0x6c), 0x08}, {CCI_REG8(0x6d), 0x08}, {CCI_REG8(0x6e), 0x08},
163 {CCI_REG8(0x6f), 0x08}, {CCI_REG8(0x70), 0x08}, {CCI_REG8(0x71), 0x08},
164 {CCI_REG8(0x76), 0x00}, {CCI_REG8(0x72), 0xf0}, {CCI_REG8(0x7e), 0x3c},
165 {CCI_REG8(0x7f), 0x00},
166 {GC2145_REG_PAGE_SELECT, 0x02},
167 {CCI_REG8(0x48), 0x15}, {CCI_REG8(0x49), 0x00}, {CCI_REG8(0x4b), 0x0b},
169 {GC2145_REG_PAGE_SELECT, 0x00},
171 {GC2145_REG_PAGE_SELECT, 0x01},
172 {CCI_REG8(0x01), 0x04}, {CCI_REG8(0x02), 0xc0}, {CCI_REG8(0x03), 0x04},
173 {CCI_REG8(0x04), 0x90}, {CCI_REG8(0x05), 0x30}, {CCI_REG8(0x06), 0x90},
174 {CCI_REG8(0x07), 0x30}, {CCI_REG8(0x08), 0x80}, {CCI_REG8(0x09), 0x00},
175 {CCI_REG8(0x0a), 0x82}, {CCI_REG8(0x0b), 0x11}, {CCI_REG8(0x0c), 0x10},
176 {CCI_REG8(0x11), 0x10}, {CCI_REG8(0x13), 0x7b}, {CCI_REG8(0x17), 0x00},
177 {CCI_REG8(0x1c), 0x11}, {CCI_REG8(0x1e), 0x61}, {CCI_REG8(0x1f), 0x35},
178 {CCI_REG8(0x20), 0x40}, {CCI_REG8(0x22), 0x40}, {CCI_REG8(0x23), 0x20},
179 {GC2145_REG_PAGE_SELECT, 0x02},
180 {CCI_REG8(0x0f), 0x04},
181 {GC2145_REG_PAGE_SELECT, 0x01},
182 {CCI_REG8(0x12), 0x35}, {CCI_REG8(0x15), 0xb0}, {CCI_REG8(0x10), 0x31},
183 {CCI_REG8(0x3e), 0x28}, {CCI_REG8(0x3f), 0xb0}, {CCI_REG8(0x40), 0x90},
184 {CCI_REG8(0x41), 0x0f},
186 {GC2145_REG_PAGE_SELECT, 0x02},
187 {CCI_REG8(0x90), 0x6c}, {CCI_REG8(0x91), 0x03}, {CCI_REG8(0x92), 0xcb},
188 {CCI_REG8(0x94), 0x33}, {CCI_REG8(0x95), 0x84}, {CCI_REG8(0x97), 0x65},
189 {CCI_REG8(0xa2), 0x11},
191 {GC2145_REG_PAGE_SELECT, 0x02},
192 {CCI_REG8(0x80), 0xc1}, {CCI_REG8(0x81), 0x08}, {CCI_REG8(0x82), 0x05},
193 {CCI_REG8(0x83), 0x08}, {CCI_REG8(0x84), 0x0a}, {CCI_REG8(0x86), 0xf0},
194 {CCI_REG8(0x87), 0x50}, {CCI_REG8(0x88), 0x15}, {CCI_REG8(0x89), 0xb0},
195 {CCI_REG8(0x8a), 0x30}, {CCI_REG8(0x8b), 0x10},
197 {GC2145_REG_PAGE_SELECT, 0x01},
198 {CCI_REG8(0x21), 0x04},
199 {GC2145_REG_PAGE_SELECT, 0x02},
200 {CCI_REG8(0xa3), 0x50}, {CCI_REG8(0xa4), 0x20}, {CCI_REG8(0xa5), 0x40},
201 {CCI_REG8(0xa6), 0x80}, {CCI_REG8(0xab), 0x40}, {CCI_REG8(0xae), 0x0c},
202 {CCI_REG8(0xb3), 0x46}, {CCI_REG8(0xb4), 0x64}, {CCI_REG8(0xb6), 0x38},
203 {CCI_REG8(0xb7), 0x01}, {CCI_REG8(0xb9), 0x2b}, {CCI_REG8(0x3c), 0x04},
204 {CCI_REG8(0x3d), 0x15}, {CCI_REG8(0x4b), 0x06}, {CCI_REG8(0x4c), 0x20},
206 {GC2145_REG_PAGE_SELECT, 0x02},
207 {CCI_REG8(0x10), 0x09}, {CCI_REG8(0x11), 0x0d}, {CCI_REG8(0x12), 0x13},
208 {CCI_REG8(0x13), 0x19}, {CCI_REG8(0x14), 0x27}, {CCI_REG8(0x15), 0x37},
209 {CCI_REG8(0x16), 0x45}, {CCI_REG8(0x17), 0x53}, {CCI_REG8(0x18), 0x69},
210 {CCI_REG8(0x19), 0x7d}, {CCI_REG8(0x1a), 0x8f}, {CCI_REG8(0x1b), 0x9d},
211 {CCI_REG8(0x1c), 0xa9}, {CCI_REG8(0x1d), 0xbd}, {CCI_REG8(0x1e), 0xcd},
212 {CCI_REG8(0x1f), 0xd9}, {CCI_REG8(0x20), 0xe3}, {CCI_REG8(0x21), 0xea},
213 {CCI_REG8(0x22), 0xef}, {CCI_REG8(0x23), 0xf5}, {CCI_REG8(0x24), 0xf9},
214 {CCI_REG8(0x25), 0xff},
215 {GC2145_REG_PAGE_SELECT, 0x00},
216 {CCI_REG8(0xc6), 0x20}, {CCI_REG8(0xc7), 0x2b},
218 {GC2145_REG_PAGE_SELECT, 0x02},
219 {CCI_REG8(0x26), 0x0f}, {CCI_REG8(0x27), 0x14}, {CCI_REG8(0x28), 0x19},
220 {CCI_REG8(0x29), 0x1e}, {CCI_REG8(0x2a), 0x27}, {CCI_REG8(0x2b), 0x33},
221 {CCI_REG8(0x2c), 0x3b}, {CCI_REG8(0x2d), 0x45}, {CCI_REG8(0x2e), 0x59},
222 {CCI_REG8(0x2f), 0x69}, {CCI_REG8(0x30), 0x7c}, {CCI_REG8(0x31), 0x89},
223 {CCI_REG8(0x32), 0x98}, {CCI_REG8(0x33), 0xae}, {CCI_REG8(0x34), 0xc0},
224 {CCI_REG8(0x35), 0xcf}, {CCI_REG8(0x36), 0xda}, {CCI_REG8(0x37), 0xe2},
225 {CCI_REG8(0x38), 0xe9}, {CCI_REG8(0x39), 0xf3}, {CCI_REG8(0x3a), 0xf9},
226 {CCI_REG8(0x3b), 0xff},
228 {GC2145_REG_PAGE_SELECT, 0x02},
229 {CCI_REG8(0xd1), 0x32}, {CCI_REG8(0xd2), 0x32}, {CCI_REG8(0xd3), 0x40},
230 {CCI_REG8(0xd6), 0xf0}, {CCI_REG8(0xd7), 0x10}, {CCI_REG8(0xd8), 0xda},
231 {CCI_REG8(0xdd), 0x14}, {CCI_REG8(0xde), 0x86}, {CCI_REG8(0xed), 0x80},
232 {CCI_REG8(0xee), 0x00}, {CCI_REG8(0xef), 0x3f}, {CCI_REG8(0xd8), 0xd8},
234 {GC2145_REG_PAGE_SELECT, 0x01},
235 {CCI_REG8(0x9f), 0x40},
237 {GC2145_REG_PAGE_SELECT, 0x01},
238 {CCI_REG8(0xc2), 0x14}, {CCI_REG8(0xc3), 0x0d}, {CCI_REG8(0xc4), 0x0c},
239 {CCI_REG8(0xc8), 0x15}, {CCI_REG8(0xc9), 0x0d}, {CCI_REG8(0xca), 0x0a},
240 {CCI_REG8(0xbc), 0x24}, {CCI_REG8(0xbd), 0x10}, {CCI_REG8(0xbe), 0x0b},
241 {CCI_REG8(0xb6), 0x25}, {CCI_REG8(0xb7), 0x16}, {CCI_REG8(0xb8), 0x15},
242 {CCI_REG8(0xc5), 0x00}, {CCI_REG8(0xc6), 0x00}, {CCI_REG8(0xc7), 0x00},
243 {CCI_REG8(0xcb), 0x00}, {CCI_REG8(0xcc), 0x00}, {CCI_REG8(0xcd), 0x00},
244 {CCI_REG8(0xbf), 0x07}, {CCI_REG8(0xc0), 0x00}, {CCI_REG8(0xc1), 0x00},
245 {CCI_REG8(0xb9), 0x00}, {CCI_REG8(0xba), 0x00}, {CCI_REG8(0xbb), 0x00},
246 {CCI_REG8(0xaa), 0x01}, {CCI_REG8(0xab), 0x01}, {CCI_REG8(0xac), 0x00},
247 {CCI_REG8(0xad), 0x05}, {CCI_REG8(0xae), 0x06}, {CCI_REG8(0xaf), 0x0e},
248 {CCI_REG8(0xb0), 0x0b}, {CCI_REG8(0xb1), 0x07}, {CCI_REG8(0xb2), 0x06},
249 {CCI_REG8(0xb3), 0x17}, {CCI_REG8(0xb4), 0x0e}, {CCI_REG8(0xb5), 0x0e},
250 {CCI_REG8(0xd0), 0x09}, {CCI_REG8(0xd1), 0x00}, {CCI_REG8(0xd2), 0x00},
251 {CCI_REG8(0xd6), 0x08}, {CCI_REG8(0xd7), 0x00}, {CCI_REG8(0xd8), 0x00},
252 {CCI_REG8(0xd9), 0x00}, {CCI_REG8(0xda), 0x00}, {CCI_REG8(0xdb), 0x00},
253 {CCI_REG8(0xd3), 0x0a}, {CCI_REG8(0xd4), 0x00}, {CCI_REG8(0xd5), 0x00},
254 {CCI_REG8(0xa4), 0x00}, {CCI_REG8(0xa5), 0x00}, {CCI_REG8(0xa6), 0x77},
255 {CCI_REG8(0xa7), 0x77}, {CCI_REG8(0xa8), 0x77}, {CCI_REG8(0xa9), 0x77},
256 {CCI_REG8(0xa1), 0x80}, {CCI_REG8(0xa2), 0x80},
257 {GC2145_REG_PAGE_SELECT, 0x01},
258 {CCI_REG8(0xdf), 0x0d}, {CCI_REG8(0xdc), 0x25}, {CCI_REG8(0xdd), 0x30},
259 {CCI_REG8(0xe0), 0x77}, {CCI_REG8(0xe1), 0x80}, {CCI_REG8(0xe2), 0x77},
260 {CCI_REG8(0xe3), 0x90}, {CCI_REG8(0xe6), 0x90}, {CCI_REG8(0xe7), 0xa0},
261 {CCI_REG8(0xe8), 0x90}, {CCI_REG8(0xe9), 0xa0},
264 {GC2145_REG_PAGE_SELECT, 0x00},
265 {CCI_REG8(0xec), 0x06}, {CCI_REG8(0xed), 0x04}, {CCI_REG8(0xee), 0x60},
266 {CCI_REG8(0xef), 0x90}, {CCI_REG8(0xb6), 0x01},
267 {GC2145_REG_PAGE_SELECT, 0x01},
268 {CCI_REG8(0x4f), 0x00}, {CCI_REG8(0x4f), 0x00}, {CCI_REG8(0x4b), 0x01},
269 {CCI_REG8(0x4f), 0x00},
270 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x71}, {CCI_REG8(0x4e), 0x01},
271 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x91}, {CCI_REG8(0x4e), 0x01},
272 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x70}, {CCI_REG8(0x4e), 0x01},
273 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x90}, {CCI_REG8(0x4e), 0x02},
274 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xb0}, {CCI_REG8(0x4e), 0x02},
275 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8f}, {CCI_REG8(0x4e), 0x02},
276 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6f}, {CCI_REG8(0x4e), 0x02},
277 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xaf}, {CCI_REG8(0x4e), 0x02},
278 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xd0}, {CCI_REG8(0x4e), 0x02},
279 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xf0}, {CCI_REG8(0x4e), 0x02},
280 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcf}, {CCI_REG8(0x4e), 0x02},
281 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xef}, {CCI_REG8(0x4e), 0x02},
282 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6e}, {CCI_REG8(0x4e), 0x03},
283 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8e}, {CCI_REG8(0x4e), 0x03},
284 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xae}, {CCI_REG8(0x4e), 0x03},
285 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xce}, {CCI_REG8(0x4e), 0x03},
286 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4d}, {CCI_REG8(0x4e), 0x03},
287 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6d}, {CCI_REG8(0x4e), 0x03},
288 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8d}, {CCI_REG8(0x4e), 0x03},
289 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xad}, {CCI_REG8(0x4e), 0x03},
290 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcd}, {CCI_REG8(0x4e), 0x03},
291 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4c}, {CCI_REG8(0x4e), 0x03},
292 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6c}, {CCI_REG8(0x4e), 0x03},
293 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8c}, {CCI_REG8(0x4e), 0x03},
294 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xac}, {CCI_REG8(0x4e), 0x03},
295 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcc}, {CCI_REG8(0x4e), 0x03},
296 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xcb}, {CCI_REG8(0x4e), 0x03},
297 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x4b}, {CCI_REG8(0x4e), 0x03},
298 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x6b}, {CCI_REG8(0x4e), 0x03},
299 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8b}, {CCI_REG8(0x4e), 0x03},
300 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xab}, {CCI_REG8(0x4e), 0x03},
301 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x04},
302 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xaa}, {CCI_REG8(0x4e), 0x04},
303 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x04},
304 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x04},
305 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xc9}, {CCI_REG8(0x4e), 0x04},
306 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x04},
307 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0x89}, {CCI_REG8(0x4e), 0x04},
308 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xa9}, {CCI_REG8(0x4e), 0x04},
309 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x0b}, {CCI_REG8(0x4e), 0x05},
310 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x0a}, {CCI_REG8(0x4e), 0x05},
311 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xeb}, {CCI_REG8(0x4e), 0x05},
312 {CCI_REG8(0x4c), 0x01}, {CCI_REG8(0x4d), 0xea}, {CCI_REG8(0x4e), 0x05},
313 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x09}, {CCI_REG8(0x4e), 0x05},
314 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x29}, {CCI_REG8(0x4e), 0x05},
315 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x2a}, {CCI_REG8(0x4e), 0x05},
316 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x4a}, {CCI_REG8(0x4e), 0x05},
317 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x8a}, {CCI_REG8(0x4e), 0x06},
318 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x49}, {CCI_REG8(0x4e), 0x06},
319 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x69}, {CCI_REG8(0x4e), 0x06},
320 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x89}, {CCI_REG8(0x4e), 0x06},
321 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xa9}, {CCI_REG8(0x4e), 0x06},
322 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x48}, {CCI_REG8(0x4e), 0x06},
323 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x68}, {CCI_REG8(0x4e), 0x06},
324 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0x69}, {CCI_REG8(0x4e), 0x06},
325 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xca}, {CCI_REG8(0x4e), 0x07},
326 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc9}, {CCI_REG8(0x4e), 0x07},
327 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe9}, {CCI_REG8(0x4e), 0x07},
328 {CCI_REG8(0x4c), 0x03}, {CCI_REG8(0x4d), 0x09}, {CCI_REG8(0x4e), 0x07},
329 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc8}, {CCI_REG8(0x4e), 0x07},
330 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe8}, {CCI_REG8(0x4e), 0x07},
331 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xa7}, {CCI_REG8(0x4e), 0x07},
332 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xc7}, {CCI_REG8(0x4e), 0x07},
333 {CCI_REG8(0x4c), 0x02}, {CCI_REG8(0x4d), 0xe7}, {CCI_REG8(0x4e), 0x07},
334 {CCI_REG8(0x4c), 0x03}, {CCI_REG8(0x4d), 0x07}, {CCI_REG8(0x4e), 0x07},
335 {CCI_REG8(0x4f), 0x01},
336 {CCI_REG8(0x50), 0x80}, {CCI_REG8(0x51), 0xa8}, {CCI_REG8(0x52), 0x47},
337 {CCI_REG8(0x53), 0x38}, {CCI_REG8(0x54), 0xc7}, {CCI_REG8(0x56), 0x0e},
338 {CCI_REG8(0x58), 0x08}, {CCI_REG8(0x5b), 0x00}, {CCI_REG8(0x5c), 0x74},
339 {CCI_REG8(0x5d), 0x8b}, {CCI_REG8(0x61), 0xdb}, {CCI_REG8(0x62), 0xb8},
340 {CCI_REG8(0x63), 0x86}, {CCI_REG8(0x64), 0xc0}, {CCI_REG8(0x65), 0x04},
341 {CCI_REG8(0x67), 0xa8}, {CCI_REG8(0x68), 0xb0}, {CCI_REG8(0x69), 0x00},
342 {CCI_REG8(0x6a), 0xa8}, {CCI_REG8(0x6b), 0xb0}, {CCI_REG8(0x6c), 0xaf},
343 {CCI_REG8(0x6d), 0x8b}, {CCI_REG8(0x6e), 0x50}, {CCI_REG8(0x6f), 0x18},
344 {CCI_REG8(0x73), 0xf0}, {CCI_REG8(0x70), 0x0d}, {CCI_REG8(0x71), 0x60},
345 {CCI_REG8(0x72), 0x80}, {CCI_REG8(0x74), 0x01}, {CCI_REG8(0x75), 0x01},
346 {CCI_REG8(0x7f), 0x0c}, {CCI_REG8(0x76), 0x70}, {CCI_REG8(0x77), 0x58},
347 {CCI_REG8(0x78), 0xa0}, {CCI_REG8(0x79), 0x5e}, {CCI_REG8(0x7a), 0x54},
348 {CCI_REG8(0x7b), 0x58},
350 {GC2145_REG_PAGE_SELECT, 0x02},
351 {CCI_REG8(0xc0), 0x01}, {CCI_REG8(0xc1), 0x44}, {CCI_REG8(0xc2), 0xfd},
352 {CCI_REG8(0xc3), 0x04}, {CCI_REG8(0xc4), 0xf0}, {CCI_REG8(0xc5), 0x48},
353 {CCI_REG8(0xc6), 0xfd}, {CCI_REG8(0xc7), 0x46}, {CCI_REG8(0xc8), 0xfd},
354 {CCI_REG8(0xc9), 0x02}, {CCI_REG8(0xca), 0xe0}, {CCI_REG8(0xcb), 0x45},
355 {CCI_REG8(0xcc), 0xec}, {CCI_REG8(0xcd), 0x48}, {CCI_REG8(0xce), 0xf0},
356 {CCI_REG8(0xcf), 0xf0}, {CCI_REG8(0xe3), 0x0c}, {CCI_REG8(0xe4), 0x4b},
357 {CCI_REG8(0xe5), 0xe0},
359 {GC2145_REG_PAGE_SELECT, 0x01},
360 {CCI_REG8(0x9f), 0x40},
362 {GC2145_REG_PAGE_SELECT, 0x02},
363 {CCI_REG8(0x40), 0xbf}, {CCI_REG8(0x46), 0xcf},
368 #define GC2145_640_480_HBLANK 0x0130
369 #define GC2145_640_480_VBLANK 0x000c
371 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},
372 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},
373 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x86},
374 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},
376 {GC2145_REG_PAD_IO, 0x00},
377 {GC2145_REG_PAGE_SELECT, 0x00},
378 /* Row/Col start - 0/0 */
379 {GC2145_REG_ROW_START, 0x0000},
380 {GC2145_REG_COL_START, 0x0000},
382 {GC2145_REG_WIN_HEIGHT, 0x04c0},
383 {GC2145_REG_WIN_WIDTH, 0x0652},
385 {CCI_REG8(0xfd), 0x01}, {CCI_REG8(0xfa), 0x00},
386 /* Crop 640-480@0-0 */
387 {GC2145_REG_CROP_ENABLE, 0x01},
388 {GC2145_REG_CROP_Y, 0x0000},
389 {GC2145_REG_CROP_X, 0x0000},
390 {GC2145_REG_CROP_HEIGHT, 0x01e0},
391 {GC2145_REG_CROP_WIDTH, 0x0280},
393 {CCI_REG8(0x99), 0x55}, {CCI_REG8(0x9a), 0x06}, {CCI_REG8(0x9b), 0x01},
394 {CCI_REG8(0x9c), 0x23}, {CCI_REG8(0x9d), 0x00}, {CCI_REG8(0x9e), 0x00},
395 {CCI_REG8(0x9f), 0x01}, {CCI_REG8(0xa0), 0x23}, {CCI_REG8(0xa1), 0x00},
396 {CCI_REG8(0xa2), 0x00},
397 {GC2145_REG_PAGE_SELECT, 0x01},
399 {CCI_REG16(0x25), 0x0175},
401 {CCI_REG16(0x27), 0x045f}, {CCI_REG16(0x29), 0x045f},
402 {CCI_REG16(0x2b), 0x045f}, {CCI_REG16(0x2d), 0x045f},
407 #define GC2145_1280_720_HBLANK 0x0156
408 #define GC2145_1280_720_VBLANK 0x0011
410 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},
411 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},
412 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x83},
413 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},
415 {GC2145_REG_PAD_IO, 0x00},
416 {GC2145_REG_PAGE_SELECT, 0x00},
418 {GC2145_REG_ROW_START, 0x00f0},
419 {GC2145_REG_COL_START, 0x00a0},
421 {GC2145_REG_WIN_HEIGHT, 0x02e0},
422 {GC2145_REG_WIN_WIDTH, 0x0510},
423 /* Crop 1280-720@0-0 */
424 {GC2145_REG_CROP_ENABLE, 0x01},
425 {GC2145_REG_CROP_Y, 0x0000},
426 {GC2145_REG_CROP_X, 0x0000},
427 {GC2145_REG_CROP_HEIGHT, 0x02d0},
428 {GC2145_REG_CROP_WIDTH, 0x0500},
429 {GC2145_REG_PAGE_SELECT, 0x01},
431 {CCI_REG16(0x25), 0x00e6},
433 {CCI_REG16(0x27), 0x02b2}, {CCI_REG16(0x29), 0x02b2},
434 {CCI_REG16(0x2b), 0x02b2}, {CCI_REG16(0x2d), 0x02b2},
439 #define GC2145_1600_1200_HBLANK 0x0156
440 #define GC2145_1600_1200_VBLANK 0x0010
442 {GC2145_REG_PAGE_SELECT, 0xf0}, {GC2145_REG_PAGE_SELECT, 0xf0},
443 {GC2145_REG_PAGE_SELECT, 0xf0}, {CCI_REG8(0xfc), 0x06},
444 {CCI_REG8(0xf6), 0x00}, {CCI_REG8(0xf7), 0x1d}, {CCI_REG8(0xf8), 0x84},
445 {CCI_REG8(0xfa), 0x00}, {CCI_REG8(0xf9), 0x8e},
447 {GC2145_REG_PAD_IO, 0x00},
448 {GC2145_REG_PAGE_SELECT, 0x00},
449 /* Row/Col start - 0/0 */
450 {GC2145_REG_ROW_START, 0x0000},
451 {GC2145_REG_COL_START, 0x0000},
453 {GC2145_REG_WIN_HEIGHT, 0x04c0},
454 {GC2145_REG_WIN_WIDTH, 0x0652},
455 /* Crop 1600-1200@0-0 */
456 {GC2145_REG_CROP_ENABLE, 0x01},
457 {GC2145_REG_CROP_Y, 0x0000},
458 {GC2145_REG_CROP_X, 0x0000},
459 {GC2145_REG_CROP_HEIGHT, 0x04b0},
460 {GC2145_REG_CROP_WIDTH, 0x0640},
461 {GC2145_REG_PAGE_SELECT, 0x01},
463 {CCI_REG16(0x25), 0x00fa},
465 {CCI_REG16(0x27), 0x04e2}, {CCI_REG16(0x29), 0x04e2},
466 {CCI_REG16(0x2b), 0x04e2}, {CCI_REG16(0x2d), 0x04e2},
485 #define GC2145_MODE_640X480 0
497 .top = 0,
498 .left = 0,
531 .top = 0,
532 .left = 0,
561 .output_fmt = 0x00,
566 .output_fmt = 0x01,
571 .output_fmt = 0x02,
576 .output_fmt = 0x03,
581 .output_fmt = 0x06,
631 for (i = 0; i < ARRAY_SIZE(supported_formats); i++) { in gc2145_get_format_code()
637 i = 0; in gc2145_get_format_code()
664 format = v4l2_subdev_state_get_format(state, 0); in gc2145_init_state()
665 gc2145_update_pad_format(gc2145, &supported_modes[0], format, in gc2145_init_state()
669 crop = v4l2_subdev_state_get_crop(state, 0); in gc2145_init_state()
670 *crop = supported_modes[0].crop; in gc2145_init_state()
672 return 0; in gc2145_init_state()
681 sel->r = *v4l2_subdev_state_get_crop(sd_state, 0); in gc2145_get_selection()
682 return 0; in gc2145_get_selection()
685 sel->r.top = 0; in gc2145_get_selection()
686 sel->r.left = 0; in gc2145_get_selection()
690 return 0; in gc2145_get_selection()
694 sel->r.top = 0; in gc2145_get_selection()
695 sel->r.left = 0; in gc2145_get_selection()
699 return 0; in gc2145_get_selection()
713 return 0; in gc2145_enum_mbus_code()
737 return 0; in gc2145_enum_frame_size()
773 return 0; in gc2145_set_pad_format()
777 {GC2145_REG_PAGE_SELECT, 0x03},
784 {GC2145_REG_DPHY_ANALOG_MODE3, GC2145_DPHY_LANE1_DIFF(0) |
790 {GC2145_REG_T_LPX, 0x10},
791 {GC2145_REG_T_CLK_HS_PREPARE, 0x04}, {GC2145_REG_T_CLK_ZERO, 0x10},
792 {GC2145_REG_T_CLK_PRE, 0x10}, {GC2145_REG_T_CLK_POST, 0x10},
793 {GC2145_REG_T_CLK_TRAIL, 0x05},
794 {GC2145_REG_T_HS_PREPARE, 0x03}, {GC2145_REG_T_HS_ZERO, 0x0a},
795 {GC2145_REG_T_HS_TRAIL, 0x06},
802 int ret = 0; in gc2145_config_mipi_mode()
816 cci_write(gc2145->regmap, GC2145_REG_LWC_LOW, lwc & 0xff, &ret); in gc2145_config_mipi_mode()
820 * 640x480 RGB: 0x0190 in gc2145_config_mipi_mode()
821 * 1280x720 / 1600x1200 (aka no scaler) non RAW: 0x0001 in gc2145_config_mipi_mode()
822 * 1600x1200 RAW: 0x0190 in gc2145_config_mipi_mode()
825 fifo_full_lvl = 0x0001; in gc2145_config_mipi_mode()
827 fifo_full_lvl = 0x0190; in gc2145_config_mipi_mode()
832 fifo_full_lvl & 0xff, &ret); in gc2145_config_mipi_mode()
836 * 0xf1 in case of RAW mode and 0xf0 otherwise in gc2145_config_mipi_mode()
838 cci_write(gc2145->regmap, GC2145_REG_FIFO_GATE_MODE, 0xf0, &ret); in gc2145_config_mipi_mode()
861 if (ret < 0) in gc2145_start_streaming()
874 fmt = v4l2_subdev_state_get_format(state, 0); in gc2145_start_streaming()
878 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret); in gc2145_start_streaming()
885 : 0, &ret); in gc2145_start_streaming()
906 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret); in gc2145_start_streaming()
908 return 0; in gc2145_start_streaming()
919 int ret = 0; in gc2145_stop_streaming()
922 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x03, &ret); in gc2145_stop_streaming()
924 GC2145_CSI2_MODE_EN | GC2145_CSI2_MODE_MIPI_EN, 0, in gc2145_stop_streaming()
926 cci_write(gc2145->regmap, GC2145_REG_PAGE_SELECT, 0x00, &ret); in gc2145_stop_streaming()
938 int ret = 0; in gc2145_set_stream()
971 gpiod_set_value_cansleep(gc2145->powerdown_gpio, 0); in gc2145_power_on()
972 gpiod_set_value_cansleep(gc2145->reset_gpio, 0); in gc2145_power_on()
981 return 0; in gc2145_power_on()
999 return 0; in gc2145_power_off()
1007 for (i = 0; i < GC2145_NUM_SUPPLIES; i++) in gc2145_get_regulators()
1033 return 0; in gc2145_identify_module()
1048 #define GC2145_TEST_PATTERN_ENABLE BIT(0)
1058 #define GC2145_TEST_BLACK (0)
1061 0,
1101 int ret = 0; in gc2145_set_ctrl_test_pattern()
1105 cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE2, 0, &ret); in gc2145_set_ctrl_test_pattern()
1106 return cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE3, 0, in gc2145_set_ctrl_test_pattern()
1115 return cci_write(gc2145->regmap, GC2145_REG_DEBUG_MODE3, 0, in gc2145_set_ctrl_test_pattern()
1130 if (pm_runtime_get_if_in_use(&client->dev) == 0) in gc2145_s_ctrl()
1131 return 0; in gc2145_s_ctrl()
1147 BIT(0), (ctrl->val ? BIT(0) : 0), NULL); in gc2145_s_ctrl()
1151 BIT(1), (ctrl->val ? BIT(1) : 0), NULL); in gc2145_s_ctrl()
1185 supported_modes[0].pixel_rate); in gc2145_init_controls()
1189 0, gc2145_link_freq_menu); in gc2145_init_controls()
1194 0, 0xfff, 1, GC2145_640_480_HBLANK); in gc2145_init_controls()
1197 0, 0x1fff, 1, GC2145_640_480_VBLANK); in gc2145_init_controls()
1202 0, 0, test_pattern_menu); in gc2145_init_controls()
1204 0, 1, 1, 0); in gc2145_init_controls()
1206 0, 1, 1, 0); in gc2145_init_controls()
1225 return 0; in gc2145_init_controls()
1267 ep_cfg.link_frequencies[0] != GC2145_640_480_LINKFREQ || in gc2145_check_hwcfg()
1349 gc2145->mode = &supported_modes[0]; in gc2145_probe()
1371 if (ret < 0) { in gc2145_probe()
1386 if (ret < 0) { in gc2145_probe()
1391 return 0; in gc2145_probe()