Lines Matching +full:mbox +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0
26 /* TX0/RX0/RXDB[0-3] */
37 /* Please not change TX & RX */
40 IMX_MU_TYPE_RX = 1, /* Rx */
42 IMX_MU_TYPE_RXDB = 3, /* Rx doorbell */
88 struct mbox_controller mbox; member
111 int (*rx)(struct imx_mu_priv *priv, struct imx_mu_con_priv *cp); member
121 #define IMX_MU_xSR_GIPn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
122 #define IMX_MU_xSR_RFn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
123 #define IMX_MU_xSR_TEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
126 #define IMX_MU_xCR_GIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(28 + (3 - (x))))
128 #define IMX_MU_xCR_RIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(24 + (3 - (x))))
130 #define IMX_MU_xCR_TIEn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(20 + (3 - (x))))
132 #define IMX_MU_xCR_GIRn(type, x) (type & IMX_MU_V2 ? BIT(x) : BIT(16 + (3 - (x))))
138 static struct imx_mu_priv *to_imx_mu_priv(struct mbox_controller *mbox) in to_imx_mu_priv() argument
140 return container_of(mbox, struct imx_mu_priv, mbox); in to_imx_mu_priv()
145 iowrite32(val, priv->base + offs); in imx_mu_write()
150 return ioread32(priv->base + offs); in imx_mu_read()
159 dev_dbg(priv->dev, "Trying to write %.8x to idx %d\n", val, idx); in imx_mu_tx_waiting_write()
162 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_tx_waiting_write()
163 can_write = status & IMX_MU_xSR_TEn(priv->dcfg->type, idx % 4); in imx_mu_tx_waiting_write()
167 dev_err(priv->dev, "timeout trying to write %.8x at %d(%.8x)\n", in imx_mu_tx_waiting_write()
169 return -ETIME; in imx_mu_tx_waiting_write()
172 imx_mu_write(priv, val, priv->dcfg->xTR + (idx % 4) * 4); in imx_mu_tx_waiting_write()
183 dev_dbg(priv->dev, "Trying to read from idx %d\n", idx); in imx_mu_rx_waiting_read()
186 status = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_rx_waiting_read()
187 can_read = status & IMX_MU_xSR_RFn(priv->dcfg->type, idx % 4); in imx_mu_rx_waiting_read()
191 dev_err(priv->dev, "timeout trying to read idx %d (%.8x)\n", in imx_mu_rx_waiting_read()
193 return -ETIME; in imx_mu_rx_waiting_read()
196 *val = imx_mu_read(priv, priv->dcfg->xRR + (idx % 4) * 4); in imx_mu_rx_waiting_read()
197 dev_dbg(priv->dev, "Read %.8x\n", *val); in imx_mu_rx_waiting_read()
207 spin_lock_irqsave(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
208 val = imx_mu_read(priv, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
211 imx_mu_write(priv, val, priv->dcfg->xCR[type]); in imx_mu_xcr_rmw()
212 spin_unlock_irqrestore(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
223 switch (cp->type) { in imx_mu_generic_tx()
225 imx_mu_write(priv, *arg, priv->dcfg->xTR + cp->idx * 4); in imx_mu_generic_tx()
226 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_generic_tx()
229 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); in imx_mu_generic_tx()
230 tasklet_schedule(&cp->txdb_tasklet); in imx_mu_generic_tx()
233 imx_mu_xcr_rmw(priv, IMX_MU_GCR, IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); in imx_mu_generic_tx()
236 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_generic_tx()
237 return -EINVAL; in imx_mu_generic_tx()
248 dat = imx_mu_read(priv, priv->dcfg->xRR + (cp->idx) * 4); in imx_mu_generic_rx()
249 mbox_chan_received_data(cp->chan, (void *)&dat); in imx_mu_generic_rx()
257 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), in imx_mu_generic_rxdb()
258 priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_generic_rxdb()
259 mbox_chan_received_data(cp->chan, NULL); in imx_mu_generic_rxdb()
271 if (priv->dcfg->type & IMX_MU_V2_S4) { in imx_mu_specific_tx()
272 size = ((struct imx_s4_rpc_msg_max *)data)->hdr.size; in imx_mu_specific_tx()
276 size = ((struct imx_sc_rpc_msg_max *)data)->hdr.size; in imx_mu_specific_tx()
281 switch (cp->type) { in imx_mu_specific_tx()
284 * msg->hdr.size specifies the number of u32 words while in imx_mu_specific_tx()
293 …dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on TX; got: %i bytes\n", max_size, si… in imx_mu_specific_tx()
294 return -EINVAL; in imx_mu_specific_tx()
298 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); in imx_mu_specific_tx()
300 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_TSR], in imx_mu_specific_tx()
302 xsr & IMX_MU_xSR_TEn(priv->dcfg->type, i % num_tr), in imx_mu_specific_tx()
305 dev_err(priv->dev, "Send data index: %d timeout\n", i); in imx_mu_specific_tx()
308 imx_mu_write(priv, *arg++, priv->dcfg->xTR + (i % num_tr) * 4); in imx_mu_specific_tx()
311 imx_mu_xcr_rmw(priv, IMX_MU_TCR, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_specific_tx()
314 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_specific_tx()
315 return -EINVAL; in imx_mu_specific_tx()
328 data = (u32 *)priv->msg; in imx_mu_specific_rx()
330 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, 0)); in imx_mu_specific_rx()
331 *data++ = imx_mu_read(priv, priv->dcfg->xRR); in imx_mu_specific_rx()
333 if (priv->dcfg->type & IMX_MU_V2_S4) { in imx_mu_specific_rx()
334 size = ((struct imx_s4_rpc_msg_max *)priv->msg)->hdr.size; in imx_mu_specific_rx()
337 size = ((struct imx_sc_rpc_msg_max *)priv->msg)->hdr.size; in imx_mu_specific_rx()
342 …dev_err(priv->dev, "Maximal message size (%u bytes) exceeded on RX; got: %i bytes\n", max_size, si… in imx_mu_specific_rx()
343 return -EINVAL; in imx_mu_specific_rx()
347 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_RSR], xsr, in imx_mu_specific_rx()
348 xsr & IMX_MU_xSR_RFn(priv->dcfg->type, i % 4), 0, in imx_mu_specific_rx()
351 dev_err(priv->dev, "timeout read idx %d\n", i); in imx_mu_specific_rx()
354 *data++ = imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); in imx_mu_specific_rx()
357 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, 0), 0); in imx_mu_specific_rx()
358 mbox_chan_received_data(cp->chan, (void *)priv->msg); in imx_mu_specific_rx()
372 dev_dbg(priv->dev, "Sending message\n"); in imx_mu_seco_tx()
374 switch (cp->type) { in imx_mu_seco_tx()
376 byte_size = msg->hdr.size * sizeof(u32); in imx_mu_seco_tx()
382 dev_err(priv->dev, in imx_mu_seco_tx()
385 return -EINVAL; in imx_mu_seco_tx()
392 dev_dbg(priv->dev, "Sending header\n"); in imx_mu_seco_tx()
393 imx_mu_write(priv, *arg++, priv->dcfg->xTR); in imx_mu_seco_tx()
396 dev_dbg(priv->dev, "Sending signaling\n"); in imx_mu_seco_tx()
398 IMX_MU_xCR_GIRn(priv->dcfg->type, cp->idx), 0); in imx_mu_seco_tx()
401 for (i = 1; i < 4 && i < msg->hdr.size; i++) { in imx_mu_seco_tx()
402 dev_dbg(priv->dev, "Sending word %d\n", i); in imx_mu_seco_tx()
404 priv->dcfg->xTR + (i % 4) * 4); in imx_mu_seco_tx()
408 for (; i < msg->hdr.size; i++) { in imx_mu_seco_tx()
409 dev_dbg(priv->dev, "Sending word %d\n", i); in imx_mu_seco_tx()
412 dev_err(priv->dev, "Timeout tx %d\n", i); in imx_mu_seco_tx()
417 /* Simulate hack for mbox framework */ in imx_mu_seco_tx()
418 tasklet_schedule(&cp->txdb_tasklet); in imx_mu_seco_tx()
422 dev_warn_ratelimited(priv->dev, in imx_mu_seco_tx()
424 cp->type); in imx_mu_seco_tx()
425 return -EINVAL; in imx_mu_seco_tx()
439 dev_dbg(priv->dev, "Receiving message\n"); in imx_mu_seco_rxdb()
442 dev_dbg(priv->dev, "Receiving header\n"); in imx_mu_seco_rxdb()
443 *data++ = imx_mu_read(priv, priv->dcfg->xRR); in imx_mu_seco_rxdb()
446 dev_err(priv->dev, "Exceed max msg size (%zu) on RX, got: %i\n", in imx_mu_seco_rxdb()
448 err = -EINVAL; in imx_mu_seco_rxdb()
454 dev_dbg(priv->dev, "Receiving word %d\n", i); in imx_mu_seco_rxdb()
457 dev_err(priv->dev, "Timeout rx %d\n", i); in imx_mu_seco_rxdb()
463 imx_mu_write(priv, IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx), in imx_mu_seco_rxdb()
464 priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_seco_rxdb()
470 dev_dbg(priv->dev, "Sending message to client\n"); in imx_mu_seco_rxdb()
471 mbox_chan_received_data(cp->chan, (void *)&msg); in imx_mu_seco_rxdb()
476 mbox_chan_received_data(cp->chan, ERR_PTR(err)); in imx_mu_seco_rxdb()
486 mbox_chan_txdone(cp->chan, 0); in imx_mu_txdb_tasklet()
492 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_isr()
493 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_isr()
496 switch (cp->type) { in imx_mu_isr()
498 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_TCR]); in imx_mu_isr()
499 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_TSR]); in imx_mu_isr()
500 val &= IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
501 (ctrl & IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
504 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_RCR]); in imx_mu_isr()
505 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_RSR]); in imx_mu_isr()
506 val &= IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
507 (ctrl & IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
510 ctrl = imx_mu_read(priv, priv->dcfg->xCR[IMX_MU_GIER]); in imx_mu_isr()
511 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_isr()
512 val &= IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx) & in imx_mu_isr()
513 (ctrl & IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
518 dev_warn_ratelimited(priv->dev, "Unhandled channel type %d\n", in imx_mu_isr()
519 cp->type); in imx_mu_isr()
526 if ((val == IMX_MU_xSR_TEn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
527 (cp->type == IMX_MU_TYPE_TX)) { in imx_mu_isr()
528 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_isr()
530 } else if ((val == IMX_MU_xSR_RFn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
531 (cp->type == IMX_MU_TYPE_RX)) { in imx_mu_isr()
532 priv->dcfg->rx(priv, cp); in imx_mu_isr()
533 } else if ((val == IMX_MU_xSR_GIPn(priv->dcfg->type, cp->idx)) && in imx_mu_isr()
534 (cp->type == IMX_MU_TYPE_RXDB)) { in imx_mu_isr()
535 priv->dcfg->rxdb(priv, cp); in imx_mu_isr()
537 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); in imx_mu_isr()
541 if (priv->suspend) in imx_mu_isr()
549 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_send_data()
550 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_send_data()
552 return priv->dcfg->tx(priv, cp, data); in imx_mu_send_data()
557 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_startup()
558 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_startup()
562 pm_runtime_get_sync(priv->dev); in imx_mu_startup()
563 if (cp->type == IMX_MU_TYPE_TXDB_V2) in imx_mu_startup()
566 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_startup()
568 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, in imx_mu_startup()
574 if (!priv->dev->pm_domain) in imx_mu_startup()
577 if (!(priv->dcfg->type & IMX_MU_V2_IRQ)) in imx_mu_startup()
580 ret = request_irq(priv->irq[cp->type], imx_mu_isr, irq_flag, cp->irq_desc, chan); in imx_mu_startup()
582 dev_err(priv->dev, "Unable to acquire IRQ %d\n", priv->irq[cp->type]); in imx_mu_startup()
586 switch (cp->type) { in imx_mu_startup()
588 imx_mu_xcr_rmw(priv, IMX_MU_RCR, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_startup()
591 imx_mu_xcr_rmw(priv, IMX_MU_GIER, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx), 0); in imx_mu_startup()
602 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_shutdown()
603 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_shutdown()
607 if (cp->type == IMX_MU_TYPE_TXDB_V2) { in imx_mu_shutdown()
608 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
612 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_shutdown()
613 tasklet_kill(&cp->txdb_tasklet); in imx_mu_shutdown()
614 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
618 switch (cp->type) { in imx_mu_shutdown()
620 imx_mu_xcr_rmw(priv, IMX_MU_TCR, 0, IMX_MU_xCR_TIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
623 imx_mu_xcr_rmw(priv, IMX_MU_RCR, 0, IMX_MU_xCR_RIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
626 imx_mu_xcr_rmw(priv, IMX_MU_GIER, 0, IMX_MU_xCR_GIEn(priv->dcfg->type, cp->idx)); in imx_mu_shutdown()
629 imx_mu_xcr_rmw(priv, IMX_MU_CR, IMX_MU_xCR_RST(priv->dcfg->type), 0); in imx_mu_shutdown()
630 ret = readl_poll_timeout(priv->base + priv->dcfg->xSR[IMX_MU_SR], sr, in imx_mu_shutdown()
631 !(sr & IMX_MU_xSR_RST(priv->dcfg->type)), 1, 5); in imx_mu_shutdown()
633 dev_warn(priv->dev, "RST channel timeout\n"); in imx_mu_shutdown()
639 free_irq(priv->irq[cp->type], chan); in imx_mu_shutdown()
640 pm_runtime_put_sync(priv->dev); in imx_mu_shutdown()
649 static struct mbox_chan *imx_mu_specific_xlate(struct mbox_controller *mbox, in imx_mu_specific_xlate() argument
654 if (sp->args_count != 2) { in imx_mu_specific_xlate()
655 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_specific_xlate()
656 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
659 type = sp->args[0]; /* channel type */ in imx_mu_specific_xlate()
660 idx = sp->args[1]; /* index */ in imx_mu_specific_xlate()
666 dev_err(mbox->dev, "Invalid chan idx: %d\n", idx); in imx_mu_specific_xlate()
673 dev_err(mbox->dev, "Invalid chan type: %d\n", type); in imx_mu_specific_xlate()
674 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
677 if (chan >= mbox->num_chans) { in imx_mu_specific_xlate()
678 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_specific_xlate()
679 return ERR_PTR(-EINVAL); in imx_mu_specific_xlate()
682 return &mbox->chans[chan]; in imx_mu_specific_xlate()
685 static struct mbox_chan * imx_mu_xlate(struct mbox_controller *mbox, in imx_mu_xlate() argument
691 if (sp->args_count != 2) { in imx_mu_xlate()
692 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_xlate()
693 return ERR_PTR(-EINVAL); in imx_mu_xlate()
696 type = sp->args[0]; /* channel type */ in imx_mu_xlate()
697 idx = sp->args[1]; /* index */ in imx_mu_xlate()
701 dev_err(mbox->dev, "Invalid RST channel %d\n", idx); in imx_mu_xlate()
702 return ERR_PTR(-EINVAL); in imx_mu_xlate()
706 if (chan >= mbox->num_chans) { in imx_mu_xlate()
707 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_xlate()
708 return ERR_PTR(-EINVAL); in imx_mu_xlate()
711 p_chan = &mbox->chans[chan]; in imx_mu_xlate()
714 p_chan->txdone_method = TXDONE_BY_ACK; in imx_mu_xlate()
719 static struct mbox_chan *imx_mu_seco_xlate(struct mbox_controller *mbox, in imx_mu_seco_xlate() argument
724 if (sp->args_count < 1) { in imx_mu_seco_xlate()
725 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_seco_xlate()
726 return ERR_PTR(-EINVAL); in imx_mu_seco_xlate()
729 type = sp->args[0]; /* channel type */ in imx_mu_seco_xlate()
733 dev_err(mbox->dev, "Invalid type: %d\n", type); in imx_mu_seco_xlate()
734 return ERR_PTR(-EINVAL); in imx_mu_seco_xlate()
737 return imx_mu_xlate(mbox, sp); in imx_mu_seco_xlate()
746 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_generic()
748 cp->idx = i % 4; in imx_mu_init_generic()
749 cp->type = i >> 2; in imx_mu_init_generic()
750 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_generic()
751 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_generic()
752 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_generic()
753 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_init_generic()
756 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_init_generic()
757 priv->mbox.of_xlate = imx_mu_xlate; in imx_mu_init_generic()
759 if (priv->side_b) in imx_mu_init_generic()
764 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); in imx_mu_init_generic()
767 val = imx_mu_read(priv, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_init_generic()
768 imx_mu_write(priv, val, priv->dcfg->xSR[IMX_MU_GSR]); in imx_mu_init_generic()
772 imx_mu_read(priv, priv->dcfg->xRR + (i % 4) * 4); in imx_mu_init_generic()
778 int num_chans = priv->dcfg->type & IMX_MU_V2_S4 ? IMX_MU_S4_CHANS : IMX_MU_SCU_CHANS; in imx_mu_init_specific()
781 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_init_specific()
783 cp->idx = i < 2 ? 0 : i - 2; in imx_mu_init_specific()
784 cp->type = i < 2 ? i : IMX_MU_TYPE_RXDB; in imx_mu_init_specific()
785 cp->chan = &priv->mbox_chans[i]; in imx_mu_init_specific()
786 priv->mbox_chans[i].con_priv = cp; in imx_mu_init_specific()
787 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_init_specific()
788 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_init_specific()
791 priv->mbox.num_chans = num_chans; in imx_mu_init_specific()
792 priv->mbox.of_xlate = imx_mu_specific_xlate; in imx_mu_init_specific()
796 imx_mu_write(priv, 0, priv->dcfg->xCR[i]); in imx_mu_init_specific()
802 priv->mbox.of_xlate = imx_mu_seco_xlate; in imx_mu_init_seco()
807 struct device *dev = &pdev->dev; in imx_mu_probe()
808 struct device_node *np = dev->of_node; in imx_mu_probe()
816 return -ENOMEM; in imx_mu_probe()
818 priv->dev = dev; in imx_mu_probe()
820 priv->base = devm_platform_ioremap_resource(pdev, 0); in imx_mu_probe()
821 if (IS_ERR(priv->base)) in imx_mu_probe()
822 return PTR_ERR(priv->base); in imx_mu_probe()
826 return -EINVAL; in imx_mu_probe()
827 priv->dcfg = dcfg; in imx_mu_probe()
828 if (priv->dcfg->type & IMX_MU_V2_IRQ) { in imx_mu_probe()
829 priv->irq[IMX_MU_TYPE_TX] = platform_get_irq_byname(pdev, "tx"); in imx_mu_probe()
830 if (priv->irq[IMX_MU_TYPE_TX] < 0) in imx_mu_probe()
831 return priv->irq[IMX_MU_TYPE_TX]; in imx_mu_probe()
832 priv->irq[IMX_MU_TYPE_RX] = platform_get_irq_byname(pdev, "rx"); in imx_mu_probe()
833 if (priv->irq[IMX_MU_TYPE_RX] < 0) in imx_mu_probe()
834 return priv->irq[IMX_MU_TYPE_RX]; in imx_mu_probe()
841 priv->irq[i] = ret; in imx_mu_probe()
844 if (priv->dcfg->type & IMX_MU_V2_S4) in imx_mu_probe()
849 priv->msg = devm_kzalloc(dev, size, GFP_KERNEL); in imx_mu_probe()
850 if (!priv->msg) in imx_mu_probe()
851 return -ENOMEM; in imx_mu_probe()
853 priv->clk = devm_clk_get(dev, NULL); in imx_mu_probe()
854 if (IS_ERR(priv->clk)) { in imx_mu_probe()
855 if (PTR_ERR(priv->clk) != -ENOENT) in imx_mu_probe()
856 return PTR_ERR(priv->clk); in imx_mu_probe()
858 priv->clk = NULL; in imx_mu_probe()
861 ret = clk_prepare_enable(priv->clk); in imx_mu_probe()
867 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); in imx_mu_probe()
869 priv->dcfg->init(priv); in imx_mu_probe()
871 spin_lock_init(&priv->xcr_lock); in imx_mu_probe()
873 priv->mbox.dev = dev; in imx_mu_probe()
874 priv->mbox.ops = &imx_mu_ops; in imx_mu_probe()
875 priv->mbox.chans = priv->mbox_chans; in imx_mu_probe()
876 priv->mbox.txdone_irq = true; in imx_mu_probe()
880 ret = devm_mbox_controller_register(dev, &priv->mbox); in imx_mu_probe()
882 clk_disable_unprepare(priv->clk); in imx_mu_probe()
896 clk_disable_unprepare(priv->clk); in imx_mu_probe()
902 clk_disable_unprepare(priv->clk); in imx_mu_probe()
910 pm_runtime_disable(priv->dev); in imx_mu_remove()
915 .rx = imx_mu_generic_rx,
926 .rx = imx_mu_generic_rx,
937 .rx = imx_mu_generic_rx,
949 .rx = imx_mu_specific_rx,
960 .rx = imx_mu_specific_rx,
971 .rx = imx_mu_specific_rx,
982 .rx = imx_mu_generic_rx,
992 { .compatible = "fsl,imx7ulp-mu", .data = &imx_mu_cfg_imx7ulp },
993 { .compatible = "fsl,imx6sx-mu", .data = &imx_mu_cfg_imx6sx },
994 { .compatible = "fsl,imx8ulp-mu", .data = &imx_mu_cfg_imx8ulp },
995 { .compatible = "fsl,imx8ulp-mu-s4", .data = &imx_mu_cfg_imx8ulp_s4 },
996 { .compatible = "fsl,imx93-mu-s4", .data = &imx_mu_cfg_imx93_s4 },
997 { .compatible = "fsl,imx8-mu-scu", .data = &imx_mu_cfg_imx8_scu },
998 { .compatible = "fsl,imx8-mu-seco", .data = &imx_mu_cfg_imx8_seco },
1008 if (!priv->clk) { in imx_mu_suspend_noirq()
1010 priv->xcr[i] = imx_mu_read(priv, priv->dcfg->xCR[i]); in imx_mu_suspend_noirq()
1013 priv->suspend = true; in imx_mu_suspend_noirq()
1031 if (!priv->clk && !imx_mu_read(priv, priv->dcfg->xCR[0])) { in imx_mu_resume_noirq()
1033 imx_mu_write(priv, priv->xcr[i], priv->dcfg->xCR[i]); in imx_mu_resume_noirq()
1036 priv->suspend = false; in imx_mu_resume_noirq()
1045 clk_disable_unprepare(priv->clk); in imx_mu_runtime_suspend()
1055 ret = clk_prepare_enable(priv->clk); in imx_mu_runtime_resume()