1 // SPDX-License-Identifier: GPL-2.0-only
7  * Broadcom PDC Mailbox Driver
8  * The PDC provides a ring based programming interface to one or more hardware
9  * offload engines. For example, the PDC driver works with both SPU-M and SPU2
10  * cryptographic offload hardware. In some chips the PDC is referred to as MDE,
11  * and in others the FA2/FA+ hardware is used with this PDC driver.
13  * The PDC driver registers with the Linux mailbox framework as a mailbox
14  * controller, once for each PDC instance. Ring 0 for each PDC is registered as
15  * a mailbox channel. The PDC driver uses interrupts to determine when data
16  * transfers to and from an offload engine are complete. The PDC driver uses
20  * The PDC driver allows multiple messages to be pending in the descriptor
24  * an rx interrupt indicates a response is ready, the PDC driver processes numd
41 #include <linux/mailbox/brcm-message.h>
43 #include <linux/dma-direction.h>
44 #include <linux/dma-mapping.h>
51 /* # entries in PDC dma ring */
72 #define PREVTXD(i, max_mask)          TXD((i) - 1, (max_mask))
74 #define PREVRXD(i, max_mask)          RXD((i) - 1, (max_mask))
75 #define NTXDACTIVE(h, t, max_mask)    TXD((t) - (h), (max_mask))
76 #define NRXDACTIVE(h, t, max_mask)    RXD((t) - (h), (max_mask))
82  * PDC driver reserves ringset 0 on each SPU for its own use. The driver does
83  * not currently support use of multiple ringsets on a single PDC engine.
114  * 11    - PtyChkDisable - parity check is disabled
115  * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
124  * 7:1   - RcvOffset - size in bytes of status region at start of rx frame buf
125  * 9     - SepRxHdrDescEn - place start of new frames only in descriptors
127  * 10    - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all
130  * 11    - PtyChkDisable - parity check is disabled
131  * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
138 #define CRYPTO_D64_RS0_CD_MASK   ((PDC_RING_ENTRIES * RING_ENTRY_SIZE) - 1)
157 	PDC_HW		/* PDC/MDE hardware (i.e. Northstar 2, Pegasus) */
176 	u32  addrlow;   /* descriptor ring base address low 32-bits */
197 /* PDC registers */
209 	u32  intrcvlazy_0;           /* 0x030 (Only in PDC, not FA2) */
210 	u32  intrcvlazy_1;           /* 0x034 (Only in PDC, not FA2) */
211 	u32  intrcvlazy_2;           /* 0x038 (Only in PDC, not FA2) */
212 	u32  intrcvlazy_3;           /* 0x03c (Only in PDC, not FA2) */
215 	u32  fa_intrecvlazy;         /* 0x100 (Only in FA2, not PDC) */
239 	u32  PAD[11];                /* 0x1b4-1dc */
241 	u32  hw_war;                 /* 0x1e4 (Only in PDC, not FA2) */
246 	struct dma64 dmaregs[PDC_NUM_DMA_RINGS];  /* 0x0200 - 0x2fc */
279 /* PDC state structure */
281 	/* Index of the PDC whose state is in this structure instance */
284 	/* Platform device for this PDC instance */
288 	 * Each PDC instance has a mailbox controller. PDC receives request
322 	struct pdc_regs *regs;    /* start of PDC registers */
407 	/* hardware type - FA2 or PDC/MDE */
411 /* Global variables */
420 /* top level debug FS directory for PDC driver */
434 		return -ENOMEM;  in pdc_debugfs_read()
436 	pdcs = filp->private_data;  in pdc_debugfs_read()
438 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
439 			       "SPU %u stats:\n", pdcs->pdc_idx);  in pdc_debugfs_read()
440 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
441 			       "PDC requests....................%u\n",  in pdc_debugfs_read()
442 			       pdcs->pdc_requests);  in pdc_debugfs_read()
443 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
444 			       "PDC responses...................%u\n",  in pdc_debugfs_read()
445 			       pdcs->pdc_replies);  in pdc_debugfs_read()
446 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
448 			       pdcs->last_tx_not_done);  in pdc_debugfs_read()
449 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
451 			       pdcs->tx_ring_full);  in pdc_debugfs_read()
452 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
454 			       pdcs->rx_ring_full);  in pdc_debugfs_read()
455 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
457 			       pdcs->txnobuf);  in pdc_debugfs_read()
458 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
460 			       pdcs->rxnobuf);  in pdc_debugfs_read()
461 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
463 			       pdcs->rx_oflow);  in pdc_debugfs_read()
464 	out_offset += scnprintf(buf + out_offset, out_count - out_offset,  in pdc_debugfs_read()
466 			       NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr,  in pdc_debugfs_read()
467 					  pdcs->nrxpost));  in pdc_debugfs_read()
484  * pdc_setup_debugfs() - Create the debug FS directories. If the top-level
487  * @pdcs: PDC state structure
496 	snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx);  in pdc_setup_debugfs()
512  * pdc_build_rxd() - Build DMA descriptor to receive SPU result.
513  * @pdcs:      PDC state for SPU that will generate result
522 	struct device *dev = &pdcs->pdev->dev;  in pdc_build_rxd()
523 	struct dma64dd *rxd = &pdcs->rxd_64[pdcs->rxout];  in pdc_build_rxd()
526 		"Writing rx descriptor for PDC %u at index %u with length %u. flags %#x\n",  in pdc_build_rxd()
527 		pdcs->pdc_idx, pdcs->rxout, buf_len, flags);  in pdc_build_rxd()
529 	rxd->addrlow = cpu_to_le32(lower_32_bits(dma_addr));  in pdc_build_rxd()
530 	rxd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr));  in pdc_build_rxd()
531 	rxd->ctrl1 = cpu_to_le32(flags);  in pdc_build_rxd()
532 	rxd->ctrl2 = cpu_to_le32(buf_len);  in pdc_build_rxd()
535 	pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost);  in pdc_build_rxd()
539  * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to
541  * @pdcs:        PDC state for the SPU that will process this request
550 	struct device *dev = &pdcs->pdev->dev;  in pdc_build_txd()
551 	struct dma64dd *txd = &pdcs->txd_64[pdcs->txout];  in pdc_build_txd()
554 		"Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n",  in pdc_build_txd()
555 		pdcs->pdc_idx, pdcs->txout, buf_len, flags);  in pdc_build_txd()
557 	txd->addrlow = cpu_to_le32(lower_32_bits(dma_addr));  in pdc_build_txd()
558 	txd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr));  in pdc_build_txd()
559 	txd->ctrl1 = cpu_to_le32(flags);  in pdc_build_txd()
560 	txd->ctrl2 = cpu_to_le32(buf_len);  in pdc_build_txd()
563 	pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost);  in pdc_build_txd()
567  * pdc_receive_one() - Receive a response message from a given SPU.
568  * @pdcs:    PDC state for the SPU to receive from
574  *          -EAGAIN indicates that no response message is available
575  *          -EIO an error occurred
580 	struct device *dev = &pdcs->pdev->dev;  in pdc_receive_one()
592 	mbc = &pdcs->mbc;  in pdc_receive_one()
593 	chan = &mbc->chans[0];  in pdc_receive_one()
601 	frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost);  in pdc_receive_one()
603 	    (frags_rdy < pdcs->rx_ctx[pdcs->rxin].rxin_numd))  in pdc_receive_one()
605 		return -EAGAIN;  in pdc_receive_one()
607 	num_frags = pdcs->txin_numd[pdcs->txin];  in pdc_receive_one()
610 	dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin],  in pdc_receive_one()
611 		     sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE);  in pdc_receive_one()
613 	pdcs->txin = (pdcs->txin + num_frags) & pdcs->ntxpost;  in pdc_receive_one()
615 	dev_dbg(dev, "PDC %u reclaimed %d tx descriptors",  in pdc_receive_one()
616 		pdcs->pdc_idx, num_frags);  in pdc_receive_one()
618 	rx_idx = pdcs->rxin;  in pdc_receive_one()
619 	rx_ctx = &pdcs->rx_ctx[rx_idx];  in pdc_receive_one()
620 	num_frags = rx_ctx->rxin_numd;  in pdc_receive_one()
622 	mssg.ctx = rx_ctx->rxp_ctx;  in pdc_receive_one()
623 	rx_ctx->rxp_ctx = NULL;  in pdc_receive_one()
624 	resp_hdr = rx_ctx->resp_hdr;  in pdc_receive_one()
625 	resp_hdr_daddr = rx_ctx->resp_hdr_daddr;  in pdc_receive_one()
626 	dma_unmap_sg(dev, rx_ctx->dst_sg, sg_nents(rx_ctx->dst_sg),  in pdc_receive_one()
629 	pdcs->rxin = (pdcs->rxin + num_frags) & pdcs->nrxpost;  in pdc_receive_one()
631 	dev_dbg(dev, "PDC %u reclaimed %d rx descriptors",  in pdc_receive_one()
632 		pdcs->pdc_idx, num_frags);  in pdc_receive_one()
635 		"PDC %u txin %u, txout %u, rxin %u, rxout %u, last_rx_curr %u\n",  in pdc_receive_one()
636 		pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin,  in pdc_receive_one()
637 		pdcs->rxout, pdcs->last_rx_curr);  in pdc_receive_one()
639 	if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) {  in pdc_receive_one()
641 		 * For SPU-M, get length of response msg and rx overflow status.  in pdc_receive_one()
651 				pdcs->rx_oflow++;  in pdc_receive_one()
655 			return -EIO;  in pdc_receive_one()
659 	dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr);  in pdc_receive_one()
663 	pdcs->pdc_replies++;  in pdc_receive_one()
668  * pdc_receive() - Process as many responses as are available in the rx ring.
669  * @pdcs:  PDC state
680 	pdcs->last_rx_curr =  in pdc_receive()
681 	    (ioread32((const void __iomem *)&pdcs->rxregs_64->status0) &  in pdc_receive()
693  * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit
696  * @pdcs:      PDC state for the SPU that will process this request
723 	tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout,  in pdc_tx_list_sg_add()
724 					      pdcs->ntxpost);  in pdc_tx_list_sg_add()
726 		pdcs->txnobuf++;  in pdc_tx_list_sg_add()
727 		return -ENOSPC;  in pdc_tx_list_sg_add()
731 	if (pdcs->tx_msg_start == pdcs->txout) {  in pdc_tx_list_sg_add()
733 		pdcs->txin_numd[pdcs->tx_msg_start] = 0;  in pdc_tx_list_sg_add()
734 		pdcs->src_sg[pdcs->txout] = sg;  in pdc_tx_list_sg_add()
739 		if (unlikely(pdcs->txout == (pdcs->ntxd - 1)))  in pdc_tx_list_sg_add()
745 		 * If sg buffer larger than PDC limit, split across  in pdc_tx_list_sg_add()
754 			bufcnt -= PDC_DMA_BUF_MAX;  in pdc_tx_list_sg_add()
756 			if (unlikely(pdcs->txout == (pdcs->ntxd - 1)))  in pdc_tx_list_sg_add()
770 	pdcs->txin_numd[pdcs->tx_msg_start] += desc_w;  in pdc_tx_list_sg_add()
776  * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx
778  * @pdcs:  PDC state for SPU to process the request
791 	iowrite32(pdcs->rxout << 4, &pdcs->rxregs_64->ptr);  in pdc_tx_list_final()
792 	iowrite32(pdcs->txout << 4, &pdcs->txregs_64->ptr);  in pdc_tx_list_final()
793 	pdcs->pdc_requests++;  in pdc_tx_list_final()
799  * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC.
800  * @pdcs:   PDC state for SPU handling request
806  * response. For example, with SPU-M, the metadata is a 32-byte DMA header and
807  * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and
823 	rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,  in pdc_rx_list_init()
824 					      pdcs->nrxpost);  in pdc_rx_list_init()
826 		pdcs->rxnobuf++;  in pdc_rx_list_init()
827 		return -ENOSPC;  in pdc_rx_list_init()
831 	vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr);  in pdc_rx_list_init()
833 		return -ENOMEM;  in pdc_rx_list_init()
840 	pdcs->rx_msg_start = pdcs->rxout;  in pdc_rx_list_init()
841 	pdcs->tx_msg_start = pdcs->txout;  in pdc_rx_list_init()
845 	pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd = 1;  in pdc_rx_list_init()
847 	if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))  in pdc_rx_list_init()
850 	rx_ctx = &pdcs->rx_ctx[pdcs->rxout];  in pdc_rx_list_init()
851 	rx_ctx->rxp_ctx = ctx;  in pdc_rx_list_init()
852 	rx_ctx->dst_sg = dst_sg;  in pdc_rx_list_init()
853 	rx_ctx->resp_hdr = vaddr;  in pdc_rx_list_init()
854 	rx_ctx->resp_hdr_daddr = daddr;  in pdc_rx_list_init()
855 	pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags);  in pdc_rx_list_init()
860  * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive
863  * @pdcs:       PDC state for the SPU that will process this request
889 	rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,  in pdc_rx_list_sg_add()
890 					      pdcs->nrxpost);  in pdc_rx_list_sg_add()
892 		pdcs->rxnobuf++;  in pdc_rx_list_sg_add()
893 		return -ENOSPC;  in pdc_rx_list_sg_add()
897 		if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))  in pdc_rx_list_sg_add()
903 		 * If sg buffer larger than PDC limit, split across  in pdc_rx_list_sg_add()
911 			bufcnt -= PDC_DMA_BUF_MAX;  in pdc_rx_list_sg_add()
913 			if (unlikely(pdcs->rxout == (pdcs->nrxd - 1)))  in pdc_rx_list_sg_add()
922 	pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd += desc_w;  in pdc_rx_list_sg_add()
928  * pdc_irq_handler() - Interrupt handler called in interrupt context.
943 	u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);  in pdc_irq_handler()
949 	iowrite32(0, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);  in pdc_irq_handler()
952 	iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET);  in pdc_irq_handler()
955 	tasklet_schedule(&pdcs->rx_tasklet);  in pdc_irq_handler()
960  * pdc_tasklet_cb() - Tasklet callback that runs the deferred processing after
971 	iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);  in pdc_tasklet_cb()
975  * pdc_ring_init() - Allocate DMA rings and initialize constant fields of
977  * @pdcs:    PDC instance state
988 	struct device *dev = &pdcs->pdev->dev;  in pdc_ring_init()
993 	tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase);  in pdc_ring_init()
995 		err = -ENOMEM;  in pdc_ring_init()
1000 	rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase);  in pdc_ring_init()
1002 		err = -ENOMEM;  in pdc_ring_init()
1006 	dev_dbg(dev, " - base DMA addr of tx ring      %pad", &tx.dmabase);  in pdc_ring_init()
1007 	dev_dbg(dev, " - base virtual addr of tx ring  %p", tx.vbase);  in pdc_ring_init()
1008 	dev_dbg(dev, " - base DMA addr of rx ring      %pad", &rx.dmabase);  in pdc_ring_init()
1009 	dev_dbg(dev, " - base virtual addr of rx ring  %p", rx.vbase);  in pdc_ring_init()
1011 	memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx));  in pdc_ring_init()
1012 	memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx));  in pdc_ring_init()
1014 	pdcs->rxin = 0;  in pdc_ring_init()
1015 	pdcs->rx_msg_start = 0;  in pdc_ring_init()
1016 	pdcs->last_rx_curr = 0;  in pdc_ring_init()
1017 	pdcs->rxout = 0;  in pdc_ring_init()
1018 	pdcs->txin = 0;  in pdc_ring_init()
1019 	pdcs->tx_msg_start = 0;  in pdc_ring_init()
1020 	pdcs->txout = 0;  in pdc_ring_init()
1023 	pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase;  in pdc_ring_init()
1024 	pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase;  in pdc_ring_init()
1027 	dma_reg = &pdcs->regs->dmaregs[ringset];  in pdc_ring_init()
1030 	iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);  in pdc_ring_init()
1031 	iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)),  in pdc_ring_init()
1032 		  &dma_reg->dmarcv.control);  in pdc_ring_init()
1033 	iowrite32(0, &dma_reg->dmaxmt.ptr);  in pdc_ring_init()
1034 	iowrite32(0, &dma_reg->dmarcv.ptr);  in pdc_ring_init()
1037 	iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase),  in pdc_ring_init()
1038 		  &dma_reg->dmaxmt.addrlow);  in pdc_ring_init()
1039 	iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase),  in pdc_ring_init()
1040 		  &dma_reg->dmaxmt.addrhigh);  in pdc_ring_init()
1042 	iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase),  in pdc_ring_init()
1043 		  &dma_reg->dmarcv.addrlow);  in pdc_ring_init()
1044 	iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase),  in pdc_ring_init()
1045 		  &dma_reg->dmarcv.addrhigh);  in pdc_ring_init()
1047 	/* Re-enable DMA */  in pdc_ring_init()
1048 	iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control);  in pdc_ring_init()
1049 	iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)),  in pdc_ring_init()
1050 		  &dma_reg->dmarcv.control);  in pdc_ring_init()
1055 		if (i != pdcs->ntxpost) {  in pdc_ring_init()
1057 				  &pdcs->txd_64[i].ctrl1);  in pdc_ring_init()
1061 				  D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1);  in pdc_ring_init()
1065 		if (i != pdcs->nrxpost) {  in pdc_ring_init()
1067 				  &pdcs->rxd_64[i].ctrl1);  in pdc_ring_init()
1071 				  &pdcs->rxd_64[i].ctrl1);  in pdc_ring_init()
1077 	dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase);  in pdc_ring_init()
1084 	if (pdcs->tx_ring_alloc.vbase) {  in pdc_ring_free()
1085 		dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase,  in pdc_ring_free()
1086 			      pdcs->tx_ring_alloc.dmabase);  in pdc_ring_free()
1087 		pdcs->tx_ring_alloc.vbase = NULL;  in pdc_ring_free()
1090 	if (pdcs->rx_ring_alloc.vbase) {  in pdc_ring_free()
1091 		dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase,  in pdc_ring_free()
1092 			      pdcs->rx_ring_alloc.dmabase);  in pdc_ring_free()
1093 		pdcs->rx_ring_alloc.vbase = NULL;  in pdc_ring_free()
1098  * pdc_desc_count() - Count the number of DMA descriptors that will be required
1108 		cnt += ((sg->length / PDC_DMA_BUF_MAX) + 1);  in pdc_desc_count()
1115  * pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors
1117  * @pdcs:  PDC state
1131 	rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout,  in pdc_rings_full()
1132 					      pdcs->nrxpost);  in pdc_rings_full()
1134 		pdcs->rx_ring_full++;  in pdc_rings_full()
1139 		tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout,  in pdc_rings_full()
1140 						      pdcs->ntxpost);  in pdc_rings_full()
1142 			pdcs->tx_ring_full++;  in pdc_rings_full()
1150  * pdc_last_tx_done() - If both the tx and rx rings have at least
1154  * Return: true if PDC can accept another message on this channel
1158 	struct pdc_state *pdcs = chan->con_priv;  in pdc_last_tx_done()
1163 		pdcs->last_tx_not_done++;  in pdc_last_tx_done()
1172  * pdc_send_data() - mailbox send_data function
1189  *	   -ENOTSUPP if the mailbox message is a type this driver does not
1195 	struct pdc_state *pdcs = chan->con_priv;  in pdc_send_data()
1196 	struct device *dev = &pdcs->pdev->dev;  in pdc_send_data()
1205 	if (unlikely(mssg->type != BRCM_MESSAGE_SPU))  in pdc_send_data()
1206 		return -ENOTSUPP;  in pdc_send_data()
1208 	src_nent = sg_nents(mssg->spu.src);  in pdc_send_data()
1210 		nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE);  in pdc_send_data()
1212 			return -EIO;  in pdc_send_data()
1215 	dst_nent = sg_nents(mssg->spu.dst);  in pdc_send_data()
1217 		nent = dma_map_sg(dev, mssg->spu.dst, dst_nent,  in pdc_send_data()
1220 			dma_unmap_sg(dev, mssg->spu.src, src_nent,  in pdc_send_data()
1222 			return -EIO;  in pdc_send_data()
1235 	tx_desc_req = pdc_desc_count(mssg->spu.src);  in pdc_send_data()
1236 	rx_desc_req = pdc_desc_count(mssg->spu.dst);  in pdc_send_data()
1238 		return -ENOSPC;  in pdc_send_data()
1241 	err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx);  in pdc_send_data()
1242 	err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst);  in pdc_send_data()
1245 	err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src);  in pdc_send_data()
1249 		dev_err(&pdcs->pdev->dev,  in pdc_send_data()
1257 	return pdc_ring_init(chan->con_priv, PDC_RINGSET);  in pdc_startup()
1262 	struct pdc_state *pdcs = chan->con_priv;  in pdc_shutdown()
1267 	dev_dbg(&pdcs->pdev->dev,  in pdc_shutdown()
1268 		"Shutdown mailbox channel for PDC %u", pdcs->pdc_idx);  in pdc_shutdown()
1273  * pdc_hw_init() - Use the given initialization parameters to initialize the
1275  * @pdcs:  state of the PDC
1285 	pdev = pdcs->pdev;  in pdc_hw_init()
1286 	dev = &pdev->dev;  in pdc_hw_init()
1288 	dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx);  in pdc_hw_init()
1291 	dev_dbg(dev, " - base virtual addr of hw regs    %p",  in pdc_hw_init()
1292 		pdcs->pdc_reg_vbase);  in pdc_hw_init()
1295 	pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase;  in pdc_hw_init()
1296 	pdcs->txregs_64 = (struct dma64_regs *)  in pdc_hw_init()
1297 	    (((u8 *)pdcs->pdc_reg_vbase) +  in pdc_hw_init()
1299 	pdcs->rxregs_64 = (struct dma64_regs *)  in pdc_hw_init()
1300 	    (((u8 *)pdcs->pdc_reg_vbase) +  in pdc_hw_init()
1303 	pdcs->ntxd = PDC_RING_ENTRIES;  in pdc_hw_init()
1304 	pdcs->nrxd = PDC_RING_ENTRIES;  in pdc_hw_init()
1305 	pdcs->ntxpost = PDC_RING_ENTRIES - 1;  in pdc_hw_init()
1306 	pdcs->nrxpost = PDC_RING_ENTRIES - 1;  in pdc_hw_init()
1307 	iowrite32(0, &pdcs->regs->intmask);  in pdc_hw_init()
1309 	dma_reg = &pdcs->regs->dmaregs[ringset];  in pdc_hw_init()
1312 	iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);  in pdc_hw_init()
1314 	iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),  in pdc_hw_init()
1315 		  &dma_reg->dmarcv.control);  in pdc_hw_init()
1318 	iowrite32(0, &dma_reg->dmaxmt.ptr);  in pdc_hw_init()
1319 	iowrite32(0, &dma_reg->dmarcv.ptr);  in pdc_hw_init()
1321 	if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN)  in pdc_hw_init()
1323 			  pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET);  in pdc_hw_init()
1327  * pdc_hw_disable() - Disable the tx and rx control in the hw.
1328  * @pdcs: PDC state structure
1335 	dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET];  in pdc_hw_disable()
1336 	iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control);  in pdc_hw_disable()
1337 	iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1),  in pdc_hw_disable()
1338 		  &dma_reg->dmarcv.control);  in pdc_hw_disable()
1342  * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata
1344  * @pdcs: PDC state structure
1346  * The metadata is not returned to the mailbox client. So the PDC driver
1350  *         -ENOMEM if pool creation fails
1357 	pdev = pdcs->pdev;  in pdc_rx_buf_pool_create()
1358 	dev = &pdev->dev;  in pdc_rx_buf_pool_create()
1360 	pdcs->pdc_resp_hdr_len = pdcs->rx_status_len;  in pdc_rx_buf_pool_create()
1361 	if (pdcs->use_bcm_hdr)  in pdc_rx_buf_pool_create()
1362 		pdcs->pdc_resp_hdr_len += BCM_HDR_LEN;  in pdc_rx_buf_pool_create()
1364 	pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev,  in pdc_rx_buf_pool_create()
1365 					    pdcs->pdc_resp_hdr_len,  in pdc_rx_buf_pool_create()
1367 	if (!pdcs->rx_buf_pool)  in pdc_rx_buf_pool_create()
1368 		return -ENOMEM;  in pdc_rx_buf_pool_create()
1374  * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and
1377  * @pdcs:   PDC state
1387 	struct platform_device *pdev = pdcs->pdev;  in pdc_interrupts_init()
1388 	struct device *dev = &pdev->dev;  in pdc_interrupts_init()
1389 	struct device_node *dn = pdev->dev.of_node;  in pdc_interrupts_init()
1393 	iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET);  in pdc_interrupts_init()
1395 	if (pdcs->hw_type == FA_HW)  in pdc_interrupts_init()
1396 		iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +  in pdc_interrupts_init()
1399 		iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase +  in pdc_interrupts_init()
1403 	pdcs->pdc_irq = irq_of_parse_and_map(dn, 0);  in pdc_interrupts_init()
1404 	dev_dbg(dev, "pdc device %s irq %u for pdcs %p",  in pdc_interrupts_init()
1405 		dev_name(dev), pdcs->pdc_irq, pdcs);  in pdc_interrupts_init()
1407 	err = devm_request_irq(dev, pdcs->pdc_irq, pdc_irq_handler, 0,  in pdc_interrupts_init()
1411 			pdcs->pdc_irq, err);  in pdc_interrupts_init()
1425  * pdc_mb_init() - Initialize the mailbox controller.
1426  * @pdcs:  PDC state
1428  * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel
1429  * driver only uses one ringset and thus one mb channel. PDC uses the transmit
1438 	struct device *dev = &pdcs->pdev->dev;  in pdc_mb_init()
1443 	mbc = &pdcs->mbc;  in pdc_mb_init()
1444 	mbc->dev = dev;  in pdc_mb_init()
1445 	mbc->ops = &pdc_mbox_chan_ops;  in pdc_mb_init()
1446 	mbc->num_chans = 1;  in pdc_mb_init()
1447 	mbc->chans = devm_kcalloc(dev, mbc->num_chans, sizeof(*mbc->chans),  in pdc_mb_init()
1449 	if (!mbc->chans)  in pdc_mb_init()
1450 		return -ENOMEM;  in pdc_mb_init()
1452 	mbc->txdone_irq = false;  in pdc_mb_init()
1453 	mbc->txdone_poll = true;  in pdc_mb_init()
1454 	mbc->txpoll_period = 1;  in pdc_mb_init()
1455 	for (chan_index = 0; chan_index < mbc->num_chans; chan_index++)  in pdc_mb_init()
1456 		mbc->chans[chan_index].con_priv = pdcs;  in pdc_mb_init()
1462 			 "Failed to register PDC mailbox controller. Error %d.",  in pdc_mb_init()
1474 	{.compatible = "brcm,iproc-pdc-mbox", .data = &pdc_hw},
1475 	{.compatible = "brcm,iproc-fa2-mbox", .data = &fa_hw},
1481  * pdc_dt_read() - Read application-specific data from device tree.
1483  * @pdcs:  PDC state
1486  * Reads whether transmit and received frames should be preceded by an 8-byte
1490  *         -ENODEV if device not available
1494 	struct device *dev = &pdev->dev;  in pdc_dt_read()
1495 	struct device_node *dn = pdev->dev.of_node;  in pdc_dt_read()
1499 	err = of_property_read_u32(dn, "brcm,rx-status-len",  in pdc_dt_read()
1500 				   &pdcs->rx_status_len);  in pdc_dt_read()
1506 	pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr");  in pdc_dt_read()
1508 	pdcs->hw_type = PDC_HW;  in pdc_dt_read()
1512 		pdcs->hw_type = *hw_type;  in pdc_dt_read()
1518  * pdc_probe() - Probe function for PDC driver.
1519  * @pdev:   PDC platform device
1523  * Initialize a mailbox controller for each PDC.
1531 	struct device *dev = &pdev->dev;  in pdc_probe()
1535 	/* PDC state for one SPU */  in pdc_probe()
1538 		err = -ENOMEM;  in pdc_probe()
1542 	pdcs->pdev = pdev;  in pdc_probe()
1544 	pdcs->pdc_idx = pdcg.num_spu;  in pdc_probe()
1549 		dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err);  in pdc_probe()
1554 	pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE,  in pdc_probe()
1556 	if (!pdcs->ring_pool) {  in pdc_probe()
1557 		err = -ENOMEM;  in pdc_probe()
1565 	pdcs->pdc_reg_vbase = devm_platform_get_and_ioremap_resource(pdev, 0, &pdc_regs);  in pdc_probe()
1566 	if (IS_ERR(pdcs->pdc_reg_vbase)) {  in pdc_probe()
1567 		err = PTR_ERR(pdcs->pdc_reg_vbase);  in pdc_probe()
1570 	dev_dbg(dev, "PDC register region res.start = %pa, res.end = %pa",  in pdc_probe()
1571 		&pdc_regs->start, &pdc_regs->end);  in pdc_probe()
1581 	tasklet_setup(&pdcs->rx_tasklet, pdc_tasklet_cb);  in pdc_probe()
1598 	tasklet_kill(&pdcs->rx_tasklet);  in pdc_probe()
1599 	dma_pool_destroy(pdcs->rx_buf_pool);  in pdc_probe()
1602 	dma_pool_destroy(pdcs->ring_pool);  in pdc_probe()
1614 	tasklet_kill(&pdcs->rx_tasklet);  in pdc_remove()
1618 	dma_pool_destroy(pdcs->rx_buf_pool);  in pdc_remove()
1619 	dma_pool_destroy(pdcs->ring_pool);  in pdc_remove()
1626 		   .name = "brcm-iproc-pdc-mbox",
1633 MODULE_DESCRIPTION("Broadcom PDC mailbox driver");