Lines Matching +full:msi +full:- +full:base +full:- +full:spi
1 // SPDX-License-Identifier: GPL-2.0
3 #define pr_fmt(fmt) "mvebu-sei: " fmt
11 #include <linux/msi.h>
41 void __iomem *base; member
48 /* Lock on MSI allocations/releases */
59 u32 reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_ack_irq()
61 writel_relaxed(BIT(SEI_IRQ_REG_BIT(d->hwirq)), in mvebu_sei_ack_irq()
62 sei->base + GICP_SECR(reg_idx)); in mvebu_sei_ack_irq()
68 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_mask_irq()
72 raw_spin_lock_irqsave(&sei->mask_lock, flags); in mvebu_sei_mask_irq()
73 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
74 reg |= BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_mask_irq()
75 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_mask_irq()
76 raw_spin_unlock_irqrestore(&sei->mask_lock, flags); in mvebu_sei_mask_irq()
82 u32 reg, reg_idx = SEI_IRQ_REG_IDX(d->hwirq); in mvebu_sei_unmask_irq()
86 raw_spin_lock_irqsave(&sei->mask_lock, flags); in mvebu_sei_unmask_irq()
87 reg = readl_relaxed(sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
88 reg &= ~BIT(SEI_IRQ_REG_BIT(d->hwirq)); in mvebu_sei_unmask_irq()
89 writel_relaxed(reg, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_unmask_irq()
90 raw_spin_unlock_irqrestore(&sei->mask_lock, flags); in mvebu_sei_unmask_irq()
97 return -EINVAL; in mvebu_sei_set_affinity()
106 return -EINVAL; in mvebu_sei_set_irqchip_state()
124 return -EINVAL; in mvebu_sei_ap_set_type()
141 struct mvebu_sei *sei = data->chip_data; in mvebu_sei_cp_compose_msi_msg()
142 phys_addr_t set = sei->res->start + GICP_SET_SEI_OFFSET; in mvebu_sei_cp_compose_msi_msg()
144 msg->data = data->hwirq + sei->caps->cp_range.first; in mvebu_sei_cp_compose_msi_msg()
145 msg->address_lo = lower_32_bits(set); in mvebu_sei_cp_compose_msi_msg()
146 msg->address_hi = upper_32_bits(set); in mvebu_sei_cp_compose_msi_msg()
152 return -EINVAL; in mvebu_sei_cp_set_type()
170 struct mvebu_sei *sei = domain->host_data; in mvebu_sei_domain_alloc()
174 irq_domain_set_hwirq_and_chip(domain, virq, fwspec->param[0], in mvebu_sei_domain_alloc()
202 *hwirq = fwspec->param[0]; in mvebu_sei_ap_translate()
211 struct mvebu_sei *sei = domain->host_data; in mvebu_sei_ap_alloc()
219 fwspec.fwnode = domain->parent->fwnode; in mvebu_sei_ap_alloc()
221 fwspec.param[0] = hwirq + sei->caps->ap_range.first; in mvebu_sei_ap_alloc()
243 mutex_lock(&sei->cp_msi_lock); in mvebu_sei_cp_release_irq()
244 clear_bit(hwirq, sei->cp_msi_bitmap); in mvebu_sei_cp_release_irq()
245 mutex_unlock(&sei->cp_msi_lock); in mvebu_sei_cp_release_irq()
252 struct mvebu_sei *sei = domain->host_data; in mvebu_sei_cp_domain_alloc()
259 return -ENOTSUPP; in mvebu_sei_cp_domain_alloc()
261 mutex_lock(&sei->cp_msi_lock); in mvebu_sei_cp_domain_alloc()
262 hwirq = find_first_zero_bit(sei->cp_msi_bitmap, in mvebu_sei_cp_domain_alloc()
263 sei->caps->cp_range.size); in mvebu_sei_cp_domain_alloc()
264 if (hwirq < sei->caps->cp_range.size) in mvebu_sei_cp_domain_alloc()
265 set_bit(hwirq, sei->cp_msi_bitmap); in mvebu_sei_cp_domain_alloc()
266 mutex_unlock(&sei->cp_msi_lock); in mvebu_sei_cp_domain_alloc()
268 if (hwirq == sei->caps->cp_range.size) in mvebu_sei_cp_domain_alloc()
269 return -ENOSPC; in mvebu_sei_cp_domain_alloc()
271 fwspec.fwnode = domain->parent->fwnode; in mvebu_sei_cp_domain_alloc()
273 fwspec.param[0] = hwirq + sei->caps->cp_range.first; in mvebu_sei_cp_domain_alloc()
293 struct mvebu_sei *sei = domain->host_data; in mvebu_sei_cp_domain_free()
296 if (nr_irqs != 1 || d->hwirq >= sei->caps->cp_range.size) { in mvebu_sei_cp_domain_free()
297 dev_err(sei->dev, "Invalid hwirq %lu\n", d->hwirq); in mvebu_sei_cp_domain_free()
301 mvebu_sei_cp_release_irq(sei, d->hwirq); in mvebu_sei_cp_domain_free()
337 irqmap = readl_relaxed(sei->base + GICP_SECR(idx)); in mvebu_sei_handle_cascade_irq()
343 err = generic_handle_domain_irq(sei->sei_domain, hwirq); in mvebu_sei_handle_cascade_irq()
345 dev_warn(sei->dev, "Spurious IRQ detected (hwirq %lu)\n", hwirq); in mvebu_sei_handle_cascade_irq()
358 writel_relaxed(0xFFFFFFFF, sei->base + GICP_SECR(reg_idx)); in mvebu_sei_reset()
359 writel_relaxed(0xFFFFFFFF, sei->base + GICP_SEMR(reg_idx)); in mvebu_sei_reset()
365 struct device_node *node = pdev->dev.of_node; in mvebu_sei_probe()
371 sei = devm_kzalloc(&pdev->dev, sizeof(*sei), GFP_KERNEL); in mvebu_sei_probe()
373 return -ENOMEM; in mvebu_sei_probe()
375 sei->dev = &pdev->dev; in mvebu_sei_probe()
377 mutex_init(&sei->cp_msi_lock); in mvebu_sei_probe()
378 raw_spin_lock_init(&sei->mask_lock); in mvebu_sei_probe()
380 sei->base = devm_platform_get_and_ioremap_resource(pdev, 0, &sei->res); in mvebu_sei_probe()
381 if (IS_ERR(sei->base)) in mvebu_sei_probe()
382 return PTR_ERR(sei->base); in mvebu_sei_probe()
385 sei->caps = of_device_get_match_data(&pdev->dev); in mvebu_sei_probe()
386 if (!sei->caps) { in mvebu_sei_probe()
387 dev_err(sei->dev, in mvebu_sei_probe()
389 return -EINVAL; in mvebu_sei_probe()
393 * Reserve the single (top-level) parent SPI IRQ from which all the in mvebu_sei_probe()
398 dev_err(sei->dev, "Failed to retrieve top-level SPI IRQ\n"); in mvebu_sei_probe()
399 return -ENODEV; in mvebu_sei_probe()
403 sei->sei_domain = irq_domain_create_linear(of_node_to_fwnode(node), in mvebu_sei_probe()
404 (sei->caps->ap_range.size + in mvebu_sei_probe()
405 sei->caps->cp_range.size), in mvebu_sei_probe()
408 if (!sei->sei_domain) { in mvebu_sei_probe()
409 dev_err(sei->dev, "Failed to create SEI IRQ domain\n"); in mvebu_sei_probe()
410 ret = -ENOMEM; in mvebu_sei_probe()
414 irq_domain_update_bus_token(sei->sei_domain, DOMAIN_BUS_NEXUS); in mvebu_sei_probe()
417 sei->ap_domain = irq_domain_create_hierarchy(sei->sei_domain, 0, in mvebu_sei_probe()
418 sei->caps->ap_range.size, in mvebu_sei_probe()
422 if (!sei->ap_domain) { in mvebu_sei_probe()
423 dev_err(sei->dev, "Failed to create AP IRQ domain\n"); in mvebu_sei_probe()
424 ret = -ENOMEM; in mvebu_sei_probe()
428 irq_domain_update_bus_token(sei->ap_domain, DOMAIN_BUS_WIRED); in mvebu_sei_probe()
430 /* Create the 'MSI' domain */ in mvebu_sei_probe()
431 sei->cp_domain = irq_domain_create_hierarchy(sei->sei_domain, 0, in mvebu_sei_probe()
432 sei->caps->cp_range.size, in mvebu_sei_probe()
436 if (!sei->cp_domain) { in mvebu_sei_probe()
438 ret = -ENOMEM; in mvebu_sei_probe()
442 irq_domain_update_bus_token(sei->cp_domain, DOMAIN_BUS_GENERIC_MSI); in mvebu_sei_probe()
446 sei->cp_domain); in mvebu_sei_probe()
448 pr_err("Failed to create CPs MSI domain\n"); in mvebu_sei_probe()
449 ret = -ENOMEM; in mvebu_sei_probe()
462 irq_domain_remove(sei->cp_domain); in mvebu_sei_probe()
464 irq_domain_remove(sei->ap_domain); in mvebu_sei_probe()
466 irq_domain_remove(sei->sei_domain); in mvebu_sei_probe()
486 .compatible = "marvell,ap806-sei",
495 .name = "mvebu-sei",