Lines Matching +full:non +full:- +full:secure +full:- +full:domain
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
24 #include <linux/irqchip/arm-gic-common.h>
25 #include <linux/irqchip/arm-gic-v3.h>
26 #include <linux/irqchip/irq-partition-percpu.h>
29 #include <linux/arm-smccc.h>
36 #include "irq-gic-common.h"
58 struct irq_domain *domain; member
82 * are potentially stolen by the secure side. Some code, especially code dealing
89 * SCR_EL3.FIQ, and the behaviour of non-secure priority registers of the
93 * When security is enabled, non-secure priority values from the (re)distributor
97 * If SCR_EL3.FIQ == 1, the values written to/read from PMR and RPR at non-secure
103 * - section 4.8.1 Non-secure accesses to register fields for Secure interrupt
105 * - Figure 4-7 Secure read of the priority field for a Non-secure Group 1
114 * When the Non-secure world has access to group 0 interrupts (as a
119 * written by software is moved to the Non-secure range by the Distributor.
142 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
180 return __get_intid_range(d->hwirq); in get_intid_range()
185 return d->hwirq; in gic_irq()
207 * For the erratum T241-FABRIC-4, read accesses to GICD_In{E} in gic_dist_base_alias()
212 * Chip0 = 32-351 in gic_dist_base_alias()
213 * Chip1 = 352-671 in gic_dist_base_alias()
214 * Chip2 = 672-991 in gic_dist_base_alias()
215 * Chip3 = 4096-4415 in gic_dist_base_alias()
219 chip = (hwirq - 32) / 320; in gic_dist_base_alias()
239 /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
244 /* SPI -> dist_base */ in gic_dist_base()
257 count--; in gic_do_wait_for_rwp()
304 while (--count) { in gic_enable_redist()
325 *index = d->hwirq; in convert_offset_index()
333 *index = d->hwirq - EPPI_BASE_INTID + 32; in convert_offset_index()
336 *index = d->hwirq - ESPI_BASE_INTID; in convert_offset_index()
365 *index = d->hwirq; in convert_offset_index()
441 if (d->hwirq >= 8192) /* SGI/PPI/SPI only */ in gic_irq_set_irqchip_state()
442 return -EINVAL; in gic_irq_set_irqchip_state()
462 return -EINVAL; in gic_irq_set_irqchip_state()
472 if (d->hwirq >= 8192) /* PPI/SPI only */ in gic_irq_get_irqchip_state()
473 return -EINVAL; in gic_irq_get_irqchip_state()
489 return -EINVAL; in gic_irq_get_irqchip_state()
509 return hwirq - 16; in __gic_get_ppi_index()
511 return hwirq - EPPI_BASE_INTID + 16; in __gic_get_ppi_index()
524 return hwirq - EPPI_BASE_INTID + 32; in __gic_get_rdist_index()
532 return __gic_get_rdist_index(d->hwirq); in gic_get_rdist_index()
537 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_setup()
540 return -EINVAL; in gic_irq_nmi_setup()
543 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_setup()
544 return -EINVAL; in gic_irq_nmi_setup()
552 return -EINVAL; in gic_irq_nmi_setup()
564 desc->handle_irq = handle_percpu_devid_fasteoi_nmi; in gic_irq_nmi_setup()
567 desc->handle_irq = handle_fasteoi_nmi; in gic_irq_nmi_setup()
577 struct irq_desc *desc = irq_to_desc(d->irq); in gic_irq_nmi_teardown()
583 pr_err("Cannot set NMI property of enabled IRQ %u\n", d->irq); in gic_irq_nmi_teardown()
600 desc->handle_irq = handle_percpu_devid_irq; in gic_irq_nmi_teardown()
602 desc->handle_irq = handle_fasteoi_irq; in gic_irq_nmi_teardown()
670 return type != IRQ_TYPE_EDGE_RISING ? -EINVAL : 0; in gic_set_type()
675 return -EINVAL; in gic_set_type()
687 pr_warn("GIC: PPI INTID%d is secure or misconfigured\n", irq); in gic_set_type()
697 return -EINVAL; in gic_irq_set_vcpu_affinity()
782 if (generic_handle_domain_irq(gic_data.domain, irqnr)) { in __gic_handle_irq()
795 if (generic_handle_domain_nmi(gic_data.domain, irqnr)) { in __gic_handle_nmi()
796 WARN_ONCE(true, "Unexpected pseudo-NMI (irqnr %u)\n", irqnr); in __gic_handle_nmi()
901 * setting the highest possible, non-zero priority in PMR. in gic_has_group0()
905 * actual priority in the non-secure range. In the process, it in gic_has_group0()
910 gic_write_pmr(BIT(8 - gic_get_pribits())); in gic_has_group0()
930 * Configure SPIs as non-secure Group-1. This will only matter in gic_dist_init()
932 * do the right thing if the kernel is running in secure mode, in gic_dist_init()
980 int ret = -ENODEV; in gic_iterate_rdists()
1014 return ret ? -ENODEV : 0; in gic_iterate_rdists()
1036 u64 offset = ptr - region->redist_base; in __gic_populate_rdist()
1037 raw_spin_lock_init(&gic_data_rdist()->rd_lock); in __gic_populate_rdist()
1039 gic_data_rdist()->phys_base = region->phys_base + offset; in __gic_populate_rdist()
1043 (int)(region - gic_data.redist_regions), in __gic_populate_rdist()
1044 &gic_data_rdist()->phys_base); in __gic_populate_rdist()
1058 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", in gic_populate_rdist()
1061 return -ENODEV; in gic_populate_rdist()
1070 /* Boot-time cleanup */ in __gic_update_rdist_properties()
1090 * doc says... :-/ And CTLR.IR implies another subset of DirectLPI in __gic_update_rdist_properties()
1103 /* Detect non-sensical configurations */ in __gic_update_rdist_properties()
1183 * any pre-emptive interrupts from working at all). Writing a zero in gic_cpu_sys_reg_init()
1252 * - The write is ignored. in gic_cpu_sys_reg_init()
1253 * - The RS field is treated as 0. in gic_cpu_sys_reg_init()
1292 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
1337 cpu--; in gic_compute_target_list()
1369 if (WARN_ON(d->hwirq >= 16)) in gic_ipi_send_mask()
1383 gic_send_sgi(cluster_id, tlist, d->hwirq); in gic_ipi_send_mask()
1402 /* Register all 8 non-secure SGIs */ in gic_smp_init()
1403 base_sgi = irq_domain_alloc_irqs(gic_data.domain, 8, NUMA_NO_NODE, &sgi_fwspec); in gic_smp_init()
1425 return -EINVAL; in gic_set_affinity()
1428 return -EINVAL; in gic_set_affinity()
1542 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1548 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1556 return -EPERM; in gic_irq_domain_map()
1557 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
1562 return -EPERM; in gic_irq_domain_map()
1575 if (fwspec->param_count == 1 && fwspec->param[0] < 16) { in gic_irq_domain_translate()
1576 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1581 if (is_of_node(fwspec->fwnode)) { in gic_irq_domain_translate()
1582 if (fwspec->param_count < 3) in gic_irq_domain_translate()
1583 return -EINVAL; in gic_irq_domain_translate()
1585 switch (fwspec->param[0]) { in gic_irq_domain_translate()
1587 *hwirq = fwspec->param[1] + 32; in gic_irq_domain_translate()
1590 *hwirq = fwspec->param[1] + 16; in gic_irq_domain_translate()
1593 *hwirq = fwspec->param[1] + ESPI_BASE_INTID; in gic_irq_domain_translate()
1596 *hwirq = fwspec->param[1] + EPPI_BASE_INTID; in gic_irq_domain_translate()
1599 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1602 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
1603 if (fwspec->param[1] >= 16) in gic_irq_domain_translate()
1604 *hwirq += EPPI_BASE_INTID - 16; in gic_irq_domain_translate()
1609 return -EINVAL; in gic_irq_domain_translate()
1612 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in gic_irq_domain_translate()
1619 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); in gic_irq_domain_translate()
1623 if (is_fwnode_irqchip(fwspec->fwnode)) { in gic_irq_domain_translate()
1624 if(fwspec->param_count != 2) in gic_irq_domain_translate()
1625 return -EINVAL; in gic_irq_domain_translate()
1627 if (fwspec->param[0] < 16) { in gic_irq_domain_translate()
1629 fwspec->param[0]); in gic_irq_domain_translate()
1630 return -EINVAL; in gic_irq_domain_translate()
1633 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
1634 *type = fwspec->param[1]; in gic_irq_domain_translate()
1640 return -EINVAL; in gic_irq_domain_translate()
1643 static int gic_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, in gic_irq_domain_alloc() argument
1651 ret = gic_irq_domain_translate(domain, fwspec, &hwirq, &type); in gic_irq_domain_alloc()
1656 ret = gic_irq_domain_map(domain, virq + i, hwirq + i); in gic_irq_domain_alloc()
1664 static void gic_irq_domain_free(struct irq_domain *domain, unsigned int virq, in gic_irq_domain_free() argument
1670 struct irq_data *d = irq_domain_get_irq_data(domain, virq + i); in gic_irq_domain_free()
1684 if (!is_of_node(fwspec->fwnode)) in fwspec_is_partitioned_ppi()
1687 if (fwspec->param_count < 4 || !fwspec->param[3]) in fwspec_is_partitioned_ppi()
1705 if (fwspec->fwnode != d->fwnode) in gic_irq_domain_select()
1708 /* If this is not DT, then we have a single domain */ in gic_irq_domain_select()
1709 if (!is_of_node(fwspec->fwnode)) in gic_irq_domain_select()
1717 return d == gic_data.domain; in gic_irq_domain_select()
1720 * If this is a PPI and we have a 4th (non-null) parameter, in gic_irq_domain_select()
1721 * then we need to match the partition domain. in gic_irq_domain_select()
1745 return -ENOMEM; in partition_domain_translate()
1747 np = of_find_node_by_phandle(fwspec->param[3]); in partition_domain_translate()
1749 return -EINVAL; in partition_domain_translate()
1762 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in partition_domain_translate()
1776 d->flags |= FLAGS_WORKAROUND_GICR_WAKER_MSM8996; in gic_enable_quirk_msm8996()
1785 d->flags |= FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539; in gic_enable_quirk_cavium_38539()
1795 * HIP06 GICD_IIDR clashes with GIC-600 product number (despite in gic_enable_quirk_hip06_07()
1797 * that GIC-600 doesn't have ESPI, so nothing to do in that case. in gic_enable_quirk_hip06_07()
1801 if (d->rdists.gicd_typer & GICD_TYPER_ESPI) { in gic_enable_quirk_hip06_07()
1803 d->rdists.gicd_typer &= ~GENMASK(9, 8); in gic_enable_quirk_hip06_07()
1851 d->flags |= FLAGS_WORKAROUND_ASR_ERRATUM_8601001; in gic_enable_quirk_asr8601()
1866 d->rdists.flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; in rd_set_non_coherent()
1873 .compatible = "qcom,msm8996-gic-v3",
1878 .compatible = "asr,asr8601-gic-v3",
1897 * - ThunderX: CN88xx
1898 * - OCTEON TX: CN83xx, CN81xx
1899 * - OCTEON TX2: CN93xx, CN96xx, CN98xx, CNF95xx*
1907 .desc = "GICv3: NVIDIA erratum T241-FABRIC-4",
1914 * GIC-700: 2941627 workaround - IP variant [0,1]
1924 * GIC-700: 2941627 workaround - IP variant [2]
1932 .desc = "GICv3: non-coherent attribute",
1933 .property = "dma-noncoherent",
1955 pr_info("Pseudo-NMIs enabled using %s ICC_PMR_EL1 synchronisation\n", in gic_enable_nmi_support()
1961 * and if Group 0 interrupts can be delivered to Linux in the non-secure in gic_enable_nmi_support()
1967 * ----------------------------------------------------------- in gic_enable_nmi_support()
1968 * 1 | - | unchanged | unchanged in gic_enable_nmi_support()
1969 * ----------------------------------------------------------- in gic_enable_nmi_support()
1970 * 0 | 1 | non-secure | non-secure in gic_enable_nmi_support()
1971 * ----------------------------------------------------------- in gic_enable_nmi_support()
1972 * 0 | 0 | unchanged | non-secure in gic_enable_nmi_support()
1974 * where non-secure means that the value is right-shifted by one and the in gic_enable_nmi_support()
1975 * MSB bit set, to make it fit in the non-secure priority range. in gic_enable_nmi_support()
1982 * be in the non-secure range, we use a different PMR value to mask IRQs in gic_enable_nmi_support()
2028 pr_info("%d SPIs implemented\n", GIC_LINE_NR - 32); in gic_init_bases()
2038 gic_data.domain = irq_domain_create_tree(handle, &gic_irq_domain_ops, in gic_init_bases()
2042 /* Disable GICv4.x features for the erratum T241-FABRIC-4 */ in gic_init_bases()
2049 if (WARN_ON(!gic_data.domain) || WARN_ON(!gic_data.rdists.rdist)) { in gic_init_bases()
2050 err = -ENOMEM; in gic_init_bases()
2054 irq_domain_update_bus_token(gic_data.domain, DOMAIN_BUS_WIRED); in gic_init_bases()
2059 err = mbi_init(handle, gic_data.domain); in gic_init_bases()
2075 its_init(handle, &gic_data.rdists, gic_data.domain); in gic_init_bases()
2080 gicv2m_init(handle, gic_data.domain); in gic_init_bases()
2086 if (gic_data.domain) in gic_init_bases()
2087 irq_domain_remove(gic_data.domain); in gic_init_bases()
2097 return -ENODEV; in gic_validate_dist_version()
2110 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); in gic_populate_ppi_partitions()
2133 part->partition_id = of_node_to_fwnode(child_part); in gic_populate_ppi_partitions()
2164 cpumask_set_cpu(cpu, &part->mask); in gic_populate_ppi_partitions()
2212 if (of_property_read_u32(node, "#redistributor-regions", in gic_of_setup_kvm_info()
2244 gic_request_region(res->start, resource_size(res), name); in gic_of_iomap()
2247 return base ?: IOMEM_ERR_PTR(-ENOMEM); in gic_of_iomap()
2274 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) in gic_of_init()
2280 err = -ENOMEM; in gic_of_init()
2288 err = -ENODEV; in gic_of_init()
2294 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) in gic_of_init()
2300 nr_redist_regions, redist_stride, &node->fwnode); in gic_of_init()
2320 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
2354 redist_base = ioremap(redist->base_address, redist->length); in gic_acpi_parse_madt_redist()
2356 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
2357 return -ENOMEM; in gic_acpi_parse_madt_redist()
2359 gic_request_region(redist->base_address, redist->length, "GICR"); in gic_acpi_parse_madt_redist()
2361 gic_acpi_register_redist(redist->base_address, redist_base); in gic_acpi_parse_madt_redist()
2378 redist_base = ioremap(gicc->gicr_base_address, size); in gic_acpi_parse_madt_gicc()
2380 return -ENOMEM; in gic_acpi_parse_madt_gicc()
2381 gic_request_region(gicc->gicr_base_address, size, "GICR"); in gic_acpi_parse_madt_gicc()
2383 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); in gic_acpi_parse_madt_gicc()
2405 return -ENODEV; in gic_acpi_collect_gicr_base()
2425 if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { in gic_acpi_match_gicc()
2437 return -ENODEV; in gic_acpi_match_gicc()
2473 if (dist->version != ape->driver_data) in acpi_validate_gic_table()
2496 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? in gic_acpi_parse_virt_madt_gicc()
2502 acpi_data.maint_irq = gicc->vgic_interrupt; in gic_acpi_parse_virt_madt_gicc()
2504 acpi_data.vcpu_base = gicc->gicv_base_address; in gic_acpi_parse_virt_madt_gicc()
2512 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || in gic_acpi_parse_virt_madt_gicc()
2514 (acpi_data.vcpu_base != gicc->gicv_base_address)) in gic_acpi_parse_virt_madt_gicc()
2515 return -EINVAL; in gic_acpi_parse_virt_madt_gicc()
2556 vcpu->flags = IORESOURCE_MEM; in gic_acpi_setup_kvm_info()
2557 vcpu->start = acpi_data.vcpu_base; in gic_acpi_setup_kvm_info()
2558 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; in gic_acpi_setup_kvm_info()
2582 acpi_data.dist_base = ioremap(dist->base_address, in gic_acpi_init()
2586 return -ENOMEM; in gic_acpi_init()
2588 gic_request_region(dist->base_address, ACPI_GICV3_DIST_MEM_SIZE, "GICD"); in gic_acpi_init()
2600 err = -ENOMEM; in gic_acpi_init()
2608 gsi_domain_handle = irq_domain_alloc_fwnode(&dist->base_address); in gic_acpi_init()
2610 err = -ENOMEM; in gic_acpi_init()
2614 err = gic_init_bases(dist->base_address, acpi_data.dist_base, in gic_acpi_init()