Lines Matching +full:synquacer +full:- +full:pre +full:- +full:its
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/arm-gic-v4.h>
40 #include "irq-gic-common.h"
65 * Collection structure - just an ID, and a redistributor address to
75 * The ITS_BASER structure - contains memory information, cached
76 * value of BASER register configuration and ITS page size.
88 * The ITS structure - contains most of the infrastructure, with the
89 * top-level MSI domain, the command queue, the collections, and the
118 u32 pre_its_base; /* for Socionext Synquacer */
122 #define is_v4(its) (!!((its)->typer & GITS_TYPER_VLPIS)) argument
123 #define is_v4_1(its) (!!((its)->typer & GITS_TYPER_VMAPP)) argument
124 #define device_ids(its) (FIELD_GET(GITS_TYPER_DEVBITS, (its)->typer) + 1) argument
132 if (gic_rdists->has_rvpeid && \
133 gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
134 nvpeid = 1 + (gic_rdists->gicd_typer2 & \
156 * The ITS view of a device - belongs to an ITS, owns an interrupt
157 * translation table, and a list of interrupts. If it some of its
163 struct its_node *its; member
196 #define gic_data_rdist() (raw_cpu_ptr(gic_rdists->rdist))
197 #define gic_data_rdist_cpu(cpu) (per_cpu_ptr(gic_rdists->rdist, cpu))
198 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
205 static bool require_its_list_vmovp(struct its_vm *vm, struct its_node *its) in require_its_list_vmovp() argument
207 return (gic_rdists->has_rvpeid || vm->vlpi_count[its->list_nr]); in require_its_list_vmovp()
212 return !(gic_rdists->flags & RDIST_FLAGS_FORCE_NON_SHAREABLE); in rdists_support_shareable()
217 struct its_node *its; in get_its_list() local
220 list_for_each_entry(its, &its_nodes, entry) { in get_its_list()
221 if (!is_v4(its)) in get_its_list()
224 if (require_its_list_vmovp(vm, its)) in get_its_list()
225 __set_bit(its->list_nr, &its_list); in get_its_list()
234 return d->hwirq - its_dev->event_map.lpi_base; in its_get_event_id()
240 struct its_node *its = its_dev->its; in dev_event_to_col() local
242 return its->collections + its_dev->event_map.col_map[event]; in dev_event_to_col()
248 if (WARN_ON_ONCE(event >= its_dev->event_map.nr_lpis)) in dev_event_to_vlpi_map()
251 return &its_dev->event_map.vlpi_maps[event]; in dev_event_to_vlpi_map()
268 raw_spin_lock_irqsave(&vpe->vpe_lock, *flags); in vpe_to_cpuid_lock()
269 return vpe->col_idx; in vpe_to_cpuid_lock()
274 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in vpe_to_cpuid_unlock()
284 if (d->chip == &its_vpe_irq_chip) { in irq_to_cpuid_lock()
289 vpe = map->vpe; in irq_to_cpuid_lock()
297 cpu = its_dev->event_map.col_map[its_get_event_id(d)]; in irq_to_cpuid_lock()
309 if (d->chip == &its_vpe_irq_chip) { in irq_to_cpuid_unlock()
314 vpe = map->vpe; in irq_to_cpuid_unlock()
323 if (WARN_ON_ONCE(col->target_address & GENMASK_ULL(15, 0))) in valid_col()
329 static struct its_vpe *valid_vpe(struct its_node *its, struct its_vpe *vpe) in valid_vpe() argument
331 if (valid_col(its->collections + vpe->col_idx)) in valid_vpe()
338 * ITS command descriptors - parameters to be encoded in a command
437 * The ITS command block, which is what the ITS actually parses.
466 its_mask_encode(&cmd->raw_cmd[0], cmd_nr, 7, 0); in its_encode_cmd()
471 its_mask_encode(&cmd->raw_cmd[0], devid, 63, 32); in its_encode_devid()
476 its_mask_encode(&cmd->raw_cmd[1], id, 31, 0); in its_encode_event_id()
481 its_mask_encode(&cmd->raw_cmd[1], phys_id, 63, 32); in its_encode_phys_id()
486 its_mask_encode(&cmd->raw_cmd[1], size, 4, 0); in its_encode_size()
491 its_mask_encode(&cmd->raw_cmd[2], itt_addr >> 8, 51, 8); in its_encode_itt()
496 its_mask_encode(&cmd->raw_cmd[2], !!valid, 63, 63); in its_encode_valid()
501 its_mask_encode(&cmd->raw_cmd[2], target_addr >> 16, 51, 16); in its_encode_target()
506 its_mask_encode(&cmd->raw_cmd[2], col, 15, 0); in its_encode_collection()
511 its_mask_encode(&cmd->raw_cmd[1], vpeid, 47, 32); in its_encode_vpeid()
516 its_mask_encode(&cmd->raw_cmd[2], virt_id, 31, 0); in its_encode_virt_id()
521 its_mask_encode(&cmd->raw_cmd[2], db_phys_id, 63, 32); in its_encode_db_phys_id()
526 its_mask_encode(&cmd->raw_cmd[2], db_valid, 0, 0); in its_encode_db_valid()
531 its_mask_encode(&cmd->raw_cmd[0], seq_num, 47, 32); in its_encode_seq_num()
536 its_mask_encode(&cmd->raw_cmd[1], its_list, 15, 0); in its_encode_its_list()
541 its_mask_encode(&cmd->raw_cmd[3], vpt_pa >> 16, 51, 16); in its_encode_vpt_addr()
546 its_mask_encode(&cmd->raw_cmd[3], vpt_size, 4, 0); in its_encode_vpt_size()
551 its_mask_encode(&cmd->raw_cmd[0], vconf_pa >> 16, 51, 16); in its_encode_vconf_addr()
556 its_mask_encode(&cmd->raw_cmd[0], alloc, 8, 8); in its_encode_alloc()
561 its_mask_encode(&cmd->raw_cmd[0], ptz, 9, 9); in its_encode_ptz()
567 its_mask_encode(&cmd->raw_cmd[1], vpe_db_lpi, 31, 0); in its_encode_vmapp_default_db()
573 its_mask_encode(&cmd->raw_cmd[3], vpe_db_lpi, 31, 0); in its_encode_vmovp_default_db()
578 its_mask_encode(&cmd->raw_cmd[2], db, 63, 63); in its_encode_db()
583 its_mask_encode(&cmd->raw_cmd[0], sgi, 35, 32); in its_encode_sgi_intid()
588 its_mask_encode(&cmd->raw_cmd[0], prio >> 4, 23, 20); in its_encode_sgi_priority()
593 its_mask_encode(&cmd->raw_cmd[0], grp, 10, 10); in its_encode_sgi_group()
598 its_mask_encode(&cmd->raw_cmd[0], clr, 9, 9); in its_encode_sgi_clear()
603 its_mask_encode(&cmd->raw_cmd[0], en, 8, 8); in its_encode_sgi_enable()
609 cmd->raw_cmd_le[0] = cpu_to_le64(cmd->raw_cmd[0]); in its_fixup_cmd()
610 cmd->raw_cmd_le[1] = cpu_to_le64(cmd->raw_cmd[1]); in its_fixup_cmd()
611 cmd->raw_cmd_le[2] = cpu_to_le64(cmd->raw_cmd[2]); in its_fixup_cmd()
612 cmd->raw_cmd_le[3] = cpu_to_le64(cmd->raw_cmd[3]); in its_fixup_cmd()
615 static struct its_collection *its_build_mapd_cmd(struct its_node *its, in its_build_mapd_cmd() argument
620 u8 size = ilog2(desc->its_mapd_cmd.dev->nr_ites); in its_build_mapd_cmd()
622 itt_addr = virt_to_phys(desc->its_mapd_cmd.dev->itt); in its_build_mapd_cmd()
626 its_encode_devid(cmd, desc->its_mapd_cmd.dev->device_id); in its_build_mapd_cmd()
627 its_encode_size(cmd, size - 1); in its_build_mapd_cmd()
629 its_encode_valid(cmd, desc->its_mapd_cmd.valid); in its_build_mapd_cmd()
636 static struct its_collection *its_build_mapc_cmd(struct its_node *its, in its_build_mapc_cmd() argument
641 its_encode_collection(cmd, desc->its_mapc_cmd.col->col_id); in its_build_mapc_cmd()
642 its_encode_target(cmd, desc->its_mapc_cmd.col->target_address); in its_build_mapc_cmd()
643 its_encode_valid(cmd, desc->its_mapc_cmd.valid); in its_build_mapc_cmd()
647 return desc->its_mapc_cmd.col; in its_build_mapc_cmd()
650 static struct its_collection *its_build_mapti_cmd(struct its_node *its, in its_build_mapti_cmd() argument
656 col = dev_event_to_col(desc->its_mapti_cmd.dev, in its_build_mapti_cmd()
657 desc->its_mapti_cmd.event_id); in its_build_mapti_cmd()
660 its_encode_devid(cmd, desc->its_mapti_cmd.dev->device_id); in its_build_mapti_cmd()
661 its_encode_event_id(cmd, desc->its_mapti_cmd.event_id); in its_build_mapti_cmd()
662 its_encode_phys_id(cmd, desc->its_mapti_cmd.phys_id); in its_build_mapti_cmd()
663 its_encode_collection(cmd, col->col_id); in its_build_mapti_cmd()
670 static struct its_collection *its_build_movi_cmd(struct its_node *its, in its_build_movi_cmd() argument
676 col = dev_event_to_col(desc->its_movi_cmd.dev, in its_build_movi_cmd()
677 desc->its_movi_cmd.event_id); in its_build_movi_cmd()
680 its_encode_devid(cmd, desc->its_movi_cmd.dev->device_id); in its_build_movi_cmd()
681 its_encode_event_id(cmd, desc->its_movi_cmd.event_id); in its_build_movi_cmd()
682 its_encode_collection(cmd, desc->its_movi_cmd.col->col_id); in its_build_movi_cmd()
689 static struct its_collection *its_build_discard_cmd(struct its_node *its, in its_build_discard_cmd() argument
695 col = dev_event_to_col(desc->its_discard_cmd.dev, in its_build_discard_cmd()
696 desc->its_discard_cmd.event_id); in its_build_discard_cmd()
699 its_encode_devid(cmd, desc->its_discard_cmd.dev->device_id); in its_build_discard_cmd()
700 its_encode_event_id(cmd, desc->its_discard_cmd.event_id); in its_build_discard_cmd()
707 static struct its_collection *its_build_inv_cmd(struct its_node *its, in its_build_inv_cmd() argument
713 col = dev_event_to_col(desc->its_inv_cmd.dev, in its_build_inv_cmd()
714 desc->its_inv_cmd.event_id); in its_build_inv_cmd()
717 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); in its_build_inv_cmd()
718 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); in its_build_inv_cmd()
725 static struct its_collection *its_build_int_cmd(struct its_node *its, in its_build_int_cmd() argument
731 col = dev_event_to_col(desc->its_int_cmd.dev, in its_build_int_cmd()
732 desc->its_int_cmd.event_id); in its_build_int_cmd()
735 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); in its_build_int_cmd()
736 its_encode_event_id(cmd, desc->its_int_cmd.event_id); in its_build_int_cmd()
743 static struct its_collection *its_build_clear_cmd(struct its_node *its, in its_build_clear_cmd() argument
749 col = dev_event_to_col(desc->its_clear_cmd.dev, in its_build_clear_cmd()
750 desc->its_clear_cmd.event_id); in its_build_clear_cmd()
753 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); in its_build_clear_cmd()
754 its_encode_event_id(cmd, desc->its_clear_cmd.event_id); in its_build_clear_cmd()
761 static struct its_collection *its_build_invall_cmd(struct its_node *its, in its_build_invall_cmd() argument
766 its_encode_collection(cmd, desc->its_invall_cmd.col->col_id); in its_build_invall_cmd()
770 return desc->its_invall_cmd.col; in its_build_invall_cmd()
773 static struct its_vpe *its_build_vinvall_cmd(struct its_node *its, in its_build_vinvall_cmd() argument
778 its_encode_vpeid(cmd, desc->its_vinvall_cmd.vpe->vpe_id); in its_build_vinvall_cmd()
782 return valid_vpe(its, desc->its_vinvall_cmd.vpe); in its_build_vinvall_cmd()
785 static struct its_vpe *its_build_vmapp_cmd(struct its_node *its, in its_build_vmapp_cmd() argument
794 its_encode_vpeid(cmd, desc->its_vmapp_cmd.vpe->vpe_id); in its_build_vmapp_cmd()
795 its_encode_valid(cmd, desc->its_vmapp_cmd.valid); in its_build_vmapp_cmd()
797 if (!desc->its_vmapp_cmd.valid) { in its_build_vmapp_cmd()
798 if (is_v4_1(its)) { in its_build_vmapp_cmd()
799 alloc = !atomic_dec_return(&desc->its_vmapp_cmd.vpe->vmapp_count); in its_build_vmapp_cmd()
806 vpt_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->vpt_page)); in its_build_vmapp_cmd()
807 target = desc->its_vmapp_cmd.col->target_address + its->vlpi_redist_offset; in its_build_vmapp_cmd()
811 its_encode_vpt_size(cmd, LPI_NRBITS - 1); in its_build_vmapp_cmd()
813 if (!is_v4_1(its)) in its_build_vmapp_cmd()
816 vconf_addr = virt_to_phys(page_address(desc->its_vmapp_cmd.vpe->its_vm->vprop_page)); in its_build_vmapp_cmd()
818 alloc = !atomic_fetch_inc(&desc->its_vmapp_cmd.vpe->vmapp_count); in its_build_vmapp_cmd()
830 its_encode_vmapp_default_db(cmd, desc->its_vmapp_cmd.vpe->vpe_db_lpi); in its_build_vmapp_cmd()
835 return valid_vpe(its, desc->its_vmapp_cmd.vpe); in its_build_vmapp_cmd()
838 static struct its_vpe *its_build_vmapti_cmd(struct its_node *its, in its_build_vmapti_cmd() argument
844 if (!is_v4_1(its) && desc->its_vmapti_cmd.db_enabled) in its_build_vmapti_cmd()
845 db = desc->its_vmapti_cmd.vpe->vpe_db_lpi; in its_build_vmapti_cmd()
850 its_encode_devid(cmd, desc->its_vmapti_cmd.dev->device_id); in its_build_vmapti_cmd()
851 its_encode_vpeid(cmd, desc->its_vmapti_cmd.vpe->vpe_id); in its_build_vmapti_cmd()
852 its_encode_event_id(cmd, desc->its_vmapti_cmd.event_id); in its_build_vmapti_cmd()
854 its_encode_virt_id(cmd, desc->its_vmapti_cmd.virt_id); in its_build_vmapti_cmd()
858 return valid_vpe(its, desc->its_vmapti_cmd.vpe); in its_build_vmapti_cmd()
861 static struct its_vpe *its_build_vmovi_cmd(struct its_node *its, in its_build_vmovi_cmd() argument
867 if (!is_v4_1(its) && desc->its_vmovi_cmd.db_enabled) in its_build_vmovi_cmd()
868 db = desc->its_vmovi_cmd.vpe->vpe_db_lpi; in its_build_vmovi_cmd()
873 its_encode_devid(cmd, desc->its_vmovi_cmd.dev->device_id); in its_build_vmovi_cmd()
874 its_encode_vpeid(cmd, desc->its_vmovi_cmd.vpe->vpe_id); in its_build_vmovi_cmd()
875 its_encode_event_id(cmd, desc->its_vmovi_cmd.event_id); in its_build_vmovi_cmd()
881 return valid_vpe(its, desc->its_vmovi_cmd.vpe); in its_build_vmovi_cmd()
884 static struct its_vpe *its_build_vmovp_cmd(struct its_node *its, in its_build_vmovp_cmd() argument
890 target = desc->its_vmovp_cmd.col->target_address + its->vlpi_redist_offset; in its_build_vmovp_cmd()
892 its_encode_seq_num(cmd, desc->its_vmovp_cmd.seq_num); in its_build_vmovp_cmd()
893 its_encode_its_list(cmd, desc->its_vmovp_cmd.its_list); in its_build_vmovp_cmd()
894 its_encode_vpeid(cmd, desc->its_vmovp_cmd.vpe->vpe_id); in its_build_vmovp_cmd()
897 if (is_v4_1(its)) { in its_build_vmovp_cmd()
899 its_encode_vmovp_default_db(cmd, desc->its_vmovp_cmd.vpe->vpe_db_lpi); in its_build_vmovp_cmd()
904 return valid_vpe(its, desc->its_vmovp_cmd.vpe); in its_build_vmovp_cmd()
907 static struct its_vpe *its_build_vinv_cmd(struct its_node *its, in its_build_vinv_cmd() argument
913 map = dev_event_to_vlpi_map(desc->its_inv_cmd.dev, in its_build_vinv_cmd()
914 desc->its_inv_cmd.event_id); in its_build_vinv_cmd()
917 its_encode_devid(cmd, desc->its_inv_cmd.dev->device_id); in its_build_vinv_cmd()
918 its_encode_event_id(cmd, desc->its_inv_cmd.event_id); in its_build_vinv_cmd()
922 return valid_vpe(its, map->vpe); in its_build_vinv_cmd()
925 static struct its_vpe *its_build_vint_cmd(struct its_node *its, in its_build_vint_cmd() argument
931 map = dev_event_to_vlpi_map(desc->its_int_cmd.dev, in its_build_vint_cmd()
932 desc->its_int_cmd.event_id); in its_build_vint_cmd()
935 its_encode_devid(cmd, desc->its_int_cmd.dev->device_id); in its_build_vint_cmd()
936 its_encode_event_id(cmd, desc->its_int_cmd.event_id); in its_build_vint_cmd()
940 return valid_vpe(its, map->vpe); in its_build_vint_cmd()
943 static struct its_vpe *its_build_vclear_cmd(struct its_node *its, in its_build_vclear_cmd() argument
949 map = dev_event_to_vlpi_map(desc->its_clear_cmd.dev, in its_build_vclear_cmd()
950 desc->its_clear_cmd.event_id); in its_build_vclear_cmd()
953 its_encode_devid(cmd, desc->its_clear_cmd.dev->device_id); in its_build_vclear_cmd()
954 its_encode_event_id(cmd, desc->its_clear_cmd.event_id); in its_build_vclear_cmd()
958 return valid_vpe(its, map->vpe); in its_build_vclear_cmd()
961 static struct its_vpe *its_build_invdb_cmd(struct its_node *its, in its_build_invdb_cmd() argument
965 if (WARN_ON(!is_v4_1(its))) in its_build_invdb_cmd()
969 its_encode_vpeid(cmd, desc->its_invdb_cmd.vpe->vpe_id); in its_build_invdb_cmd()
973 return valid_vpe(its, desc->its_invdb_cmd.vpe); in its_build_invdb_cmd()
976 static struct its_vpe *its_build_vsgi_cmd(struct its_node *its, in its_build_vsgi_cmd() argument
980 if (WARN_ON(!is_v4_1(its))) in its_build_vsgi_cmd()
984 its_encode_vpeid(cmd, desc->its_vsgi_cmd.vpe->vpe_id); in its_build_vsgi_cmd()
985 its_encode_sgi_intid(cmd, desc->its_vsgi_cmd.sgi); in its_build_vsgi_cmd()
986 its_encode_sgi_priority(cmd, desc->its_vsgi_cmd.priority); in its_build_vsgi_cmd()
987 its_encode_sgi_group(cmd, desc->its_vsgi_cmd.group); in its_build_vsgi_cmd()
988 its_encode_sgi_clear(cmd, desc->its_vsgi_cmd.clear); in its_build_vsgi_cmd()
989 its_encode_sgi_enable(cmd, desc->its_vsgi_cmd.enable); in its_build_vsgi_cmd()
993 return valid_vpe(its, desc->its_vsgi_cmd.vpe); in its_build_vsgi_cmd()
996 static u64 its_cmd_ptr_to_offset(struct its_node *its, in its_cmd_ptr_to_offset() argument
999 return (ptr - its->cmd_base) * sizeof(*ptr); in its_cmd_ptr_to_offset()
1002 static int its_queue_full(struct its_node *its) in its_queue_full() argument
1007 widx = its->cmd_write - its->cmd_base; in its_queue_full()
1008 ridx = readl_relaxed(its->base + GITS_CREADR) / sizeof(struct its_cmd_block); in its_queue_full()
1010 /* This is incredibly unlikely to happen, unless the ITS locks up. */ in its_queue_full()
1017 static struct its_cmd_block *its_allocate_entry(struct its_node *its) in its_allocate_entry() argument
1022 while (its_queue_full(its)) { in its_allocate_entry()
1023 count--; in its_allocate_entry()
1025 pr_err_ratelimited("ITS queue not draining\n"); in its_allocate_entry()
1032 cmd = its->cmd_write++; in its_allocate_entry()
1035 if (its->cmd_write == (its->cmd_base + ITS_CMD_QUEUE_NR_ENTRIES)) in its_allocate_entry()
1036 its->cmd_write = its->cmd_base; in its_allocate_entry()
1039 cmd->raw_cmd[0] = 0; in its_allocate_entry()
1040 cmd->raw_cmd[1] = 0; in its_allocate_entry()
1041 cmd->raw_cmd[2] = 0; in its_allocate_entry()
1042 cmd->raw_cmd[3] = 0; in its_allocate_entry()
1047 static struct its_cmd_block *its_post_commands(struct its_node *its) in its_post_commands() argument
1049 u64 wr = its_cmd_ptr_to_offset(its, its->cmd_write); in its_post_commands()
1051 writel_relaxed(wr, its->base + GITS_CWRITER); in its_post_commands()
1053 return its->cmd_write; in its_post_commands()
1056 static void its_flush_cmd(struct its_node *its, struct its_cmd_block *cmd) in its_flush_cmd() argument
1060 * the ITS. in its_flush_cmd()
1062 if (its->flags & ITS_FLAGS_CMDQ_NEEDS_FLUSHING) in its_flush_cmd()
1068 static int its_wait_for_range_completion(struct its_node *its, in its_wait_for_range_completion() argument
1076 to_idx = its_cmd_ptr_to_offset(its, to); in its_wait_for_range_completion()
1085 rd_idx = readl_relaxed(its->base + GITS_CREADR); in its_wait_for_range_completion()
1089 * potential wrap-around into account. in its_wait_for_range_completion()
1091 delta = rd_idx - prev_idx; in its_wait_for_range_completion()
1099 count--; in its_wait_for_range_completion()
1101 pr_err_ratelimited("ITS queue timeout (%llu %llu)\n", in its_wait_for_range_completion()
1103 return -1; in its_wait_for_range_completion()
1115 void name(struct its_node *its, \
1124 raw_spin_lock_irqsave(&its->lock, flags); \
1126 cmd = its_allocate_entry(its); \
1128 raw_spin_unlock_irqrestore(&its->lock, flags); \
1131 sync_obj = builder(its, cmd, desc); \
1132 its_flush_cmd(its, cmd); \
1135 sync_cmd = its_allocate_entry(its); \
1139 buildfn(its, sync_cmd, sync_obj); \
1140 its_flush_cmd(its, sync_cmd); \
1144 rd_idx = readl_relaxed(its->base + GITS_CREADR); \
1145 next_cmd = its_post_commands(its); \
1146 raw_spin_unlock_irqrestore(&its->lock, flags); \
1148 if (its_wait_for_range_completion(its, rd_idx, next_cmd)) \
1149 pr_err_ratelimited("ITS cmd %ps failed\n", builder); \
1152 static void its_build_sync_cmd(struct its_node *its, in its_build_sync_cmd() argument
1157 its_encode_target(sync_cmd, sync_col->target_address); in its_build_sync_cmd()
1165 static void its_build_vsync_cmd(struct its_node *its, in BUILD_SINGLE_CMD_FUNC()
1170 its_encode_vpeid(sync_cmd, sync_vpe->vpe_id); in BUILD_SINGLE_CMD_FUNC()
1185 its_send_single_command(dev->its, its_build_int_cmd, &desc); in BUILD_SINGLE_CMD_FUNC()
1195 its_send_single_command(dev->its, its_build_clear_cmd, &desc); in its_send_clear()
1205 its_send_single_command(dev->its, its_build_inv_cmd, &desc); in its_send_inv()
1215 its_send_single_command(dev->its, its_build_mapd_cmd, &desc); in its_send_mapd()
1218 static void its_send_mapc(struct its_node *its, struct its_collection *col, in its_send_mapc() argument
1226 its_send_single_command(its, its_build_mapc_cmd, &desc); in its_send_mapc()
1237 its_send_single_command(dev->its, its_build_mapti_cmd, &desc); in its_send_mapti()
1249 its_send_single_command(dev->its, its_build_movi_cmd, &desc); in its_send_movi()
1259 its_send_single_command(dev->its, its_build_discard_cmd, &desc); in its_send_discard()
1262 static void its_send_invall(struct its_node *its, struct its_collection *col) in its_send_invall() argument
1268 its_send_single_command(its, its_build_invall_cmd, &desc); in its_send_invall()
1276 desc.its_vmapti_cmd.vpe = map->vpe; in its_send_vmapti()
1278 desc.its_vmapti_cmd.virt_id = map->vintid; in its_send_vmapti()
1280 desc.its_vmapti_cmd.db_enabled = map->db_enabled; in its_send_vmapti()
1282 its_send_single_vcommand(dev->its, its_build_vmapti_cmd, &desc); in its_send_vmapti()
1290 desc.its_vmovi_cmd.vpe = map->vpe; in its_send_vmovi()
1293 desc.its_vmovi_cmd.db_enabled = map->db_enabled; in its_send_vmovi()
1295 its_send_single_vcommand(dev->its, its_build_vmovi_cmd, &desc); in its_send_vmovi()
1298 static void its_send_vmapp(struct its_node *its, in its_send_vmapp() argument
1305 desc.its_vmapp_cmd.col = &its->collections[vpe->col_idx]; in its_send_vmapp()
1307 its_send_single_vcommand(its, its_build_vmapp_cmd, &desc); in its_send_vmapp()
1313 struct its_node *its; in its_send_vmovp() local
1315 int col_id = vpe->col_idx; in its_send_vmovp()
1320 its = list_first_entry(&its_nodes, struct its_node, entry); in its_send_vmovp()
1321 desc.its_vmovp_cmd.col = &its->collections[col_id]; in its_send_vmovp()
1322 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); in its_send_vmovp()
1332 * Wall <-- Head. in its_send_vmovp()
1337 desc.its_vmovp_cmd.its_list = get_its_list(vpe->its_vm); in its_send_vmovp()
1340 list_for_each_entry(its, &its_nodes, entry) { in its_send_vmovp()
1341 if (!is_v4(its)) in its_send_vmovp()
1344 if (!require_its_list_vmovp(vpe->its_vm, its)) in its_send_vmovp()
1347 desc.its_vmovp_cmd.col = &its->collections[col_id]; in its_send_vmovp()
1348 its_send_single_vcommand(its, its_build_vmovp_cmd, &desc); in its_send_vmovp()
1354 static void its_send_vinvall(struct its_node *its, struct its_vpe *vpe) in its_send_vinvall() argument
1359 its_send_single_vcommand(its, its_build_vinvall_cmd, &desc); in its_send_vinvall()
1373 its_send_single_vcommand(dev->its, its_build_vinv_cmd, &desc); in its_send_vinv()
1387 its_send_single_vcommand(dev->its, its_build_vint_cmd, &desc); in its_send_vint()
1401 its_send_single_vcommand(dev->its, its_build_vclear_cmd, &desc); in its_send_vclear()
1404 static void its_send_invdb(struct its_node *its, struct its_vpe *vpe) in its_send_invdb() argument
1409 its_send_single_vcommand(its, its_build_invdb_cmd, &desc); in its_send_invdb()
1413 * irqchip functions - assumes MSI, mostly.
1423 va = page_address(map->vm->vprop_page); in lpi_write_config()
1424 hwirq = map->vintid; in lpi_write_config()
1427 map->properties &= ~clr; in lpi_write_config()
1428 map->properties |= set | LPI_PROP_GROUP1; in lpi_write_config()
1430 va = gic_rdists->prop_table_va; in lpi_write_config()
1431 hwirq = d->hwirq; in lpi_write_config()
1434 cfg = va + hwirq - 8192; in lpi_write_config()
1443 if (gic_rdists->flags & RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING) in lpi_write_config()
1463 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in __direct_lpi_inv()
1465 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; in __direct_lpi_inv()
1469 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in __direct_lpi_inv()
1481 WARN_ON(!is_v4_1(its_dev->its)); in direct_lpi_inv()
1484 val |= FIELD_PREP(GICR_INVLPIR_VPEID, map->vpe->vpe_id); in direct_lpi_inv()
1485 val |= FIELD_PREP(GICR_INVLPIR_INTID, map->vintid); in direct_lpi_inv()
1487 val = d->hwirq; in direct_lpi_inv()
1498 if (gic_rdists->has_direct_lpi && in lpi_update_config()
1499 (is_v4_1(its_dev->its) || !irqd_is_forwarded_to_vcpu(d))) in lpi_update_config()
1514 * GICv4.1 does away with the per-LPI nonsense, nothing to do in its_vlpi_set_doorbell()
1517 if (is_v4_1(its_dev->its)) in its_vlpi_set_doorbell()
1522 if (map->db_enabled == enable) in its_vlpi_set_doorbell()
1525 map->db_enabled = enable; in its_vlpi_set_doorbell()
1530 * Ideally, we'd issue a VMAPTI to set the doorbell to its LPI in its_vlpi_set_doorbell()
1559 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_read_lpi_count()
1561 return atomic_read(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_read_lpi_count()
1567 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_inc_lpi_count()
1569 atomic_inc(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_inc_lpi_count()
1575 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->managed); in its_dec_lpi_count()
1577 atomic_dec(&per_cpu_ptr(&cpu_lpi_count, cpu)->unmanaged); in its_dec_lpi_count()
1610 node = its_dev->its->numa_node; in its_select_cpu()
1632 * ITS placed next to two NUMA nodes. in its_select_cpu()
1642 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144)) in its_select_cpu()
1660 if ((its_dev->its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) && in its_select_cpu()
1669 pr_debug("IRQ%d -> %*pbl CPU%d\n", d->irq, cpumask_pr_args(aff_mask), cpu); in its_select_cpu()
1683 return -EINVAL; in its_set_affinity()
1685 prev_cpu = its_dev->event_map.col_map[id]; in its_set_affinity()
1698 target_col = &its_dev->its->collections[cpu]; in its_set_affinity()
1700 its_dev->event_map.col_map[id] = cpu; in its_set_affinity()
1710 return -EINVAL; in its_set_affinity()
1715 struct its_node *its = its_dev->its; in its_irq_get_msi_base() local
1717 return its->phys_base + GITS_TRANSLATER; in its_irq_get_msi_base()
1723 struct its_node *its; in its_irq_compose_msi_msg() local
1726 its = its_dev->its; in its_irq_compose_msi_msg()
1727 addr = its->get_msi_base(its_dev); in its_irq_compose_msi_msg()
1729 msg->address_lo = lower_32_bits(addr); in its_irq_compose_msi_msg()
1730 msg->address_hi = upper_32_bits(addr); in its_irq_compose_msi_msg()
1731 msg->data = its_get_event_id(d); in its_irq_compose_msi_msg()
1744 return -EINVAL; in its_irq_set_irqchip_state()
1780 if (!its_list_map || gic_rdists->has_rvpeid) in gic_requires_eager_mapping()
1786 static void its_map_vm(struct its_node *its, struct its_vm *vm) in its_map_vm() argument
1799 vm->vlpi_count[its->list_nr]++; in its_map_vm()
1801 if (vm->vlpi_count[its->list_nr] == 1) { in its_map_vm()
1804 for (i = 0; i < vm->nr_vpes; i++) { in its_map_vm()
1805 struct its_vpe *vpe = vm->vpes[i]; in its_map_vm()
1806 struct irq_data *d = irq_get_irq_data(vpe->irq); in its_map_vm()
1809 vpe->col_idx = cpumask_first(cpu_online_mask); in its_map_vm()
1810 its_send_vmapp(its, vpe, true); in its_map_vm()
1811 its_send_vinvall(its, vpe); in its_map_vm()
1812 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); in its_map_vm()
1819 static void its_unmap_vm(struct its_node *its, struct its_vm *vm) in its_unmap_vm() argument
1823 /* Not using the ITS list? Everything is always mapped. */ in its_unmap_vm()
1829 if (!--vm->vlpi_count[its->list_nr]) { in its_unmap_vm()
1832 for (i = 0; i < vm->nr_vpes; i++) in its_unmap_vm()
1833 its_send_vmapp(its, vm->vpes[i], false); in its_unmap_vm()
1845 if (!info->map) in its_vlpi_map()
1846 return -EINVAL; in its_vlpi_map()
1848 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_map()
1850 if (!its_dev->event_map.vm) { in its_vlpi_map()
1853 maps = kcalloc(its_dev->event_map.nr_lpis, sizeof(*maps), in its_vlpi_map()
1856 ret = -ENOMEM; in its_vlpi_map()
1860 its_dev->event_map.vm = info->map->vm; in its_vlpi_map()
1861 its_dev->event_map.vlpi_maps = maps; in its_vlpi_map()
1862 } else if (its_dev->event_map.vm != info->map->vm) { in its_vlpi_map()
1863 ret = -EINVAL; in its_vlpi_map()
1868 its_dev->event_map.vlpi_maps[event] = *info->map; in its_vlpi_map()
1874 /* Ensure all the VPEs are mapped on this ITS */ in its_vlpi_map()
1875 its_map_vm(its_dev->its, info->map->vm); in its_vlpi_map()
1884 lpi_write_config(d, 0xff, info->map->properties); in its_vlpi_map()
1893 its_dev->event_map.nr_vlpis++; in its_vlpi_map()
1897 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_map()
1907 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_get()
1911 if (!its_dev->event_map.vm || !map) { in its_vlpi_get()
1912 ret = -EINVAL; in its_vlpi_get()
1917 *info->map = *map; in its_vlpi_get()
1920 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_get()
1930 raw_spin_lock(&its_dev->event_map.vlpi_lock); in its_vlpi_unmap()
1932 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) { in its_vlpi_unmap()
1933 ret = -EINVAL; in its_vlpi_unmap()
1942 its_send_mapti(its_dev, d->hwirq, event); in its_vlpi_unmap()
1947 /* Potentially unmap the VM from this ITS */ in its_vlpi_unmap()
1948 its_unmap_vm(its_dev->its, its_dev->event_map.vm); in its_vlpi_unmap()
1954 if (!--its_dev->event_map.nr_vlpis) { in its_vlpi_unmap()
1955 its_dev->event_map.vm = NULL; in its_vlpi_unmap()
1956 kfree(its_dev->event_map.vlpi_maps); in its_vlpi_unmap()
1960 raw_spin_unlock(&its_dev->event_map.vlpi_lock); in its_vlpi_unmap()
1968 if (!its_dev->event_map.vm || !irqd_is_forwarded_to_vcpu(d)) in its_vlpi_prop_update()
1969 return -EINVAL; in its_vlpi_prop_update()
1971 if (info->cmd_type == PROP_UPDATE_AND_INV_VLPI) in its_vlpi_prop_update()
1972 lpi_update_config(d, 0xff, info->config); in its_vlpi_prop_update()
1974 lpi_write_config(d, 0xff, info->config); in its_vlpi_prop_update()
1975 its_vlpi_set_doorbell(d, !!(info->config & LPI_PROP_ENABLED)); in its_vlpi_prop_update()
1985 /* Need a v4 ITS */ in its_irq_set_vcpu_affinity()
1986 if (!is_v4(its_dev->its)) in its_irq_set_vcpu_affinity()
1987 return -EINVAL; in its_irq_set_vcpu_affinity()
1993 switch (info->cmd_type) { in its_irq_set_vcpu_affinity()
2005 return -EINVAL; in its_irq_set_vcpu_affinity()
2010 .name = "ITS",
2054 range->base_id = base; in mk_lpi_range()
2055 range->span = span; in mk_lpi_range()
2064 int err = -ENOSPC; in alloc_lpi_range()
2069 if (range->span >= nr_lpis) { in alloc_lpi_range()
2070 *base = range->base_id; in alloc_lpi_range()
2071 range->base_id += nr_lpis; in alloc_lpi_range()
2072 range->span -= nr_lpis; in alloc_lpi_range()
2074 if (range->span == 0) { in alloc_lpi_range()
2075 list_del(&range->entry); in alloc_lpi_range()
2086 pr_debug("ITS: alloc %u:%u\n", *base, nr_lpis); in alloc_lpi_range()
2092 if (&a->entry == &lpi_range_list || &b->entry == &lpi_range_list) in merge_lpi_ranges()
2094 if (a->base_id + a->span != b->base_id) in merge_lpi_ranges()
2096 b->base_id = a->base_id; in merge_lpi_ranges()
2097 b->span += a->span; in merge_lpi_ranges()
2098 list_del(&a->entry); in merge_lpi_ranges()
2108 return -ENOMEM; in free_lpi_range()
2113 if (old->base_id < base) in free_lpi_range()
2117 * old is the last element with ->base_id smaller than base, in free_lpi_range()
2119 * ->base_id smaller than base, &old->entry ends up pointing in free_lpi_range()
2123 list_add(&new->entry, &old->entry); in free_lpi_range()
2137 u32 lpis = (1UL << id_bits) - 8192; in its_lpi_init()
2141 numlpis = 1UL << GICD_TYPER_NUM_LPIS(gic_rdists->gicd_typer); in its_lpi_init()
2145 pr_info("ITS: Using hypervisor restricted LPI range [%u]\n", in its_lpi_init()
2154 pr_debug("ITS: Allocator initialized for %u LPIs\n", lpis); in its_lpi_init()
2172 err = -ENOSPC; in its_lpi_alloc()
2198 /* Priority 0xa0, Group-1, disabled */ in gic_reset_prop_table()
2237 addr_end = addr + size - 1; in gic_check_reserved_range()
2261 if (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) { in its_setup_lpi_prop_table()
2267 gic_rdists->prop_table_pa = val & GENMASK_ULL(51, 12); in its_setup_lpi_prop_table()
2268 gic_rdists->prop_table_va = memremap(gic_rdists->prop_table_pa, in its_setup_lpi_prop_table()
2271 gic_reset_prop_table(gic_rdists->prop_table_va); in its_setup_lpi_prop_table()
2276 GICD_TYPER_ID_BITS(gic_rdists->gicd_typer), in its_setup_lpi_prop_table()
2281 return -ENOMEM; in its_setup_lpi_prop_table()
2284 gic_rdists->prop_table_pa = page_to_phys(page); in its_setup_lpi_prop_table()
2285 gic_rdists->prop_table_va = page_address(page); in its_setup_lpi_prop_table()
2286 WARN_ON(gic_reserve_range(gic_rdists->prop_table_pa, in its_setup_lpi_prop_table()
2291 &gic_rdists->prop_table_pa); in its_setup_lpi_prop_table()
2306 static u64 its_read_baser(struct its_node *its, struct its_baser *baser) in its_read_baser() argument
2308 u32 idx = baser - its->tables; in its_read_baser()
2310 return gits_read_baser(its->base + GITS_BASER + (idx << 3)); in its_read_baser()
2313 static void its_write_baser(struct its_node *its, struct its_baser *baser, in its_write_baser() argument
2316 u32 idx = baser - its->tables; in its_write_baser()
2318 gits_write_baser(val, its->base + GITS_BASER + (idx << 3)); in its_write_baser()
2319 baser->val = its_read_baser(its, baser); in its_write_baser()
2322 static int its_setup_baser(struct its_node *its, struct its_baser *baser, in its_setup_baser() argument
2325 u64 val = its_read_baser(its, baser); in its_setup_baser()
2333 psz = baser->psz; in its_setup_baser()
2336 pr_warn("ITS@%pa: %s too large, reduce ITS pages %u->%u\n", in its_setup_baser()
2337 &its->phys_base, its_base_type_string[type], in its_setup_baser()
2343 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, order); in its_setup_baser()
2345 return -ENOMEM; in its_setup_baser()
2355 pr_err("ITS: no 52bit PA support when psz=%d\n", psz); in its_setup_baser()
2357 return -ENXIO; in its_setup_baser()
2367 ((esz - 1) << GITS_BASER_ENTRY_SIZE_SHIFT) | in its_setup_baser()
2368 ((alloc_pages - 1) << GITS_BASER_PAGES_SHIFT) | in its_setup_baser()
2390 its_write_baser(its, baser, val); in its_setup_baser()
2391 tmp = baser->val; in its_setup_baser()
2399 * non-cacheable as well. in its_setup_baser()
2409 pr_err("ITS@%pa: %s doesn't stick: %llx %llx\n", in its_setup_baser()
2410 &its->phys_base, its_base_type_string[type], in its_setup_baser()
2413 return -ENXIO; in its_setup_baser()
2416 baser->order = order; in its_setup_baser()
2417 baser->base = base; in its_setup_baser()
2418 baser->psz = psz; in its_setup_baser()
2421 pr_info("ITS@%pa: allocated %d %s @%lx (%s, esz %d, psz %dK, shr %d)\n", in its_setup_baser()
2422 &its->phys_base, (int)(PAGE_ORDER_TO_SIZE(order) / (int)tmp), in its_setup_baser()
2431 static bool its_parse_indirect_baser(struct its_node *its, in its_parse_indirect_baser() argument
2435 u64 tmp = its_read_baser(its, baser); in its_parse_indirect_baser()
2440 u32 psz = baser->psz; in its_parse_indirect_baser()
2446 * Find out whether hw supports a single or two-level table by in its_parse_indirect_baser()
2449 its_write_baser(its, baser, val | GITS_BASER_INDIRECT); in its_parse_indirect_baser()
2450 indirect = !!(baser->val & GITS_BASER_INDIRECT); in its_parse_indirect_baser()
2454 * The size of the lvl2 table is equal to ITS page size in its_parse_indirect_baser()
2457 * which is reported by ITS hardware times lvl1 table in its_parse_indirect_baser()
2460 ids -= ilog2(psz / (int)esz); in its_parse_indirect_baser()
2467 * range of device IDs that the ITS can grok... The ID in its_parse_indirect_baser()
2469 * massive waste of memory if two-level device table in its_parse_indirect_baser()
2476 pr_warn("ITS@%pa: %s Table too large, reduce ids %llu->%u\n", in its_parse_indirect_baser()
2477 &its->phys_base, its_base_type_string[type], in its_parse_indirect_baser()
2478 device_ids(its), ids); in its_parse_indirect_baser()
2496 static u32 compute_its_aff(struct its_node *its) in compute_its_aff() argument
2502 * Reencode the ITS SVPET and MPIDR as a GICR_TYPER, and compute in compute_its_aff()
2506 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); in compute_its_aff()
2508 val |= FIELD_PREP(GICR_TYPER_AFFINITY, its->mpidr); in compute_its_aff()
2514 struct its_node *its; in find_sibling_its() local
2517 if (!FIELD_GET(GITS_TYPER_SVPET, cur_its->typer)) in find_sibling_its()
2522 list_for_each_entry(its, &its_nodes, entry) { in find_sibling_its()
2525 if (!is_v4_1(its) || its == cur_its) in find_sibling_its()
2528 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) in find_sibling_its()
2531 if (aff != compute_its_aff(its)) in find_sibling_its()
2535 baser = its->tables[2].val; in find_sibling_its()
2539 return its; in find_sibling_its()
2545 static void its_free_tables(struct its_node *its) in its_free_tables() argument
2550 if (its->tables[i].base) { in its_free_tables()
2551 free_pages((unsigned long)its->tables[i].base, in its_free_tables()
2552 its->tables[i].order); in its_free_tables()
2553 its->tables[i].base = NULL; in its_free_tables()
2558 static int its_probe_baser_psz(struct its_node *its, struct its_baser *baser) in its_probe_baser_psz() argument
2565 val = its_read_baser(its, baser); in its_probe_baser_psz()
2584 its_write_baser(its, baser, val); in its_probe_baser_psz()
2586 if (FIELD_GET(GITS_BASER_PAGE_SIZE_MASK, baser->val) == gpsz) in its_probe_baser_psz()
2598 return -1; in its_probe_baser_psz()
2602 baser->psz = psz; in its_probe_baser_psz()
2606 static int its_alloc_tables(struct its_node *its) in its_alloc_tables() argument
2612 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_22375) in its_alloc_tables()
2616 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) { in its_alloc_tables()
2622 struct its_baser *baser = its->tables + i; in its_alloc_tables()
2623 u64 val = its_read_baser(its, baser); in its_alloc_tables()
2631 if (its_probe_baser_psz(its, baser)) { in its_alloc_tables()
2632 its_free_tables(its); in its_alloc_tables()
2633 return -ENXIO; in its_alloc_tables()
2636 order = get_order(baser->psz); in its_alloc_tables()
2640 indirect = its_parse_indirect_baser(its, baser, &order, in its_alloc_tables()
2641 device_ids(its)); in its_alloc_tables()
2645 if (is_v4_1(its)) { in its_alloc_tables()
2649 if ((sibling = find_sibling_its(its))) { in its_alloc_tables()
2650 *baser = sibling->tables[2]; in its_alloc_tables()
2651 its_write_baser(its, baser, baser->val); in its_alloc_tables()
2656 indirect = its_parse_indirect_baser(its, baser, &order, in its_alloc_tables()
2661 err = its_setup_baser(its, baser, cache, shr, order, indirect); in its_alloc_tables()
2663 its_free_tables(its); in its_alloc_tables()
2668 cache = baser->val & GITS_BASER_CACHEABILITY_MASK; in its_alloc_tables()
2669 shr = baser->val & GITS_BASER_SHAREABILITY_MASK; in its_alloc_tables()
2677 struct its_node *its; in inherit_vpe_l1_table_from_its() local
2684 list_for_each_entry(its, &its_nodes, entry) { in inherit_vpe_l1_table_from_its()
2687 if (!is_v4_1(its)) in inherit_vpe_l1_table_from_its()
2690 if (!FIELD_GET(GITS_TYPER_SVPET, its->typer)) in inherit_vpe_l1_table_from_its()
2693 if (aff != compute_its_aff(its)) in inherit_vpe_l1_table_from_its()
2697 baser = its->tables[2].val; in inherit_vpe_l1_table_from_its()
2702 gic_data_rdist()->vpe_l1_base = its->tables[2].base; in inherit_vpe_l1_table_from_its()
2724 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, GITS_BASER_NR_PAGES(baser) - 1); in inherit_vpe_l1_table_from_its()
2742 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; in inherit_vpe_l1_table_from_rd()
2754 * ours wrt CommonLPIAff. Let's use its own VPROPBASER. in inherit_vpe_l1_table_from_rd()
2760 gic_data_rdist()->vpe_l1_base = gic_data_rdist_cpu(cpu)->vpe_l1_base; in inherit_vpe_l1_table_from_rd()
2761 *mask = gic_data_rdist_cpu(cpu)->vpe_table_mask; in inherit_vpe_l1_table_from_rd()
2771 void __iomem *base = gic_data_rdist_cpu(cpu)->rd_base; in allocate_vpe_l2_table()
2777 if (!gic_rdists->has_rvpeid) in allocate_vpe_l2_table()
2780 /* Skip non-present CPUs */ in allocate_vpe_l2_table()
2814 table = gic_data_rdist_cpu(cpu)->vpe_l1_base; in allocate_vpe_l2_table()
2847 if (!gic_rdists->has_rvpeid) in allocate_vpe_l1_table()
2866 val = inherit_vpe_l1_table_from_rd(&gic_data_rdist()->vpe_table_mask); in allocate_vpe_l1_table()
2870 gic_data_rdist()->vpe_table_mask = kzalloc(sizeof(cpumask_t), GFP_ATOMIC); in allocate_vpe_l1_table()
2871 if (!gic_data_rdist()->vpe_table_mask) in allocate_vpe_l1_table()
2872 return -ENOMEM; in allocate_vpe_l1_table()
2930 val |= FIELD_PREP(GICR_VPROPBASER_4_1_SIZE, npg - 1); in allocate_vpe_l1_table()
2939 return -ENOMEM; in allocate_vpe_l1_table()
2941 gic_data_rdist()->vpe_l1_base = page_address(page); in allocate_vpe_l1_table()
2955 cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask); in allocate_vpe_l1_table()
2959 cpumask_pr_args(gic_data_rdist()->vpe_table_mask)); in allocate_vpe_l1_table()
2964 static int its_alloc_collections(struct its_node *its) in its_alloc_collections() argument
2968 its->collections = kcalloc(nr_cpu_ids, sizeof(*its->collections), in its_alloc_collections()
2970 if (!its->collections) in its_alloc_collections()
2971 return -ENOMEM; in its_alloc_collections()
2974 its->collections[i].target_address = ~0ULL; in its_alloc_collections()
2988 /* Make sure the GIC will observe the zero-ed page */ in its_allocate_pending_table()
3022 * flag the RD tables as pre-allocated if the stars do align. in allocate_lpi_tables()
3026 gic_rdists->flags |= (RDIST_FLAGS_RD_TABLES_PREALLOCATED | in allocate_lpi_tables()
3046 return -ENOMEM; in allocate_lpi_tables()
3049 gic_data_rdist_cpu(cpu)->pend_page = pend_page; in allocate_lpi_tables()
3065 count--; in read_vpend_dirty_clear()
3072 pr_err_ratelimited("ITS virtual pending table not cleaning\n"); in read_vpend_dirty_clear()
3102 if (gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) in its_cpu_init_lpis()
3106 if ((gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED) && in its_cpu_init_lpis()
3114 if (WARN_ON(gic_rdists->prop_table_pa != paddr)) in its_cpu_init_lpis()
3121 gic_data_rdist()->flags |= RD_LOCAL_PENDTABLE_PREALLOCATED; in its_cpu_init_lpis()
3126 pend_page = gic_data_rdist()->pend_page; in its_cpu_init_lpis()
3130 val = (gic_rdists->prop_table_pa | in its_cpu_init_lpis()
3133 ((LPI_NRBITS - 1) & GICR_PROPBASER_IDBITS_MASK)); in its_cpu_init_lpis()
3144 * The HW reports non-shareable, we must in its_cpu_init_lpis()
3154 gic_rdists->flags |= RDIST_FLAGS_PROPBASE_NEEDS_FLUSHING; in its_cpu_init_lpis()
3170 * The HW reports non-shareable, we must remove the in its_cpu_init_lpis()
3185 if (gic_rdists->has_vlpis && !gic_rdists->has_rvpeid) { in its_cpu_init_lpis()
3195 val = (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; in its_cpu_init_lpis()
3214 gic_rdists->has_rvpeid = false; in its_cpu_init_lpis()
3215 gic_rdists->has_vlpis = false; in its_cpu_init_lpis()
3220 gic_data_rdist()->flags |= RD_LOCAL_LPI_ENABLED; in its_cpu_init_lpis()
3223 gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED ? in its_cpu_init_lpis()
3228 static void its_cpu_init_collection(struct its_node *its) in its_cpu_init_collection() argument
3233 /* avoid cross node collections and its mapping */ in its_cpu_init_collection()
3234 if (its->flags & ITS_FLAGS_WORKAROUND_CAVIUM_23144) { in its_cpu_init_collection()
3238 if (its->numa_node != NUMA_NO_NODE && in its_cpu_init_collection()
3239 its->numa_node != of_node_to_nid(cpu_node)) in its_cpu_init_collection()
3244 * We now have to bind each collection to its target in its_cpu_init_collection()
3247 if (gic_read_typer(its->base + GITS_TYPER) & GITS_TYPER_PTA) { in its_cpu_init_collection()
3249 * This ITS wants the physical address of the in its_cpu_init_collection()
3252 target = gic_data_rdist()->phys_base; in its_cpu_init_collection()
3254 /* This ITS wants a linear CPU number. */ in its_cpu_init_collection()
3260 its->collections[cpu].target_address = target; in its_cpu_init_collection()
3261 its->collections[cpu].col_id = cpu; in its_cpu_init_collection()
3263 its_send_mapc(its, &its->collections[cpu], 1); in its_cpu_init_collection()
3264 its_send_invall(its, &its->collections[cpu]); in its_cpu_init_collection()
3269 struct its_node *its; in its_cpu_init_collections() local
3273 list_for_each_entry(its, &its_nodes, entry) in its_cpu_init_collections()
3274 its_cpu_init_collection(its); in its_cpu_init_collections()
3279 static struct its_device *its_find_device(struct its_node *its, u32 dev_id) in its_find_device() argument
3284 raw_spin_lock_irqsave(&its->lock, flags); in its_find_device()
3286 list_for_each_entry(tmp, &its->its_device_list, entry) { in its_find_device()
3287 if (tmp->device_id == dev_id) { in its_find_device()
3293 raw_spin_unlock_irqrestore(&its->lock, flags); in its_find_device()
3298 static struct its_baser *its_get_baser(struct its_node *its, u32 type) in its_get_baser() argument
3303 if (GITS_BASER_TYPE(its->tables[i].val) == type) in its_get_baser()
3304 return &its->tables[i]; in its_get_baser()
3310 static bool its_alloc_table_entry(struct its_node *its, in its_alloc_table_entry() argument
3318 esz = GITS_BASER_ENTRY_SIZE(baser->val); in its_alloc_table_entry()
3319 if (!(baser->val & GITS_BASER_INDIRECT)) in its_alloc_table_entry()
3320 return (id < (PAGE_ORDER_TO_SIZE(baser->order) / esz)); in its_alloc_table_entry()
3323 idx = id >> ilog2(baser->psz / esz); in its_alloc_table_entry()
3324 if (idx >= (PAGE_ORDER_TO_SIZE(baser->order) / GITS_LVL1_ENTRY_SIZE)) in its_alloc_table_entry()
3327 table = baser->base; in its_alloc_table_entry()
3331 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, in its_alloc_table_entry()
3332 get_order(baser->psz)); in its_alloc_table_entry()
3337 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) in its_alloc_table_entry()
3338 gic_flush_dcache_to_poc(page_address(page), baser->psz); in its_alloc_table_entry()
3343 if (!(baser->val & GITS_BASER_SHAREABILITY_MASK)) in its_alloc_table_entry()
3346 /* Ensure updated table contents are visible to ITS hardware */ in its_alloc_table_entry()
3353 static bool its_alloc_device_table(struct its_node *its, u32 dev_id) in its_alloc_device_table() argument
3357 baser = its_get_baser(its, GITS_BASER_TYPE_DEVICE); in its_alloc_device_table()
3359 /* Don't allow device id that exceeds ITS hardware limit */ in its_alloc_device_table()
3361 return (ilog2(dev_id) < device_ids(its)); in its_alloc_device_table()
3363 return its_alloc_table_entry(its, baser, dev_id); in its_alloc_device_table()
3368 struct its_node *its; in its_alloc_vpe_table() local
3378 list_for_each_entry(its, &its_nodes, entry) { in its_alloc_vpe_table()
3381 if (!is_v4(its)) in its_alloc_vpe_table()
3384 baser = its_get_baser(its, GITS_BASER_TYPE_VCPU); in its_alloc_vpe_table()
3388 if (!its_alloc_table_entry(its, baser, vpe_id)) in its_alloc_vpe_table()
3393 if (!gic_rdists->has_rvpeid) in its_alloc_vpe_table()
3408 static struct its_device *its_create_device(struct its_node *its, u32 dev_id, in its_create_device() argument
3421 if (!its_alloc_device_table(its, dev_id)) in its_create_device()
3433 sz = nr_ites * (FIELD_GET(GITS_TYPER_ITT_ENTRY_SIZE, its->typer) + 1); in its_create_device()
3434 sz = max(sz, ITS_ITT_ALIGN) + ITS_ITT_ALIGN - 1; in its_create_device()
3435 itt = kzalloc_node(sz, GFP_KERNEL, its->numa_node); in its_create_device()
3457 dev->its = its; in its_create_device()
3458 dev->itt = itt; in its_create_device()
3459 dev->nr_ites = nr_ites; in its_create_device()
3460 dev->event_map.lpi_map = lpi_map; in its_create_device()
3461 dev->event_map.col_map = col_map; in its_create_device()
3462 dev->event_map.lpi_base = lpi_base; in its_create_device()
3463 dev->event_map.nr_lpis = nr_lpis; in its_create_device()
3464 raw_spin_lock_init(&dev->event_map.vlpi_lock); in its_create_device()
3465 dev->device_id = dev_id; in its_create_device()
3466 INIT_LIST_HEAD(&dev->entry); in its_create_device()
3468 raw_spin_lock_irqsave(&its->lock, flags); in its_create_device()
3469 list_add(&dev->entry, &its->its_device_list); in its_create_device()
3470 raw_spin_unlock_irqrestore(&its->lock, flags); in its_create_device()
3472 /* Map device to its ITT */ in its_create_device()
3482 raw_spin_lock_irqsave(&its_dev->its->lock, flags); in its_free_device()
3483 list_del(&its_dev->entry); in its_free_device()
3484 raw_spin_unlock_irqrestore(&its_dev->its->lock, flags); in its_free_device()
3485 kfree(its_dev->event_map.col_map); in its_free_device()
3486 kfree(its_dev->itt); in its_free_device()
3495 idx = bitmap_find_free_region(dev->event_map.lpi_map, in its_alloc_device_irq()
3496 dev->event_map.nr_lpis, in its_alloc_device_irq()
3499 return -ENOSPC; in its_alloc_device_irq()
3501 *hwirq = dev->event_map.lpi_base + idx; in its_alloc_device_irq()
3509 struct its_node *its; in its_msi_prepare() local
3519 * are built on top of the ITS. in its_msi_prepare()
3521 dev_id = info->scratchpad[0].ul; in its_msi_prepare()
3524 its = msi_info->data; in its_msi_prepare()
3526 if (!gic_rdists->has_direct_lpi && in its_msi_prepare()
3528 vpe_proxy.dev->its == its && in its_msi_prepare()
3529 dev_id == vpe_proxy.dev->device_id) { in its_msi_prepare()
3533 return -EINVAL; in its_msi_prepare()
3536 mutex_lock(&its->dev_alloc_lock); in its_msi_prepare()
3537 its_dev = its_find_device(its, dev_id); in its_msi_prepare()
3544 its_dev->shared = true; in its_msi_prepare()
3549 its_dev = its_create_device(its, dev_id, nvec, true); in its_msi_prepare()
3551 err = -ENOMEM; in its_msi_prepare()
3555 if (info->flags & MSI_ALLOC_FLAGS_PROXY_DEVICE) in its_msi_prepare()
3556 its_dev->shared = true; in its_msi_prepare()
3560 mutex_unlock(&its->dev_alloc_lock); in its_msi_prepare()
3561 info->scratchpad[0].ptr = its_dev; in its_msi_prepare()
3575 if (irq_domain_get_of_node(domain->parent)) { in its_irq_gic_domain_alloc()
3576 fwspec.fwnode = domain->parent->fwnode; in its_irq_gic_domain_alloc()
3581 } else if (is_fwnode_irqchip(domain->parent->fwnode)) { in its_irq_gic_domain_alloc()
3582 fwspec.fwnode = domain->parent->fwnode; in its_irq_gic_domain_alloc()
3587 return -EINVAL; in its_irq_gic_domain_alloc()
3597 struct its_device *its_dev = info->scratchpad[0].ptr; in its_irq_domain_alloc()
3598 struct its_node *its = its_dev->its; in its_irq_domain_alloc() local
3608 err = iommu_dma_prepare_msi(info->desc, its->get_msi_base(its_dev)); in its_irq_domain_alloc()
3624 (int)(hwirq + i - its_dev->event_map.lpi_base), in its_irq_domain_alloc()
3640 return -EINVAL; in its_irq_domain_activate()
3643 its_dev->event_map.col_map[event] = cpu; in its_irq_domain_activate()
3647 its_send_mapti(its_dev, d->hwirq, event); in its_irq_domain_activate()
3657 its_dec_lpi_count(d, its_dev->event_map.col_map[event]); in its_irq_domain_deactivate()
3667 struct its_node *its = its_dev->its; in its_irq_domain_free() local
3670 bitmap_release_region(its_dev->event_map.lpi_map, in its_irq_domain_free()
3681 mutex_lock(&its->dev_alloc_lock); in its_irq_domain_free()
3687 if (!its_dev->shared && in its_irq_domain_free()
3688 bitmap_empty(its_dev->event_map.lpi_map, in its_irq_domain_free()
3689 its_dev->event_map.nr_lpis)) { in its_irq_domain_free()
3690 its_lpi_free(its_dev->event_map.lpi_map, in its_irq_domain_free()
3691 its_dev->event_map.lpi_base, in its_irq_domain_free()
3692 its_dev->event_map.nr_lpis); in its_irq_domain_free()
3699 mutex_unlock(&its->dev_alloc_lock); in its_irq_domain_free()
3733 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_unmap_locked()
3737 if (vpe->vpe_proxy_event == -1) in its_vpe_db_proxy_unmap_locked()
3740 its_send_discard(vpe_proxy.dev, vpe->vpe_proxy_event); in its_vpe_db_proxy_unmap_locked()
3741 vpe_proxy.vpes[vpe->vpe_proxy_event] = NULL; in its_vpe_db_proxy_unmap_locked()
3751 vpe_proxy.next_victim = vpe->vpe_proxy_event; in its_vpe_db_proxy_unmap_locked()
3753 vpe->vpe_proxy_event = -1; in its_vpe_db_proxy_unmap_locked()
3759 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_unmap()
3762 if (!gic_rdists->has_direct_lpi) { in its_vpe_db_proxy_unmap()
3774 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_map_locked()
3778 if (vpe->vpe_proxy_event != -1) in its_vpe_db_proxy_map_locked()
3787 vpe->vpe_proxy_event = vpe_proxy.next_victim; in its_vpe_db_proxy_map_locked()
3788 vpe_proxy.next_victim = (vpe_proxy.next_victim + 1) % vpe_proxy.dev->nr_ites; in its_vpe_db_proxy_map_locked()
3790 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = vpe->col_idx; in its_vpe_db_proxy_map_locked()
3791 its_send_mapti(vpe_proxy.dev, vpe->vpe_db_lpi, vpe->vpe_proxy_event); in its_vpe_db_proxy_map_locked()
3800 if (gic_rdists->has_rvpeid) in its_vpe_db_proxy_move()
3803 if (gic_rdists->has_direct_lpi) { in its_vpe_db_proxy_move()
3806 rdbase = per_cpu_ptr(gic_rdists->rdist, from)->rd_base; in its_vpe_db_proxy_move()
3807 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); in its_vpe_db_proxy_move()
3817 target_col = &vpe_proxy.dev->its->collections[to]; in its_vpe_db_proxy_move()
3818 its_send_movi(vpe_proxy.dev, target_col, vpe->vpe_proxy_event); in its_vpe_db_proxy_move()
3819 vpe_proxy.dev->event_map.col_map[vpe->vpe_proxy_event] = to; in its_vpe_db_proxy_move()
3837 * interrupt to its new location. in its_vpe_set_affinity()
3842 * protect us, and that we must ensure nobody samples vpe->col_idx in its_vpe_set_affinity()
3844 * taken on any vLPI handling path that evaluates vpe->col_idx. in its_vpe_set_affinity()
3847 table_mask = gic_data_rdist_cpu(from)->vpe_table_mask; in its_vpe_set_affinity()
3850 * If we are offered another CPU in the same GICv4.1 ITS in its_vpe_set_affinity()
3861 vpe->col_idx = cpu; in its_vpe_set_affinity()
3878 if (!gic_rdists->has_vpend_valid_dirty) in its_wait_vpt_parse_complete()
3893 val = virt_to_phys(page_address(vpe->its_vm->vprop_page)) & in its_vpe_schedule()
3895 val |= (LPI_NRBITS - 1) & GICR_VPROPBASER_IDBITS_MASK; in its_vpe_schedule()
3902 val = virt_to_phys(page_address(vpe->vpt_page)) & in its_vpe_schedule()
3911 * easily. So in the end, vpe->pending_last is only an in its_vpe_schedule()
3914 * would be able to read its coarse map pretty quickly anyway, in its_vpe_schedule()
3918 val |= vpe->idai ? GICR_VPENDBASER_IDAI : 0; in its_vpe_schedule()
3930 vpe->idai = !!(val & GICR_VPENDBASER_IDAI); in its_vpe_deschedule()
3931 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); in its_vpe_deschedule()
3936 struct its_node *its; in its_vpe_invall() local
3938 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_invall()
3939 if (!is_v4(its)) in its_vpe_invall()
3942 if (its_list_map && !vpe->its_vm->vlpi_count[its->list_nr]) in its_vpe_invall()
3946 * Sending a VINVALL to a single ITS is enough, as all in its_vpe_invall()
3949 its_send_vinvall(its, vpe); in its_vpe_invall()
3959 switch (info->cmd_type) { in its_vpe_set_vcpu_affinity()
3977 return -EINVAL; in its_vpe_set_vcpu_affinity()
3989 cmd(vpe_proxy.dev, vpe->vpe_proxy_event); in its_vpe_send_cmd()
3998 if (gic_rdists->has_direct_lpi) in its_vpe_send_inv()
3999 __direct_lpi_inv(d, d->parent_data->hwirq); in its_vpe_send_inv()
4012 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); in its_vpe_mask_irq()
4019 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); in its_vpe_unmask_irq()
4030 return -EINVAL; in its_vpe_set_irqchip_state()
4032 if (gic_rdists->has_direct_lpi) { in its_vpe_set_irqchip_state()
4035 rdbase = per_cpu_ptr(gic_rdists->rdist, vpe->col_idx)->rd_base; in its_vpe_set_irqchip_state()
4037 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_SETLPIR); in its_vpe_set_irqchip_state()
4039 gic_write_lpir(vpe->vpe_db_lpi, rdbase + GICR_CLRLPIR); in its_vpe_set_irqchip_state()
4058 .name = "GICv4-vpe",
4070 static struct its_node *its = NULL; in find_4_1_its() local
4072 if (!its) { in find_4_1_its()
4073 list_for_each_entry(its, &its_nodes, entry) { in find_4_1_its()
4074 if (is_v4_1(its)) in find_4_1_its()
4075 return its; in find_4_1_its()
4079 its = NULL; in find_4_1_its()
4082 return its; in find_4_1_its()
4088 struct its_node *its; in its_vpe_4_1_send_inv() local
4093 * it to the first valid ITS, and let the HW do its magic. in its_vpe_4_1_send_inv()
4095 its = find_4_1_its(); in its_vpe_4_1_send_inv()
4096 if (its) in its_vpe_4_1_send_inv()
4097 its_send_invdb(its, vpe); in its_vpe_4_1_send_inv()
4102 lpi_write_config(d->parent_data, LPI_PROP_ENABLED, 0); in its_vpe_4_1_mask_irq()
4108 lpi_write_config(d->parent_data, 0, LPI_PROP_ENABLED); in its_vpe_4_1_unmask_irq()
4120 val |= info->g0en ? GICR_VPENDBASER_4_1_VGRP0EN : 0; in its_vpe_4_1_schedule()
4121 val |= info->g1en ? GICR_VPENDBASER_4_1_VGRP1EN : 0; in its_vpe_4_1_schedule()
4122 val |= FIELD_PREP(GICR_VPENDBASER_4_1_VPEID, vpe->vpe_id); in its_vpe_4_1_schedule()
4133 if (info->req_db) { in its_vpe_4_1_deschedule()
4137 * vPE is going to block: make the vPE non-resident with in its_vpe_4_1_deschedule()
4139 * we read-back PendingLast clear, then a doorbell will be in its_vpe_4_1_deschedule()
4146 raw_spin_lock_irqsave(&vpe->vpe_lock, flags); in its_vpe_4_1_deschedule()
4150 vpe->pending_last = !!(val & GICR_VPENDBASER_PendingLast); in its_vpe_4_1_deschedule()
4151 raw_spin_unlock_irqrestore(&vpe->vpe_lock, flags); in its_vpe_4_1_deschedule()
4154 * We're not blocking, so just make the vPE non-resident in its_vpe_4_1_deschedule()
4160 vpe->pending_last = true; in its_vpe_4_1_deschedule()
4172 val |= FIELD_PREP(GICR_INVALLR_VPEID, vpe->vpe_id); in its_vpe_4_1_invall()
4176 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_vpe_4_1_invall()
4177 rdbase = per_cpu_ptr(gic_rdists->rdist, cpu)->rd_base; in its_vpe_4_1_invall()
4181 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_vpe_4_1_invall()
4190 switch (info->cmd_type) { in its_vpe_4_1_set_vcpu_affinity()
4208 return -EINVAL; in its_vpe_4_1_set_vcpu_affinity()
4213 .name = "GICv4.1-vpe",
4227 desc.its_vsgi_cmd.sgi = d->hwirq; in its_configure_sgi()
4228 desc.its_vsgi_cmd.priority = vpe->sgi_config[d->hwirq].priority; in its_configure_sgi()
4229 desc.its_vsgi_cmd.enable = vpe->sgi_config[d->hwirq].enabled; in its_configure_sgi()
4230 desc.its_vsgi_cmd.group = vpe->sgi_config[d->hwirq].group; in its_configure_sgi()
4234 * GICv4.1 allows us to send VSGI commands to any ITS as long as the in its_configure_sgi()
4236 * activation time, we're pretty sure the first GICv4.1 ITS will do. in its_configure_sgi()
4245 vpe->sgi_config[d->hwirq].enabled = false; in its_sgi_mask_irq()
4253 vpe->sgi_config[d->hwirq].enabled = true; in its_sgi_unmask_irq()
4275 return -EINVAL; in its_sgi_set_irqchip_state()
4279 struct its_node *its = find_4_1_its(); in its_sgi_set_irqchip_state() local
4282 val = FIELD_PREP(GITS_SGIR_VPEID, vpe->vpe_id); in its_sgi_set_irqchip_state()
4283 val |= FIELD_PREP(GITS_SGIR_VINTID, d->hwirq); in its_sgi_set_irqchip_state()
4284 writeq_relaxed(val, its->sgir_base + GITS_SGIR - SZ_128K); in its_sgi_set_irqchip_state()
4303 return -EINVAL; in its_sgi_get_irqchip_state()
4308 * - Concurrent vPE affinity change: we must make sure it cannot in its_sgi_get_irqchip_state()
4312 * - Concurrent VSGIPENDR access: As it involves accessing two in its_sgi_get_irqchip_state()
4316 raw_spin_lock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_sgi_get_irqchip_state()
4317 base = gic_data_rdist_cpu(cpu)->rd_base + SZ_128K; in its_sgi_get_irqchip_state()
4318 writel_relaxed(vpe->vpe_id, base + GICR_VSGIR); in its_sgi_get_irqchip_state()
4324 count--; in its_sgi_get_irqchip_state()
4334 raw_spin_unlock(&gic_data_rdist_cpu(cpu)->rd_lock); in its_sgi_get_irqchip_state()
4338 return -ENXIO; in its_sgi_get_irqchip_state()
4340 *val = !!(status & (1 << d->hwirq)); in its_sgi_get_irqchip_state()
4350 switch (info->cmd_type) { in its_sgi_set_vcpu_affinity()
4352 vpe->sgi_config[d->hwirq].priority = info->priority; in its_sgi_set_vcpu_affinity()
4353 vpe->sgi_config[d->hwirq].group = info->group; in its_sgi_set_vcpu_affinity()
4358 return -EINVAL; in its_sgi_set_vcpu_affinity()
4363 .name = "GICv4.1-sgi",
4383 vpe->sgi_config[i].priority = 0; in its_sgi_irq_domain_alloc()
4384 vpe->sgi_config[i].enabled = false; in its_sgi_irq_domain_alloc()
4385 vpe->sgi_config[i].group = false; in its_sgi_irq_domain_alloc()
4418 * - To change the configuration, CLEAR must be set to false, in its_sgi_irq_domain_deactivate()
4420 * - To clear the pending bit, CLEAR must be set to true, leaving in its_sgi_irq_domain_deactivate()
4425 vpe->sgi_config[d->hwirq].enabled = false; in its_sgi_irq_domain_deactivate()
4461 return -ENOMEM; in its_vpe_init()
4467 return -ENOMEM; in its_vpe_init()
4470 raw_spin_lock_init(&vpe->vpe_lock); in its_vpe_init()
4471 vpe->vpe_id = vpe_id; in its_vpe_init()
4472 vpe->vpt_page = vpt_page; in its_vpe_init()
4473 if (gic_rdists->has_rvpeid) in its_vpe_init()
4474 atomic_set(&vpe->vmapp_count, 0); in its_vpe_init()
4476 vpe->vpe_proxy_event = -1; in its_vpe_init()
4484 its_vpe_id_free(vpe->vpe_id); in its_vpe_teardown()
4485 its_free_pending_table(vpe->vpt_page); in its_vpe_teardown()
4492 struct its_vm *vm = domain->host_data; in its_vpe_irq_domain_free()
4502 BUG_ON(vm != vpe->its_vm); in its_vpe_irq_domain_free()
4504 clear_bit(data->hwirq, vm->db_bitmap); in its_vpe_irq_domain_free()
4509 if (bitmap_empty(vm->db_bitmap, vm->nr_db_lpis)) { in its_vpe_irq_domain_free()
4510 its_lpi_free(vm->db_bitmap, vm->db_lpi_base, vm->nr_db_lpis); in its_vpe_irq_domain_free()
4511 its_free_prop_table(vm->vprop_page); in its_vpe_irq_domain_free()
4528 return -ENOMEM; in its_vpe_irq_domain_alloc()
4532 return -ENOMEM; in its_vpe_irq_domain_alloc()
4538 return -ENOMEM; in its_vpe_irq_domain_alloc()
4541 vm->db_bitmap = bitmap; in its_vpe_irq_domain_alloc()
4542 vm->db_lpi_base = base; in its_vpe_irq_domain_alloc()
4543 vm->nr_db_lpis = nr_ids; in its_vpe_irq_domain_alloc()
4544 vm->vprop_page = vprop_page; in its_vpe_irq_domain_alloc()
4546 if (gic_rdists->has_rvpeid) in its_vpe_irq_domain_alloc()
4550 vm->vpes[i]->vpe_db_lpi = base + i; in its_vpe_irq_domain_alloc()
4551 err = its_vpe_init(vm->vpes[i]); in its_vpe_irq_domain_alloc()
4555 vm->vpes[i]->vpe_db_lpi); in its_vpe_irq_domain_alloc()
4559 irqchip, vm->vpes[i]); in its_vpe_irq_domain_alloc()
4579 struct its_node *its; in its_vpe_irq_domain_activate() local
4590 vpe->col_idx = cpumask_first(cpu_online_mask); in its_vpe_irq_domain_activate()
4592 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_irq_domain_activate()
4593 if (!is_v4(its)) in its_vpe_irq_domain_activate()
4596 its_send_vmapp(its, vpe, true); in its_vpe_irq_domain_activate()
4597 its_send_vinvall(its, vpe); in its_vpe_irq_domain_activate()
4600 irq_data_update_effective_affinity(d, cpumask_of(vpe->col_idx)); in its_vpe_irq_domain_activate()
4609 struct its_node *its; in its_vpe_irq_domain_deactivate() local
4618 list_for_each_entry(its, &its_nodes, entry) { in its_vpe_irq_domain_deactivate()
4619 if (!is_v4(its)) in its_vpe_irq_domain_deactivate()
4622 its_send_vmapp(its, vpe, false); in its_vpe_irq_domain_deactivate()
4630 if (find_4_1_its() && !atomic_read(&vpe->vmapp_count)) in its_vpe_irq_domain_deactivate()
4631 gic_flush_dcache_to_poc(page_address(vpe->vpt_page), in its_vpe_irq_domain_deactivate()
4649 * GIC architecture specification requires the ITS to be both in its_force_quiescent()
4656 /* Disable the generation of all interrupts to this ITS */ in its_force_quiescent()
4660 /* Poll GITS_CTLR and wait until ITS becomes quiescent */ in its_force_quiescent()
4666 count--; in its_force_quiescent()
4668 return -EBUSY; in its_force_quiescent()
4677 struct its_node *its = data; in its_enable_quirk_cavium_22375() local
4680 its->typer &= ~GITS_TYPER_DEVBITS; in its_enable_quirk_cavium_22375()
4681 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, 20 - 1); in its_enable_quirk_cavium_22375()
4682 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_22375; in its_enable_quirk_cavium_22375()
4689 struct its_node *its = data; in its_enable_quirk_cavium_23144() local
4691 its->flags |= ITS_FLAGS_WORKAROUND_CAVIUM_23144; in its_enable_quirk_cavium_23144()
4698 struct its_node *its = data; in its_enable_quirk_qdf2400_e0065() local
4701 its->typer &= ~GITS_TYPER_ITT_ENTRY_SIZE; in its_enable_quirk_qdf2400_e0065()
4702 its->typer |= FIELD_PREP(GITS_TYPER_ITT_ENTRY_SIZE, 16 - 1); in its_enable_quirk_qdf2400_e0065()
4709 struct its_node *its = its_dev->its; in its_irq_get_msi_base_pre_its() local
4712 * The Socionext Synquacer SoC has a so-called 'pre-ITS', in its_irq_get_msi_base_pre_its()
4713 * which maps 32-bit writes targeted at a separate window of in its_irq_get_msi_base_pre_its()
4718 return its->pre_its_base + (its_dev->device_id << 2); in its_irq_get_msi_base_pre_its()
4723 struct its_node *its = data; in its_enable_quirk_socionext_synquacer() local
4727 if (!fwnode_property_read_u32_array(its->fwnode_handle, in its_enable_quirk_socionext_synquacer()
4728 "socionext,synquacer-pre-its", in its_enable_quirk_socionext_synquacer()
4732 its->pre_its_base = pre_its_window[0]; in its_enable_quirk_socionext_synquacer()
4733 its->get_msi_base = its_irq_get_msi_base_pre_its; in its_enable_quirk_socionext_synquacer()
4735 ids = ilog2(pre_its_window[1]) - 2; in its_enable_quirk_socionext_synquacer()
4736 if (device_ids(its) > ids) { in its_enable_quirk_socionext_synquacer()
4737 its->typer &= ~GITS_TYPER_DEVBITS; in its_enable_quirk_socionext_synquacer()
4738 its->typer |= FIELD_PREP(GITS_TYPER_DEVBITS, ids - 1); in its_enable_quirk_socionext_synquacer()
4741 /* the pre-ITS breaks isolation, so disable MSI remapping */ in its_enable_quirk_socionext_synquacer()
4742 its->msi_domain_flags &= ~IRQ_DOMAIN_FLAG_ISOLATED_MSI; in its_enable_quirk_socionext_synquacer()
4750 struct its_node *its = data; in its_enable_quirk_hip07_161600802() local
4756 its->vlpi_redist_offset = SZ_128K; in its_enable_quirk_hip07_161600802()
4762 struct its_node *its = data; in its_enable_rk3588001() local
4768 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; in its_enable_rk3588001()
4769 gic_rdists->flags |= RDIST_FLAGS_FORCE_NON_SHAREABLE; in its_enable_rk3588001()
4776 struct its_node *its = data; in its_set_non_coherent() local
4778 its->flags |= ITS_FLAGS_FORCE_NON_SHAREABLE; in its_set_non_coherent()
4785 .desc = "ITS: Cavium errata 22375, 24313",
4793 .desc = "ITS: Cavium erratum 23144",
4801 .desc = "ITS: QDF2400 erratum 0065",
4802 .iidr = 0x00001070, /* QDF2400 ITS rev 1.x */
4810 * The Socionext Synquacer SoC incorporates ARM's own GIC-500
4811 * implementation, but with a 'pre-ITS' added that requires
4814 .desc = "ITS: Socionext Synquacer pre-ITS",
4822 .desc = "ITS: Hip07 erratum 161600802",
4830 .desc = "ITS: Rockchip erratum RK3588001",
4837 .desc = "ITS: non-coherent attribute",
4838 .property = "dma-noncoherent",
4845 static void its_enable_quirks(struct its_node *its) in its_enable_quirks() argument
4847 u32 iidr = readl_relaxed(its->base + GITS_IIDR); in its_enable_quirks()
4849 gic_enable_quirks(iidr, its_quirks, its); in its_enable_quirks()
4851 if (is_of_node(its->fwnode_handle)) in its_enable_quirks()
4852 gic_enable_of_quirks(to_of_node(its->fwnode_handle), in its_enable_quirks()
4853 its_quirks, its); in its_enable_quirks()
4858 struct its_node *its; in its_save_disable() local
4862 list_for_each_entry(its, &its_nodes, entry) { in its_save_disable()
4865 base = its->base; in its_save_disable()
4866 its->ctlr_save = readl_relaxed(base + GITS_CTLR); in its_save_disable()
4869 pr_err("ITS@%pa: failed to quiesce: %d\n", in its_save_disable()
4870 &its->phys_base, err); in its_save_disable()
4871 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_save_disable()
4875 its->cbaser_save = gits_read_cbaser(base + GITS_CBASER); in its_save_disable()
4880 list_for_each_entry_continue_reverse(its, &its_nodes, entry) { in its_save_disable()
4883 base = its->base; in its_save_disable()
4884 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_save_disable()
4894 struct its_node *its; in its_restore_enable() local
4898 list_for_each_entry(its, &its_nodes, entry) { in its_restore_enable()
4902 base = its->base; in its_restore_enable()
4905 * Make sure that the ITS is disabled. If it fails to quiesce, in its_restore_enable()
4907 * registers is undefined according to the GIC v3 ITS in its_restore_enable()
4910 * Firmware resuming with the ITS enabled is terminally broken. in its_restore_enable()
4915 pr_err("ITS@%pa: failed to quiesce on resume: %d\n", in its_restore_enable()
4916 &its->phys_base, ret); in its_restore_enable()
4920 gits_write_cbaser(its->cbaser_save, base + GITS_CBASER); in its_restore_enable()
4926 its->cmd_write = its->cmd_base; in its_restore_enable()
4931 struct its_baser *baser = &its->tables[i]; in its_restore_enable()
4933 if (!(baser->val & GITS_BASER_VALID)) in its_restore_enable()
4936 its_write_baser(its, baser, baser->val); in its_restore_enable()
4938 writel_relaxed(its->ctlr_save, base + GITS_CTLR); in its_restore_enable()
4941 * Reinit the collection if it's stored in the ITS. This is in its_restore_enable()
4945 if (its->collections[smp_processor_id()].col_id < in its_restore_enable()
4947 its_cpu_init_collection(its); in its_restore_enable()
4962 its_base = ioremap(res->start, SZ_64K); in its_map_one()
4964 pr_warn("ITS@%pa: Unable to map ITS registers\n", &res->start); in its_map_one()
4965 *err = -ENOMEM; in its_map_one()
4971 pr_warn("ITS@%pa: No ITS detected, giving up\n", &res->start); in its_map_one()
4972 *err = -ENODEV; in its_map_one()
4978 pr_warn("ITS@%pa: Failed to quiesce, giving up\n", &res->start); in its_map_one()
4989 static int its_init_domain(struct its_node *its) in its_init_domain() argument
4996 return -ENOMEM; in its_init_domain()
4998 info->ops = &its_msi_domain_ops; in its_init_domain()
4999 info->data = its; in its_init_domain()
5002 its->msi_domain_flags, 0, in its_init_domain()
5003 its->fwnode_handle, &its_domain_ops, in its_init_domain()
5007 return -ENOMEM; in its_init_domain()
5017 struct its_node *its; in its_init_vpe_domain() local
5021 if (gic_rdists->has_direct_lpi) { in its_init_vpe_domain()
5022 pr_info("ITS: Using DirectLPI for VPE invalidation\n"); in its_init_vpe_domain()
5026 /* Any ITS will do, even if not v4 */ in its_init_vpe_domain()
5027 its = list_first_entry(&its_nodes, struct its_node, entry); in its_init_vpe_domain()
5033 return -ENOMEM; in its_init_vpe_domain()
5036 devid = GENMASK(device_ids(its) - 1, 0); in its_init_vpe_domain()
5037 vpe_proxy.dev = its_create_device(its, devid, entries, false); in its_init_vpe_domain()
5040 pr_err("ITS: Can't allocate GICv4 proxy device\n"); in its_init_vpe_domain()
5041 return -ENOMEM; in its_init_vpe_domain()
5044 BUG_ON(entries > vpe_proxy.dev->nr_ites); in its_init_vpe_domain()
5048 pr_info("ITS: Allocated DevID %x as GICv4 proxy device (%d slots)\n", in its_init_vpe_domain()
5049 devid, vpe_proxy.dev->nr_ites); in its_init_vpe_domain()
5054 static int __init its_compute_its_list_map(struct its_node *its) in its_compute_its_list_map() argument
5061 * guaranteed to be single-threaded, hence no in its_compute_its_list_map()
5067 pr_err("ITS@%pa: No ITSList entry available!\n", in its_compute_its_list_map()
5068 &its->phys_base); in its_compute_its_list_map()
5069 return -EINVAL; in its_compute_its_list_map()
5072 ctlr = readl_relaxed(its->base + GITS_CTLR); in its_compute_its_list_map()
5075 writel_relaxed(ctlr, its->base + GITS_CTLR); in its_compute_its_list_map()
5076 ctlr = readl_relaxed(its->base + GITS_CTLR); in its_compute_its_list_map()
5083 pr_err("ITS@%pa: Duplicate ITSList entry %d\n", in its_compute_its_list_map()
5084 &its->phys_base, its_number); in its_compute_its_list_map()
5085 return -EINVAL; in its_compute_its_list_map()
5091 static int __init its_probe_one(struct its_node *its) in its_probe_one() argument
5098 its_enable_quirks(its); in its_probe_one()
5100 if (is_v4(its)) { in its_probe_one()
5101 if (!(its->typer & GITS_TYPER_VMOVP)) { in its_probe_one()
5102 err = its_compute_its_list_map(its); in its_probe_one()
5106 its->list_nr = err; in its_probe_one()
5108 pr_info("ITS@%pa: Using ITS number %d\n", in its_probe_one()
5109 &its->phys_base, err); in its_probe_one()
5111 pr_info("ITS@%pa: Single VMOVP capable\n", &its->phys_base); in its_probe_one()
5114 if (is_v4_1(its)) { in its_probe_one()
5115 u32 svpet = FIELD_GET(GITS_TYPER_SVPET, its->typer); in its_probe_one()
5117 its->sgir_base = ioremap(its->phys_base + SZ_128K, SZ_64K); in its_probe_one()
5118 if (!its->sgir_base) { in its_probe_one()
5119 err = -ENOMEM; in its_probe_one()
5123 its->mpidr = readl_relaxed(its->base + GITS_MPIDR); in its_probe_one()
5125 pr_info("ITS@%pa: Using GICv4.1 mode %08x %08x\n", in its_probe_one()
5126 &its->phys_base, its->mpidr, svpet); in its_probe_one()
5130 page = alloc_pages_node(its->numa_node, GFP_KERNEL | __GFP_ZERO, in its_probe_one()
5133 err = -ENOMEM; in its_probe_one()
5136 its->cmd_base = (void *)page_address(page); in its_probe_one()
5137 its->cmd_write = its->cmd_base; in its_probe_one()
5139 err = its_alloc_tables(its); in its_probe_one()
5143 err = its_alloc_collections(its); in its_probe_one()
5147 baser = (virt_to_phys(its->cmd_base) | in its_probe_one()
5150 (ITS_CMD_QUEUE_SZ / SZ_4K - 1) | in its_probe_one()
5153 gits_write_cbaser(baser, its->base + GITS_CBASER); in its_probe_one()
5154 tmp = gits_read_cbaser(its->base + GITS_CBASER); in its_probe_one()
5156 if (its->flags & ITS_FLAGS_FORCE_NON_SHAREABLE) in its_probe_one()
5162 * The HW reports non-shareable, we must in its_probe_one()
5169 gits_write_cbaser(baser, its->base + GITS_CBASER); in its_probe_one()
5171 pr_info("ITS: using cache flushing for cmd queue\n"); in its_probe_one()
5172 its->flags |= ITS_FLAGS_CMDQ_NEEDS_FLUSHING; in its_probe_one()
5175 gits_write_cwriter(0, its->base + GITS_CWRITER); in its_probe_one()
5176 ctlr = readl_relaxed(its->base + GITS_CTLR); in its_probe_one()
5178 if (is_v4(its)) in its_probe_one()
5180 writel_relaxed(ctlr, its->base + GITS_CTLR); in its_probe_one()
5182 err = its_init_domain(its); in its_probe_one()
5187 list_add(&its->entry, &its_nodes); in its_probe_one()
5193 its_free_tables(its); in its_probe_one()
5195 free_pages((unsigned long)its->cmd_base, get_order(ITS_CMD_QUEUE_SZ)); in its_probe_one()
5197 if (its->sgir_base) in its_probe_one()
5198 iounmap(its->sgir_base); in its_probe_one()
5200 pr_err("ITS@%pa: failed probing (%d)\n", &its->phys_base, err); in its_probe_one()
5217 return -ENXIO; in redist_disable_lpis()
5226 * LPIs before trying to re-enable them. They are already in redist_disable_lpis()
5231 if ((gic_data_rdist()->flags & RD_LOCAL_LPI_ENABLED) || in redist_disable_lpis()
5232 (gic_rdists->flags & RDIST_FLAGS_RD_TABLES_PREALLOCATED)) in redist_disable_lpis()
5258 return -ETIMEDOUT; in redist_disable_lpis()
5261 timeout--; in redist_disable_lpis()
5271 return -EBUSY; in redist_disable_lpis()
5295 cpuhp_remove_state_nocalls(gic_rdists->cpuhp_memreserve_state); in rdist_memreserve_cpuhp_cleanup_workfn()
5296 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID; in rdist_memreserve_cpuhp_cleanup_workfn()
5308 if (gic_data_rdist()->flags & RD_LOCAL_MEMRESERVE_DONE) in its_cpu_memreserve_lpi()
5311 pend_page = gic_data_rdist()->pend_page; in its_cpu_memreserve_lpi()
5313 ret = -ENOMEM; in its_cpu_memreserve_lpi()
5317 * If the pending table was pre-programmed, free the memory we in its_cpu_memreserve_lpi()
5321 if (gic_data_rdist()->flags & RD_LOCAL_PENDTABLE_PREALLOCATED) { in its_cpu_memreserve_lpi()
5323 gic_data_rdist()->pend_page = NULL; in its_cpu_memreserve_lpi()
5335 gic_data_rdist()->flags |= RD_LOCAL_MEMRESERVE_DONE; in its_cpu_memreserve_lpi()
5357 { .compatible = "arm,gic-v3-its", },
5365 struct its_node *its; in its_node_init() local
5372 pr_info("ITS %pR\n", res); in its_node_init()
5374 its = kzalloc(sizeof(*its), GFP_KERNEL); in its_node_init()
5375 if (!its) in its_node_init()
5378 raw_spin_lock_init(&its->lock); in its_node_init()
5379 mutex_init(&its->dev_alloc_lock); in its_node_init()
5380 INIT_LIST_HEAD(&its->entry); in its_node_init()
5381 INIT_LIST_HEAD(&its->its_device_list); in its_node_init()
5383 its->typer = gic_read_typer(its_base + GITS_TYPER); in its_node_init()
5384 its->base = its_base; in its_node_init()
5385 its->phys_base = res->start; in its_node_init()
5386 its->get_msi_base = its_irq_get_msi_base; in its_node_init()
5387 its->msi_domain_flags = IRQ_DOMAIN_FLAG_ISOLATED_MSI; in its_node_init()
5389 its->numa_node = numa_node; in its_node_init()
5390 its->fwnode_handle = handle; in its_node_init()
5392 return its; in its_node_init()
5399 static void its_node_destroy(struct its_node *its) in its_node_destroy() argument
5401 iounmap(its->base); in its_node_destroy()
5402 kfree(its); in its_node_destroy()
5412 * Make sure *all* the ITS are reset before we probe any, as in its_of_probe()
5413 * they may be sharing memory. If any of the ITS fails to in its_of_probe()
5420 !of_property_read_bool(np, "msi-controller") || in its_of_probe()
5431 struct its_node *its; in its_of_probe() local
5435 if (!of_property_read_bool(np, "msi-controller")) { in its_of_probe()
5436 pr_warn("%pOF: no msi-controller property, ITS ignored\n", in its_of_probe()
5447 its = its_node_init(&res, &np->fwnode, of_node_to_nid(np)); in its_of_probe()
5448 if (!its) in its_of_probe()
5449 return -ENOMEM; in its_of_probe()
5451 err = its_probe_one(its); in its_of_probe()
5453 its_node_destroy(its); in its_of_probe()
5468 /* GIC ITS ID */
5500 return -EINVAL; in gic_acpi_parse_srat_its()
5502 if (its_affinity->header.length < sizeof(*its_affinity)) { in gic_acpi_parse_srat_its()
5503 pr_err("SRAT: Invalid header length %d in ITS affinity\n", in gic_acpi_parse_srat_its()
5504 its_affinity->header.length); in gic_acpi_parse_srat_its()
5505 return -EINVAL; in gic_acpi_parse_srat_its()
5513 node = pxm_to_node(its_affinity->proximity_domain); in gic_acpi_parse_srat_its()
5516 pr_err("SRAT: Invalid NUMA node %d in ITS affinity\n", node); in gic_acpi_parse_srat_its()
5521 its_srat_maps[its_in_srat].its_id = its_affinity->its_id; in gic_acpi_parse_srat_its()
5523 pr_info("SRAT: PXM %d -> ITS %d -> Node %d\n", in gic_acpi_parse_srat_its()
5524 its_affinity->proximity_domain, its_affinity->its_id, node); in gic_acpi_parse_srat_its()
5551 /* free the its_srat_maps after ITS probing */
5567 struct its_node *its; in gic_acpi_parse_madt_its() local
5573 res.start = its_entry->base_address; in gic_acpi_parse_madt_its()
5574 res.end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1; in gic_acpi_parse_madt_its()
5579 pr_err("ITS@%pa: Unable to allocate GICv3 ITS domain token\n", in gic_acpi_parse_madt_its()
5581 return -ENOMEM; in gic_acpi_parse_madt_its()
5584 err = iort_register_domain_token(its_entry->translation_id, res.start, in gic_acpi_parse_madt_its()
5587 pr_err("ITS@%pa: Unable to register GICv3 ITS domain token (ITS ID %d) to IORT\n", in gic_acpi_parse_madt_its()
5588 &res.start, its_entry->translation_id); in gic_acpi_parse_madt_its()
5592 its = its_node_init(&res, dom_handle, in gic_acpi_parse_madt_its()
5593 acpi_get_its_numa_node(its_entry->translation_id)); in gic_acpi_parse_madt_its()
5594 if (!its) { in gic_acpi_parse_madt_its()
5595 err = -ENOMEM; in gic_acpi_parse_madt_its()
5599 err = its_probe_one(its); in gic_acpi_parse_madt_its()
5604 iort_deregister_domain_token(its_entry->translation_id); in gic_acpi_parse_madt_its()
5618 .start = its_entry->base_address, in its_acpi_reset()
5619 .end = its_entry->base_address + ACPI_GICV3_ITS_MEM_SIZE - 1, in its_acpi_reset()
5630 * Make sure *all* the ITS are reset before we probe any, as in its_acpi_probe()
5631 * they may be sharing memory. If any of the ITS fails to in its_acpi_probe()
5655 gic_rdists->cpuhp_memreserve_state = CPUHP_INVALID; in its_lpi_memreserve_init()
5663 gic_rdists->cpuhp_memreserve_state = state; in its_lpi_memreserve_init()
5672 struct its_node *its; in its_init() local
5687 pr_warn("ITS: No ITS available, not enabling LPIs\n"); in its_init()
5688 return -ENXIO; in its_init()
5695 list_for_each_entry(its, &its_nodes, entry) { in its_init()
5696 has_v4 |= is_v4(its); in its_init()
5697 has_v4_1 |= is_v4_1(its); in its_init()
5701 if (WARN_ON(!has_v4_1 && rdists->has_rvpeid)) in its_init()
5702 rdists->has_rvpeid = false; in its_init()
5704 if (has_v4 & rdists->has_vlpis) { in its_init()
5714 rdists->has_vlpis = false; in its_init()
5715 pr_err("ITS: Disabling GICv4 support\n"); in its_init()