7  * Gregory CLEMENT <gregory.clement@free-electrons.com>
8  * Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
44  * +---------------+     +---------------+
46  * |    per-CPU    |	 |    per-CPU    |
50  * +---------------+	 +---------------+
55  *            +-------------------+
60  *            +-------------------+
68  * ARMADA_370_XP_INT_CLEAR_ENABLE_OFFS registers, which are relative
71  * The "per-CPU mask/unmask" is modified using the
73  * ARMADA_370_XP_INT_CLEAR_MASK_OFFS registers, which are relative to
77  * The per-CPU mask/unmask can also be adjusted using the global
78  * per-interrupt ARMADA_370_XP_INT_SOURCE_CTL register, which we use
82  * different levels: at the global level and at the per-CPU level.
86  *  - For global interrupts:
88  *    At ->map() time, a global interrupt is unmasked at the per-CPU
90  *    the current CPU, running the ->map() code. This allows to have
91  *    the interrupt unmasked at this level in non-SMP
92  *    configurations. In SMP configurations, the ->set_affinity()
94  *    ARMADA_370_XP_INT_SOURCE_CTL() readjusts the per-CPU mask/unmask
97  *    The ->mask() and ->unmask() operations only mask/unmask the
100  *    So, a global interrupt is enabled at the per-CPU level as soon
104  *  - For per-CPU interrupts
106  *    At ->map() time, a per-CPU interrupt is unmasked at the global
109  *    The ->mask() and ->unmask() operations mask/unmask the interrupt
110  *    at the per-CPU level.
112  *    So, a per-CPU interrupt is enabled at the global level as soon
114  *    at the per-CPU level.
117 /* Registers relative to main_int_base */
126 /* Registers relative to per_cpu_int_base */
207 	.chip	= &armada_370_xp_msi_irq_chip,
214 	msg->address_lo = lower_32_bits(msi_doorbell_addr);  in armada_370_xp_compose_msi_msg()
215 	msg->address_hi = upper_32_bits(msi_doorbell_addr);  in armada_370_xp_compose_msi_msg()
216 	msg->data = BIT(cpu + 8) | (data->hwirq + PCI_MSI_DOORBELL_START);  in armada_370_xp_compose_msi_msg()
230 		return -EINVAL;  in armada_370_xp_msi_set_affinity()
254 		return -ENOSPC;  in armada_370_xp_msi_alloc()
259 				    domain->host_data, handle_simple_irq,  in armada_370_xp_msi_alloc()
272 	bitmap_release_region(msi_used, d->hwirq, order_base_2(nr_irqs));  in armada_370_xp_msi_free()
303 		return -ENOMEM;  in armada_370_xp_msi_init()
311 		return -ENOMEM;  in armada_370_xp_msi_init()
336 	if (!of_machine_is_compatible("marvell,armada-370-xp"))  in armada_xp_mpic_perf_init()
353 	reg &= ~BIT(d->hwirq);  in armada_370_xp_ipi_mask()
361 	reg |= BIT(d->hwirq);  in armada_370_xp_ipi_unmask()
382 	writel((map << 8) | d->hwirq, main_int_base +  in armada_370_xp_ipi_send_mask()
388 	writel(~BIT(d->hwirq), per_cpu_int_base + ARMADA_370_XP_IN_DRBEL_CAUSE_OFFS);  in armada_370_xp_ipi_ack()
408 				    d->host_data,  in armada_370_xp_ipi_alloc()
513 	/* Re-enable per-CPU interrupts that were enabled before suspend */  in armada_xp_mpic_reenable_percpu()
615 		irq = msinr - PCI_MSI_DOORBELL_START;  in armada_370_xp_handle_msi_irq()
626 	struct irq_chip *chip = irq_desc_get_chip(desc);  in armada_370_xp_mpic_handle_cascade_irq()  local
629 	chained_irq_enter(chip, desc);  in armada_370_xp_mpic_handle_cascade_irq()
639 		 * Test IRQ (0-1) and FIQ (8-9) mask bits.  in armada_370_xp_mpic_handle_cascade_irq()
652 	chained_irq_exit(chip, desc);  in armada_370_xp_mpic_handle_cascade_irq()
708 	/* Re-enable interrupts */  in armada_370_xp_mpic_resume()
721 			/* Non per-CPU interrupts */  in armada_370_xp_mpic_resume()
727 			/* Per-CPU interrupts */  in armada_370_xp_mpic_resume()
732 			 * Re-enable on the current CPU,  in armada_370_xp_mpic_resume()
769 				   node->full_name));  in armada_370_xp_mpic_of_init()
772 				   node->full_name));  in armada_370_xp_mpic_of_init()