796 static int __init aic_init_smp(struct aic_irq_chip *irqc, struct device_node *node)  in aic_init_smp()  argument
918 	struct aic_irq_chip *irqc;  in aic_of_ic_init()  local
926 	irqc = kzalloc(sizeof(*irqc), GFP_KERNEL);  in aic_of_ic_init()
927 	if (!irqc) {  in aic_of_ic_init()
932 	irqc->base = regs;  in aic_of_ic_init()
938 	irqc->info = *(struct aic_info *)match->data;  in aic_of_ic_init()
940 	aic_irqc = irqc;  in aic_of_ic_init()
942 	switch (irqc->info.version) {  in aic_of_ic_init()
946 		info = aic_ic_read(irqc, AIC_INFO);  in aic_of_ic_init()
947 		irqc->nr_irq = FIELD_GET(AIC_INFO_NR_IRQ, info);  in aic_of_ic_init()
948 		irqc->max_irq = AIC_MAX_IRQ;  in aic_of_ic_init()
949 		irqc->nr_die = irqc->max_die = 1;  in aic_of_ic_init()
951 		off = start_off = irqc->info.target_cpu;  in aic_of_ic_init()
952 		off += sizeof(u32) * irqc->max_irq; /* TARGET_CPU */  in aic_of_ic_init()
954 		irqc->event = irqc->base;  in aic_of_ic_init()
961 		info1 = aic_ic_read(irqc, AIC2_INFO1);  in aic_of_ic_init()
962 		info3 = aic_ic_read(irqc, AIC2_INFO3);  in aic_of_ic_init()
964 		irqc->nr_irq = FIELD_GET(AIC2_INFO1_NR_IRQ, info1);  in aic_of_ic_init()
965 		irqc->max_irq = FIELD_GET(AIC2_INFO3_MAX_IRQ, info3);  in aic_of_ic_init()
966 		irqc->nr_die = FIELD_GET(AIC2_INFO1_LAST_DIE, info1) + 1;  in aic_of_ic_init()
967 		irqc->max_die = FIELD_GET(AIC2_INFO3_MAX_DIE, info3);  in aic_of_ic_init()
969 		off = start_off = irqc->info.irq_cfg;  in aic_of_ic_init()
970 		off += sizeof(u32) * irqc->max_irq; /* IRQ_CFG */  in aic_of_ic_init()
972 		irqc->event = of_iomap(node, 1);  in aic_of_ic_init()
973 		if (WARN_ON(!irqc->event))  in aic_of_ic_init()
980 	irqc->info.sw_set = off;  in aic_of_ic_init()
981 	off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_SET */  in aic_of_ic_init()
982 	irqc->info.sw_clr = off;  in aic_of_ic_init()
983 	off += sizeof(u32) * (irqc->max_irq >> 5); /* SW_CLR */  in aic_of_ic_init()
984 	irqc->info.mask_set = off;  in aic_of_ic_init()
985 	off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_SET */  in aic_of_ic_init()
986 	irqc->info.mask_clr = off;  in aic_of_ic_init()
987 	off += sizeof(u32) * (irqc->max_irq >> 5); /* MASK_CLR */  in aic_of_ic_init()
988 	off += sizeof(u32) * (irqc->max_irq >> 5); /* HW_STATE */  in aic_of_ic_init()
990 	if (irqc->info.fast_ipi)  in aic_of_ic_init()
995 	irqc->info.die_stride = off - start_off;  in aic_of_ic_init()
997 	irqc->hw_domain = irq_domain_create_tree(of_node_to_fwnode(node),  in aic_of_ic_init()
998 						 &aic_irq_domain_ops, irqc);  in aic_of_ic_init()
999 	if (WARN_ON(!irqc->hw_domain))  in aic_of_ic_init()
1002 	irq_domain_update_bus_token(irqc->hw_domain, DOMAIN_BUS_WIRED);  in aic_of_ic_init()
1004 	if (aic_init_smp(irqc, node))  in aic_of_ic_init()
1012 			build_fiq_affinity(irqc, chld);  in aic_of_ic_init()
1020 	for (die = 0; die < irqc->nr_die; die++) {  in aic_of_ic_init()
1021 		for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++)  in aic_of_ic_init()
1022 			aic_ic_write(irqc, irqc->info.mask_set + off + i * 4, U32_MAX);  in aic_of_ic_init()
1023 		for (i = 0; i < BITS_TO_U32(irqc->nr_irq); i++)  in aic_of_ic_init()
1024 			aic_ic_write(irqc, irqc->info.sw_clr + off + i * 4, U32_MAX);  in aic_of_ic_init()
1025 		if (irqc->info.target_cpu)  in aic_of_ic_init()
1026 			for (i = 0; i < irqc->nr_irq; i++)  in aic_of_ic_init()
1027 				aic_ic_write(irqc, irqc->info.target_cpu + off + i * 4, 1);  in aic_of_ic_init()
1028 		off += irqc->info.die_stride;  in aic_of_ic_init()
1031 	if (irqc->info.version == 2) {  in aic_of_ic_init()
1032 		u32 config = aic_ic_read(irqc, AIC2_CONFIG);  in aic_of_ic_init()
1035 		aic_ic_write(irqc, AIC2_CONFIG, config);  in aic_of_ic_init()
1066 		irqc->nr_irq, irqc->max_irq, irqc->nr_die, irqc->max_die, AIC_NR_FIQ, AIC_NR_SWIPI);  in aic_of_ic_init()
1071 	irq_domain_remove(irqc->hw_domain);  in aic_of_ic_init()
1073 	if (irqc->event && irqc->event != irqc->base)  in aic_of_ic_init()
1074 		iounmap(irqc->event);  in aic_of_ic_init()
1075 	iounmap(irqc->base);  in aic_of_ic_init()
1076 	kfree(irqc);  in aic_of_ic_init()