377 	/* Tlb flush all always is in bank0. */  in mtk_iommu_tlb_flush_all()
1037 	const struct mtk_iommu_bank_data *bank0 = &data->bank[0];  in mtk_iommu_hw_init()  local
1041 	 * Global control settings are in bank0. May re-init these global registers  in mtk_iommu_hw_init()
1042 	 * since no sure if there is bank0 consumers.  in mtk_iommu_hw_init()
1048 		regval = readl_relaxed(bank0->base + REG_MMU_CTRL_REG);  in mtk_iommu_hw_init()
1051 	writel_relaxed(regval, bank0->base + REG_MMU_CTRL_REG);  in mtk_iommu_hw_init()
1060 		writel_relaxed(regval, bank0->base + REG_MMU_VLD_PA_RNG);  in mtk_iommu_hw_init()
1063 		writel_relaxed(F_MMU_DCM, bank0->base + REG_MMU_DCM_DIS);  in mtk_iommu_hw_init()
1065 		writel_relaxed(0, bank0->base + REG_MMU_DCM_DIS);  in mtk_iommu_hw_init()
1069 		regval = readl_relaxed(bank0->base + REG_MMU_WR_LEN_CTRL);  in mtk_iommu_hw_init()
1071 		writel_relaxed(regval, bank0->base + REG_MMU_WR_LEN_CTRL);  in mtk_iommu_hw_init()
1078 		regval = readl_relaxed(bank0->base + REG_MMU_MISC_CTRL);  in mtk_iommu_hw_init()
1084 	writel_relaxed(regval, bank0->base + REG_MMU_MISC_CTRL);  in mtk_iommu_hw_init()