Lines Matching full:smmu
3 * IOMMU API for ARM architected SMMU implementations.
13 * - Non-secure access to the SMMU
18 #define pr_fmt(fmt) "arm-smmu: " fmt
40 #include "arm-smmu.h"
44 * Apparently, some Qualcomm arm64 platforms which appear to expose their SMMU
58 …"Force SMMU mappings to be installed at a particular stage of translation. A value of '1' or '2' f…
63 …domain will report an abort back to the device and will not be allowed to pass through the SMMU.");
71 static inline int arm_smmu_rpm_get(struct arm_smmu_device *smmu) in arm_smmu_rpm_get() argument
73 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_get()
74 return pm_runtime_resume_and_get(smmu->dev); in arm_smmu_rpm_get()
79 static inline void arm_smmu_rpm_put(struct arm_smmu_device *smmu) in arm_smmu_rpm_put() argument
81 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_rpm_put()
82 pm_runtime_put_autosuspend(smmu->dev); in arm_smmu_rpm_put()
85 static void arm_smmu_rpm_use_autosuspend(struct arm_smmu_device *smmu) in arm_smmu_rpm_use_autosuspend() argument
98 pm_runtime_set_autosuspend_delay(smmu->dev, 20); in arm_smmu_rpm_use_autosuspend()
99 pm_runtime_use_autosuspend(smmu->dev); in arm_smmu_rpm_use_autosuspend()
147 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
190 *smmu = dev_get_drvdata(smmu_dev); in arm_smmu_register_legacy_master()
198 struct arm_smmu_device **smmu) in arm_smmu_register_legacy_master() argument
210 static void __arm_smmu_tlb_sync(struct arm_smmu_device *smmu, int page, in __arm_smmu_tlb_sync() argument
216 if (smmu->impl && unlikely(smmu->impl->tlb_sync)) in __arm_smmu_tlb_sync()
217 return smmu->impl->tlb_sync(smmu, page, sync, status); in __arm_smmu_tlb_sync()
219 arm_smmu_writel(smmu, page, sync, QCOM_DUMMY_VAL); in __arm_smmu_tlb_sync()
222 reg = arm_smmu_readl(smmu, page, status); in __arm_smmu_tlb_sync()
229 dev_err_ratelimited(smmu->dev, in __arm_smmu_tlb_sync()
230 "TLB sync timed out -- SMMU may be deadlocked\n"); in __arm_smmu_tlb_sync()
233 static void arm_smmu_tlb_sync_global(struct arm_smmu_device *smmu) in arm_smmu_tlb_sync_global() argument
237 spin_lock_irqsave(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
238 __arm_smmu_tlb_sync(smmu, ARM_SMMU_GR0, ARM_SMMU_GR0_sTLBGSYNC, in arm_smmu_tlb_sync_global()
240 spin_unlock_irqrestore(&smmu->global_sync_lock, flags); in arm_smmu_tlb_sync_global()
245 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_sync_context() local
249 __arm_smmu_tlb_sync(smmu, ARM_SMMU_CB(smmu, smmu_domain->cfg.cbndx), in arm_smmu_tlb_sync_context()
262 arm_smmu_cb_write(smmu_domain->smmu, smmu_domain->cfg.cbndx, in arm_smmu_tlb_inv_context_s1()
270 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_context_s2() local
274 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_inv_context_s2()
275 arm_smmu_tlb_sync_global(smmu); in arm_smmu_tlb_inv_context_s2()
282 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s1() local
286 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s1()
293 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
300 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s1()
310 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_inv_range_s2() local
313 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_inv_range_s2()
319 arm_smmu_cb_writeq(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
321 arm_smmu_cb_write(smmu, idx, reg, iova); in arm_smmu_tlb_inv_range_s2()
382 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_tlb_add_page_s2_v1() local
384 if (smmu->features & ARM_SMMU_FEAT_COHERENT_WALK) in arm_smmu_tlb_add_page_s2_v1()
387 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIVMID, smmu_domain->cfg.vmid); in arm_smmu_tlb_add_page_s2_v1()
413 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_context_fault() local
417 fsr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSR); in arm_smmu_context_fault()
421 fsynr = arm_smmu_cb_read(smmu, idx, ARM_SMMU_CB_FSYNR0); in arm_smmu_context_fault()
422 iova = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_FAR); in arm_smmu_context_fault()
423 cbfrsynra = arm_smmu_gr1_read(smmu, ARM_SMMU_GR1_CBFRSYNRA(idx)); in arm_smmu_context_fault()
429 dev_err_ratelimited(smmu->dev, in arm_smmu_context_fault()
433 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_FSR, fsr); in arm_smmu_context_fault()
440 struct arm_smmu_device *smmu = dev; in arm_smmu_global_fault() local
444 gfsr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_global_fault()
445 gfsynr0 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR0); in arm_smmu_global_fault()
446 gfsynr1 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR1); in arm_smmu_global_fault()
447 gfsynr2 = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSYNR2); in arm_smmu_global_fault()
455 dev_err(smmu->dev, in arm_smmu_global_fault()
456 …"Blocked unknown Stream ID 0x%hx; boot with \"arm-smmu.disable_bypass=0\" to allow, but this may h… in arm_smmu_global_fault()
459 dev_err(smmu->dev, in arm_smmu_global_fault()
461 dev_err(smmu->dev, in arm_smmu_global_fault()
466 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, gfsr); in arm_smmu_global_fault()
474 struct arm_smmu_cb *cb = &smmu_domain->smmu->cbs[cfg->cbndx]; in arm_smmu_init_context_bank()
527 void arm_smmu_write_context_bank(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_context_bank() argument
531 struct arm_smmu_cb *cb = &smmu->cbs[idx]; in arm_smmu_write_context_bank()
536 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, 0); in arm_smmu_write_context_bank()
543 if (smmu->version > ARM_SMMU_V1) { in arm_smmu_write_context_bank()
549 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_write_context_bank()
552 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBA2R(idx), reg); in arm_smmu_write_context_bank()
557 if (smmu->version < ARM_SMMU_V2) in arm_smmu_write_context_bank()
569 } else if (!(smmu->features & ARM_SMMU_FEAT_VMID16)) { in arm_smmu_write_context_bank()
573 arm_smmu_gr1_write(smmu, ARM_SMMU_GR1_CBAR(idx), reg); in arm_smmu_write_context_bank()
580 if (stage1 && smmu->version > ARM_SMMU_V1) in arm_smmu_write_context_bank()
581 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR2, cb->tcr[1]); in arm_smmu_write_context_bank()
582 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TCR, cb->tcr[0]); in arm_smmu_write_context_bank()
586 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_CONTEXTIDR, cfg->asid); in arm_smmu_write_context_bank()
587 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
588 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_TTBR1, cb->ttbr[1]); in arm_smmu_write_context_bank()
590 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR0, cb->ttbr[0]); in arm_smmu_write_context_bank()
592 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_TTBR1, in arm_smmu_write_context_bank()
598 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR0, cb->mair[0]); in arm_smmu_write_context_bank()
599 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_S1_MAIR1, cb->mair[1]); in arm_smmu_write_context_bank()
610 if (smmu->impl && smmu->impl->write_sctlr) in arm_smmu_write_context_bank()
611 smmu->impl->write_sctlr(smmu, idx, reg); in arm_smmu_write_context_bank()
613 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_SCTLR, reg); in arm_smmu_write_context_bank()
617 struct arm_smmu_device *smmu, in arm_smmu_alloc_context_bank() argument
620 if (smmu->impl && smmu->impl->alloc_context_bank) in arm_smmu_alloc_context_bank()
621 return smmu->impl->alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_alloc_context_bank()
623 return __arm_smmu_alloc_bitmap(smmu->context_map, start, smmu->num_context_banks); in arm_smmu_alloc_context_bank()
627 struct arm_smmu_device *smmu, in arm_smmu_init_domain_context() argument
640 if (smmu_domain->smmu) in arm_smmu_init_domain_context()
661 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S1)) in arm_smmu_init_domain_context()
663 if (!(smmu->features & ARM_SMMU_FEAT_TRANS_S2)) in arm_smmu_init_domain_context()
674 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_L) in arm_smmu_init_domain_context()
678 (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) && in arm_smmu_init_domain_context()
682 (smmu->features & (ARM_SMMU_FEAT_FMT_AARCH64_64K | in arm_smmu_init_domain_context()
695 start = smmu->num_s2_context_banks; in arm_smmu_init_domain_context()
696 ias = smmu->va_size; in arm_smmu_init_domain_context()
697 oas = smmu->ipa_size; in arm_smmu_init_domain_context()
719 ias = smmu->ipa_size; in arm_smmu_init_domain_context()
720 oas = smmu->pa_size; in arm_smmu_init_domain_context()
728 if (smmu->version == ARM_SMMU_V2) in arm_smmu_init_domain_context()
738 ret = arm_smmu_alloc_context_bank(smmu_domain, smmu, dev, start); in arm_smmu_init_domain_context()
743 smmu_domain->smmu = smmu; in arm_smmu_init_domain_context()
746 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_init_domain_context()
747 cfg->irptndx = atomic_inc_return(&smmu->irptndx); in arm_smmu_init_domain_context()
748 cfg->irptndx %= smmu->num_context_irqs; in arm_smmu_init_domain_context()
759 .pgsize_bitmap = smmu->pgsize_bitmap, in arm_smmu_init_domain_context()
762 .coherent_walk = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK, in arm_smmu_init_domain_context()
764 .iommu_dev = smmu->dev, in arm_smmu_init_domain_context()
767 if (smmu->impl && smmu->impl->init_context) { in arm_smmu_init_domain_context()
768 ret = smmu->impl->init_context(smmu_domain, &pgtbl_cfg, dev); in arm_smmu_init_domain_context()
796 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_init_domain_context()
802 irq = smmu->irqs[cfg->irptndx]; in arm_smmu_init_domain_context()
804 if (smmu->impl && smmu->impl->context_fault) in arm_smmu_init_domain_context()
805 context_fault = smmu->impl->context_fault; in arm_smmu_init_domain_context()
809 ret = devm_request_irq(smmu->dev, irq, context_fault, IRQF_SHARED, in arm_smmu_init_domain_context()
810 "arm-smmu-context-fault", smmu_domain); in arm_smmu_init_domain_context()
812 dev_err(smmu->dev, "failed to request context IRQ %d (%u)\n", in arm_smmu_init_domain_context()
824 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_init_domain_context()
825 smmu_domain->smmu = NULL; in arm_smmu_init_domain_context()
833 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_destroy_domain_context() local
837 if (!smmu) in arm_smmu_destroy_domain_context()
840 ret = arm_smmu_rpm_get(smmu); in arm_smmu_destroy_domain_context()
848 smmu->cbs[cfg->cbndx].cfg = NULL; in arm_smmu_destroy_domain_context()
849 arm_smmu_write_context_bank(smmu, cfg->cbndx); in arm_smmu_destroy_domain_context()
852 irq = smmu->irqs[cfg->irptndx]; in arm_smmu_destroy_domain_context()
853 devm_free_irq(smmu->dev, irq, smmu_domain); in arm_smmu_destroy_domain_context()
857 __arm_smmu_free_bitmap(smmu->context_map, cfg->cbndx); in arm_smmu_destroy_domain_context()
859 arm_smmu_rpm_put(smmu); in arm_smmu_destroy_domain_context()
897 static void arm_smmu_write_smr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_smr() argument
899 struct arm_smmu_smr *smr = smmu->smrs + idx; in arm_smmu_write_smr()
903 if (!(smmu->features & ARM_SMMU_FEAT_EXIDS) && smr->valid) in arm_smmu_write_smr()
905 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(idx), reg); in arm_smmu_write_smr()
908 static void arm_smmu_write_s2cr(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_s2cr() argument
910 struct arm_smmu_s2cr *s2cr = smmu->s2crs + idx; in arm_smmu_write_s2cr()
913 if (smmu->impl && smmu->impl->write_s2cr) { in arm_smmu_write_s2cr()
914 smmu->impl->write_s2cr(smmu, idx); in arm_smmu_write_s2cr()
922 if (smmu->features & ARM_SMMU_FEAT_EXIDS && smmu->smrs && in arm_smmu_write_s2cr()
923 smmu->smrs[idx].valid) in arm_smmu_write_s2cr()
925 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_S2CR(idx), reg); in arm_smmu_write_s2cr()
928 static void arm_smmu_write_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_write_sme() argument
930 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_write_sme()
931 if (smmu->smrs) in arm_smmu_write_sme()
932 arm_smmu_write_smr(smmu, idx); in arm_smmu_write_sme()
939 static void arm_smmu_test_smr_masks(struct arm_smmu_device *smmu) in arm_smmu_test_smr_masks() argument
944 if (!smmu->smrs) in arm_smmu_test_smr_masks()
954 for (i = 0; i < smmu->num_mapping_groups; i++) in arm_smmu_test_smr_masks()
955 if (!smmu->smrs[i].valid) in arm_smmu_test_smr_masks()
964 smr = FIELD_PREP(ARM_SMMU_SMR_ID, smmu->streamid_mask); in arm_smmu_test_smr_masks()
965 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
966 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
967 smmu->streamid_mask = FIELD_GET(ARM_SMMU_SMR_ID, smr); in arm_smmu_test_smr_masks()
969 smr = FIELD_PREP(ARM_SMMU_SMR_MASK, smmu->streamid_mask); in arm_smmu_test_smr_masks()
970 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_SMR(i), smr); in arm_smmu_test_smr_masks()
971 smr = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_SMR(i)); in arm_smmu_test_smr_masks()
972 smmu->smr_mask_mask = FIELD_GET(ARM_SMMU_SMR_MASK, smr); in arm_smmu_test_smr_masks()
975 static int arm_smmu_find_sme(struct arm_smmu_device *smmu, u16 id, u16 mask) in arm_smmu_find_sme() argument
977 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_find_sme()
985 for (i = 0; i < smmu->num_mapping_groups; ++i) { in arm_smmu_find_sme()
1017 static bool arm_smmu_free_sme(struct arm_smmu_device *smmu, int idx) in arm_smmu_free_sme() argument
1019 if (--smmu->s2crs[idx].count) in arm_smmu_free_sme()
1022 smmu->s2crs[idx] = s2cr_init_val; in arm_smmu_free_sme()
1023 if (smmu->smrs) in arm_smmu_free_sme()
1024 smmu->smrs[idx].valid = false; in arm_smmu_free_sme()
1033 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_alloc_smes() local
1034 struct arm_smmu_smr *smrs = smmu->smrs; in arm_smmu_master_alloc_smes()
1037 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1048 ret = arm_smmu_find_sme(smmu, sid, mask); in arm_smmu_master_alloc_smes()
1053 if (smrs && smmu->s2crs[idx].count == 0) { in arm_smmu_master_alloc_smes()
1058 smmu->s2crs[idx].count++; in arm_smmu_master_alloc_smes()
1064 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_alloc_smes()
1066 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1071 arm_smmu_free_sme(smmu, cfg->smendx[i]); in arm_smmu_master_alloc_smes()
1074 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_alloc_smes()
1081 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_free_smes() local
1084 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1086 if (arm_smmu_free_sme(smmu, idx)) in arm_smmu_master_free_smes()
1087 arm_smmu_write_sme(smmu, idx); in arm_smmu_master_free_smes()
1090 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_master_free_smes()
1097 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_master_install_s2crs() local
1098 struct arm_smmu_s2cr *s2cr = smmu->s2crs; in arm_smmu_master_install_s2crs()
1108 arm_smmu_write_s2cr(smmu, idx); in arm_smmu_master_install_s2crs()
1117 struct arm_smmu_device *smmu; in arm_smmu_attach_dev() local
1131 smmu = cfg->smmu; in arm_smmu_attach_dev()
1133 ret = arm_smmu_rpm_get(smmu); in arm_smmu_attach_dev()
1138 ret = arm_smmu_init_domain_context(smmu_domain, smmu, dev); in arm_smmu_attach_dev()
1146 if (smmu_domain->smmu != smmu) { in arm_smmu_attach_dev()
1154 arm_smmu_rpm_use_autosuspend(smmu); in arm_smmu_attach_dev()
1156 arm_smmu_rpm_put(smmu); in arm_smmu_attach_dev()
1165 struct arm_smmu_device *smmu; in arm_smmu_attach_dev_type() local
1170 smmu = cfg->smmu; in arm_smmu_attach_dev_type()
1172 ret = arm_smmu_rpm_get(smmu); in arm_smmu_attach_dev_type()
1177 arm_smmu_rpm_use_autosuspend(smmu); in arm_smmu_attach_dev_type()
1178 arm_smmu_rpm_put(smmu); in arm_smmu_attach_dev_type()
1217 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_map_pages() local
1223 arm_smmu_rpm_get(smmu); in arm_smmu_map_pages()
1225 arm_smmu_rpm_put(smmu); in arm_smmu_map_pages()
1235 struct arm_smmu_device *smmu = to_smmu_domain(domain)->smmu; in arm_smmu_unmap_pages() local
1241 arm_smmu_rpm_get(smmu); in arm_smmu_unmap_pages()
1243 arm_smmu_rpm_put(smmu); in arm_smmu_unmap_pages()
1251 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_flush_iotlb_all() local
1254 arm_smmu_rpm_get(smmu); in arm_smmu_flush_iotlb_all()
1256 arm_smmu_rpm_put(smmu); in arm_smmu_flush_iotlb_all()
1264 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iotlb_sync() local
1266 if (!smmu) in arm_smmu_iotlb_sync()
1269 arm_smmu_rpm_get(smmu); in arm_smmu_iotlb_sync()
1270 if (smmu->version == ARM_SMMU_V2 || in arm_smmu_iotlb_sync()
1274 arm_smmu_tlb_sync_global(smmu); in arm_smmu_iotlb_sync()
1275 arm_smmu_rpm_put(smmu); in arm_smmu_iotlb_sync()
1282 struct arm_smmu_device *smmu = smmu_domain->smmu; in arm_smmu_iova_to_phys_hard() local
1285 struct device *dev = smmu->dev; in arm_smmu_iova_to_phys_hard()
1293 ret = arm_smmu_rpm_get(smmu); in arm_smmu_iova_to_phys_hard()
1300 arm_smmu_cb_writeq(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1302 arm_smmu_cb_write(smmu, idx, ARM_SMMU_CB_ATS1PR, va); in arm_smmu_iova_to_phys_hard()
1304 reg = arm_smmu_page(smmu, ARM_SMMU_CB(smmu, idx)) + ARM_SMMU_CB_ATSR; in arm_smmu_iova_to_phys_hard()
1311 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1315 phys = arm_smmu_cb_readq(smmu, idx, ARM_SMMU_CB_PAR); in arm_smmu_iova_to_phys_hard()
1325 arm_smmu_rpm_put(smmu); in arm_smmu_iova_to_phys_hard()
1339 if (smmu_domain->smmu->features & ARM_SMMU_FEAT_TRANS_OPS && in arm_smmu_iova_to_phys()
1358 return cfg->smmu->features & ARM_SMMU_FEAT_COHERENT_WALK || in arm_smmu_capable()
1379 struct arm_smmu_device *smmu = NULL; in arm_smmu_probe_device() local
1385 ret = arm_smmu_register_legacy_master(dev, &smmu); in arm_smmu_probe_device()
1396 smmu = arm_smmu_get_by_fwnode(fwspec->iommu_fwnode); in arm_smmu_probe_device()
1404 if (sid & ~smmu->streamid_mask) { in arm_smmu_probe_device()
1405 dev_err(dev, "stream ID 0x%x out of range for SMMU (0x%x)\n", in arm_smmu_probe_device()
1406 sid, smmu->streamid_mask); in arm_smmu_probe_device()
1409 if (mask & ~smmu->smr_mask_mask) { in arm_smmu_probe_device()
1410 dev_err(dev, "SMR mask 0x%x out of range for SMMU (0x%x)\n", in arm_smmu_probe_device()
1411 mask, smmu->smr_mask_mask); in arm_smmu_probe_device()
1422 cfg->smmu = smmu; in arm_smmu_probe_device()
1427 ret = arm_smmu_rpm_get(smmu); in arm_smmu_probe_device()
1432 arm_smmu_rpm_put(smmu); in arm_smmu_probe_device()
1437 device_link_add(dev, smmu->dev, in arm_smmu_probe_device()
1440 return &smmu->iommu; in arm_smmu_probe_device()
1455 ret = arm_smmu_rpm_get(cfg->smmu); in arm_smmu_release_device()
1461 arm_smmu_rpm_put(cfg->smmu); in arm_smmu_release_device()
1469 struct arm_smmu_device *smmu; in arm_smmu_probe_finalize() local
1472 smmu = cfg->smmu; in arm_smmu_probe_finalize()
1474 if (smmu->impl && smmu->impl->probe_finalize) in arm_smmu_probe_finalize()
1475 smmu->impl->probe_finalize(smmu, dev); in arm_smmu_probe_finalize()
1482 struct arm_smmu_device *smmu = cfg->smmu; in arm_smmu_device_group() local
1486 mutex_lock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1488 if (group && smmu->s2crs[idx].group && in arm_smmu_device_group()
1489 group != smmu->s2crs[idx].group) { in arm_smmu_device_group()
1490 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1494 group = smmu->s2crs[idx].group; in arm_smmu_device_group()
1498 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1512 smmu->s2crs[idx].group = group; in arm_smmu_device_group()
1514 mutex_unlock(&smmu->stream_map_mutex); in arm_smmu_device_group()
1524 if (smmu_domain->smmu) in arm_smmu_enable_nesting()
1540 if (smmu_domain->smmu) in arm_smmu_set_pgtable_quirks()
1583 const struct arm_smmu_impl *impl = cfg->smmu->impl; in arm_smmu_def_domain_type()
1621 static void arm_smmu_device_reset(struct arm_smmu_device *smmu) in arm_smmu_device_reset() argument
1627 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sGFSR); in arm_smmu_device_reset()
1628 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sGFSR, reg); in arm_smmu_device_reset()
1634 for (i = 0; i < smmu->num_mapping_groups; ++i) in arm_smmu_device_reset()
1635 arm_smmu_write_sme(smmu, i); in arm_smmu_device_reset()
1638 for (i = 0; i < smmu->num_context_banks; ++i) { in arm_smmu_device_reset()
1639 arm_smmu_write_context_bank(smmu, i); in arm_smmu_device_reset()
1640 arm_smmu_cb_write(smmu, i, ARM_SMMU_CB_FSR, ARM_SMMU_FSR_FAULT); in arm_smmu_device_reset()
1644 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1645 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_TLBIALLNSNH, QCOM_DUMMY_VAL); in arm_smmu_device_reset()
1647 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_device_reset()
1669 if (smmu->features & ARM_SMMU_FEAT_VMID16) in arm_smmu_device_reset()
1672 if (smmu->features & ARM_SMMU_FEAT_EXIDS) in arm_smmu_device_reset()
1675 if (smmu->impl && smmu->impl->reset) in arm_smmu_device_reset()
1676 smmu->impl->reset(smmu); in arm_smmu_device_reset()
1679 arm_smmu_tlb_sync_global(smmu); in arm_smmu_device_reset()
1680 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_device_reset()
1702 static int arm_smmu_device_cfg_probe(struct arm_smmu_device *smmu) in arm_smmu_device_cfg_probe() argument
1706 bool cttw_reg, cttw_fw = smmu->features & ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_cfg_probe()
1709 dev_notice(smmu->dev, "probing hardware configuration...\n"); in arm_smmu_device_cfg_probe()
1710 dev_notice(smmu->dev, "SMMUv%d with:\n", in arm_smmu_device_cfg_probe()
1711 smmu->version == ARM_SMMU_V2 ? 2 : 1); in arm_smmu_device_cfg_probe()
1714 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID0); in arm_smmu_device_cfg_probe()
1723 smmu->features |= ARM_SMMU_FEAT_TRANS_S1; in arm_smmu_device_cfg_probe()
1724 dev_notice(smmu->dev, "\tstage 1 translation\n"); in arm_smmu_device_cfg_probe()
1728 smmu->features |= ARM_SMMU_FEAT_TRANS_S2; in arm_smmu_device_cfg_probe()
1729 dev_notice(smmu->dev, "\tstage 2 translation\n"); in arm_smmu_device_cfg_probe()
1733 smmu->features |= ARM_SMMU_FEAT_TRANS_NESTED; in arm_smmu_device_cfg_probe()
1734 dev_notice(smmu->dev, "\tnested translation\n"); in arm_smmu_device_cfg_probe()
1737 if (!(smmu->features & in arm_smmu_device_cfg_probe()
1739 dev_err(smmu->dev, "\tno translation support!\n"); in arm_smmu_device_cfg_probe()
1744 ((smmu->version < ARM_SMMU_V2) || !(id & ARM_SMMU_ID0_ATOSNS))) { in arm_smmu_device_cfg_probe()
1745 smmu->features |= ARM_SMMU_FEAT_TRANS_OPS; in arm_smmu_device_cfg_probe()
1746 dev_notice(smmu->dev, "\taddress translation ops\n"); in arm_smmu_device_cfg_probe()
1757 dev_notice(smmu->dev, "\t%scoherent table walk\n", in arm_smmu_device_cfg_probe()
1760 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1764 if (smmu->version == ARM_SMMU_V2 && id & ARM_SMMU_ID0_EXIDS) { in arm_smmu_device_cfg_probe()
1765 smmu->features |= ARM_SMMU_FEAT_EXIDS; in arm_smmu_device_cfg_probe()
1770 smmu->streamid_mask = size - 1; in arm_smmu_device_cfg_probe()
1772 smmu->features |= ARM_SMMU_FEAT_STREAM_MATCH; in arm_smmu_device_cfg_probe()
1775 dev_err(smmu->dev, in arm_smmu_device_cfg_probe()
1781 smmu->smrs = devm_kcalloc(smmu->dev, size, sizeof(*smmu->smrs), in arm_smmu_device_cfg_probe()
1783 if (!smmu->smrs) in arm_smmu_device_cfg_probe()
1786 dev_notice(smmu->dev, in arm_smmu_device_cfg_probe()
1790 smmu->s2crs = devm_kmalloc_array(smmu->dev, size, sizeof(*smmu->s2crs), in arm_smmu_device_cfg_probe()
1792 if (!smmu->s2crs) in arm_smmu_device_cfg_probe()
1795 smmu->s2crs[i] = s2cr_init_val; in arm_smmu_device_cfg_probe()
1797 smmu->num_mapping_groups = size; in arm_smmu_device_cfg_probe()
1798 mutex_init(&smmu->stream_map_mutex); in arm_smmu_device_cfg_probe()
1799 spin_lock_init(&smmu->global_sync_lock); in arm_smmu_device_cfg_probe()
1801 if (smmu->version < ARM_SMMU_V2 || in arm_smmu_device_cfg_probe()
1803 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_L; in arm_smmu_device_cfg_probe()
1805 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH32_S; in arm_smmu_device_cfg_probe()
1809 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID1); in arm_smmu_device_cfg_probe()
1810 smmu->pgshift = (id & ARM_SMMU_ID1_PAGESIZE) ? 16 : 12; in arm_smmu_device_cfg_probe()
1812 /* Check for size mismatch of SMMU address space from mapped region */ in arm_smmu_device_cfg_probe()
1814 if (smmu->numpage != 2 * size << smmu->pgshift) in arm_smmu_device_cfg_probe()
1815 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1816 "SMMU address space size (0x%x) differs from mapped region size (0x%x)!\n", in arm_smmu_device_cfg_probe()
1817 2 * size << smmu->pgshift, smmu->numpage); in arm_smmu_device_cfg_probe()
1819 smmu->numpage = size; in arm_smmu_device_cfg_probe()
1821 smmu->num_s2_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMS2CB, id); in arm_smmu_device_cfg_probe()
1822 smmu->num_context_banks = FIELD_GET(ARM_SMMU_ID1_NUMCB, id); in arm_smmu_device_cfg_probe()
1823 if (smmu->num_s2_context_banks > smmu->num_context_banks) { in arm_smmu_device_cfg_probe()
1824 dev_err(smmu->dev, "impossible number of S2 context banks!\n"); in arm_smmu_device_cfg_probe()
1827 dev_notice(smmu->dev, "\t%u context banks (%u stage-2 only)\n", in arm_smmu_device_cfg_probe()
1828 smmu->num_context_banks, smmu->num_s2_context_banks); in arm_smmu_device_cfg_probe()
1829 smmu->cbs = devm_kcalloc(smmu->dev, smmu->num_context_banks, in arm_smmu_device_cfg_probe()
1830 sizeof(*smmu->cbs), GFP_KERNEL); in arm_smmu_device_cfg_probe()
1831 if (!smmu->cbs) in arm_smmu_device_cfg_probe()
1835 id = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_ID2); in arm_smmu_device_cfg_probe()
1837 smmu->ipa_size = size; in arm_smmu_device_cfg_probe()
1841 smmu->pa_size = size; in arm_smmu_device_cfg_probe()
1844 smmu->features |= ARM_SMMU_FEAT_VMID16; in arm_smmu_device_cfg_probe()
1851 if (dma_set_mask_and_coherent(smmu->dev, DMA_BIT_MASK(size))) in arm_smmu_device_cfg_probe()
1852 dev_warn(smmu->dev, in arm_smmu_device_cfg_probe()
1855 if (smmu->version < ARM_SMMU_V2) { in arm_smmu_device_cfg_probe()
1856 smmu->va_size = smmu->ipa_size; in arm_smmu_device_cfg_probe()
1857 if (smmu->version == ARM_SMMU_V1_64K) in arm_smmu_device_cfg_probe()
1858 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1861 smmu->va_size = arm_smmu_id_size_to_bits(size); in arm_smmu_device_cfg_probe()
1863 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_4K; in arm_smmu_device_cfg_probe()
1865 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_16K; in arm_smmu_device_cfg_probe()
1867 smmu->features |= ARM_SMMU_FEAT_FMT_AARCH64_64K; in arm_smmu_device_cfg_probe()
1870 if (smmu->impl && smmu->impl->cfg_probe) { in arm_smmu_device_cfg_probe()
1871 ret = smmu->impl->cfg_probe(smmu); in arm_smmu_device_cfg_probe()
1877 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH32_S) in arm_smmu_device_cfg_probe()
1878 smmu->pgsize_bitmap |= SZ_4K | SZ_64K | SZ_1M | SZ_16M; in arm_smmu_device_cfg_probe()
1879 if (smmu->features & in arm_smmu_device_cfg_probe()
1881 smmu->pgsize_bitmap |= SZ_4K | SZ_2M | SZ_1G; in arm_smmu_device_cfg_probe()
1882 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_16K) in arm_smmu_device_cfg_probe()
1883 smmu->pgsize_bitmap |= SZ_16K | SZ_32M; in arm_smmu_device_cfg_probe()
1884 if (smmu->features & ARM_SMMU_FEAT_FMT_AARCH64_64K) in arm_smmu_device_cfg_probe()
1885 smmu->pgsize_bitmap |= SZ_64K | SZ_512M; in arm_smmu_device_cfg_probe()
1888 arm_smmu_ops.pgsize_bitmap = smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1890 arm_smmu_ops.pgsize_bitmap |= smmu->pgsize_bitmap; in arm_smmu_device_cfg_probe()
1891 dev_notice(smmu->dev, "\tSupported page sizes: 0x%08lx\n", in arm_smmu_device_cfg_probe()
1892 smmu->pgsize_bitmap); in arm_smmu_device_cfg_probe()
1895 if (smmu->features & ARM_SMMU_FEAT_TRANS_S1) in arm_smmu_device_cfg_probe()
1896 dev_notice(smmu->dev, "\tStage-1: %lu-bit VA -> %lu-bit IPA\n", in arm_smmu_device_cfg_probe()
1897 smmu->va_size, smmu->ipa_size); in arm_smmu_device_cfg_probe()
1899 if (smmu->features & ARM_SMMU_FEAT_TRANS_S2) in arm_smmu_device_cfg_probe()
1900 dev_notice(smmu->dev, "\tStage-2: %lu-bit IPA -> %lu-bit PA\n", in arm_smmu_device_cfg_probe()
1901 smmu->ipa_size, smmu->pa_size); in arm_smmu_device_cfg_probe()
1922 { .compatible = "arm,smmu-v1", .data = &smmu_generic_v1 },
1923 { .compatible = "arm,smmu-v2", .data = &smmu_generic_v2 },
1927 { .compatible = "cavium,smmu-v2", .data = &cavium_smmuv2 },
1928 { .compatible = "nvidia,smmu-500", .data = &arm_mmu500 },
1929 { .compatible = "qcom,smmu-v2", .data = &qcom_smmuv2 },
1935 static int acpi_smmu_get_data(u32 model, struct arm_smmu_device *smmu) in acpi_smmu_get_data() argument
1942 smmu->version = ARM_SMMU_V1; in acpi_smmu_get_data()
1943 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1946 smmu->version = ARM_SMMU_V1_64K; in acpi_smmu_get_data()
1947 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1950 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1951 smmu->model = GENERIC_SMMU; in acpi_smmu_get_data()
1954 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1955 smmu->model = ARM_MMU500; in acpi_smmu_get_data()
1958 smmu->version = ARM_SMMU_V2; in acpi_smmu_get_data()
1959 smmu->model = CAVIUM_SMMUV2; in acpi_smmu_get_data()
1968 static int arm_smmu_device_acpi_probe(struct arm_smmu_device *smmu, in arm_smmu_device_acpi_probe() argument
1971 struct device *dev = smmu->dev; in arm_smmu_device_acpi_probe()
1980 ret = acpi_smmu_get_data(iort_smmu->model, smmu); in arm_smmu_device_acpi_probe()
1989 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_acpi_probe()
1994 static inline int arm_smmu_device_acpi_probe(struct arm_smmu_device *smmu, in arm_smmu_device_acpi_probe() argument
2001 static int arm_smmu_device_dt_probe(struct arm_smmu_device *smmu, in arm_smmu_device_dt_probe() argument
2005 struct device *dev = smmu->dev; in arm_smmu_device_dt_probe()
2014 smmu->version = data->version; in arm_smmu_device_dt_probe()
2015 smmu->model = data->model; in arm_smmu_device_dt_probe()
2021 IS_ENABLED(CONFIG_ARM_SMMU_LEGACY_DT_BINDINGS) ? "DMA API" : "SMMU"); in arm_smmu_device_dt_probe()
2032 smmu->features |= ARM_SMMU_FEAT_COHERENT_WALK; in arm_smmu_device_dt_probe()
2037 static void arm_smmu_rmr_install_bypass_smr(struct arm_smmu_device *smmu) in arm_smmu_rmr_install_bypass_smr() argument
2045 iort_get_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_smr()
2051 * SMMU until it gets enabled again in the reset routine. in arm_smmu_rmr_install_bypass_smr()
2053 reg = arm_smmu_gr0_read(smmu, ARM_SMMU_GR0_sCR0); in arm_smmu_rmr_install_bypass_smr()
2055 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, reg); in arm_smmu_rmr_install_bypass_smr()
2063 idx = arm_smmu_find_sme(smmu, rmr->sids[i], ~0); in arm_smmu_rmr_install_bypass_smr()
2067 if (smmu->s2crs[idx].count == 0) { in arm_smmu_rmr_install_bypass_smr()
2068 smmu->smrs[idx].id = rmr->sids[i]; in arm_smmu_rmr_install_bypass_smr()
2069 smmu->smrs[idx].mask = 0; in arm_smmu_rmr_install_bypass_smr()
2070 smmu->smrs[idx].valid = true; in arm_smmu_rmr_install_bypass_smr()
2072 smmu->s2crs[idx].count++; in arm_smmu_rmr_install_bypass_smr()
2073 smmu->s2crs[idx].type = S2CR_TYPE_BYPASS; in arm_smmu_rmr_install_bypass_smr()
2074 smmu->s2crs[idx].privcfg = S2CR_PRIVCFG_DEFAULT; in arm_smmu_rmr_install_bypass_smr()
2080 dev_notice(smmu->dev, "\tpreserved %d boot mapping%s\n", cnt, in arm_smmu_rmr_install_bypass_smr()
2082 iort_put_rmr_sids(dev_fwnode(smmu->dev), &rmr_list); in arm_smmu_rmr_install_bypass_smr()
2088 struct arm_smmu_device *smmu; in arm_smmu_device_probe() local
2094 smmu = devm_kzalloc(dev, sizeof(*smmu), GFP_KERNEL); in arm_smmu_device_probe()
2095 if (!smmu) { in arm_smmu_device_probe()
2099 smmu->dev = dev; in arm_smmu_device_probe()
2102 err = arm_smmu_device_dt_probe(smmu, &global_irqs, &pmu_irqs); in arm_smmu_device_probe()
2104 err = arm_smmu_device_acpi_probe(smmu, &global_irqs, &pmu_irqs); in arm_smmu_device_probe()
2108 smmu->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in arm_smmu_device_probe()
2109 if (IS_ERR(smmu->base)) in arm_smmu_device_probe()
2110 return PTR_ERR(smmu->base); in arm_smmu_device_probe()
2111 smmu->ioaddr = res->start; in arm_smmu_device_probe()
2117 smmu->numpage = resource_size(res); in arm_smmu_device_probe()
2119 smmu = arm_smmu_impl_init(smmu); in arm_smmu_device_probe()
2120 if (IS_ERR(smmu)) in arm_smmu_device_probe()
2121 return PTR_ERR(smmu); in arm_smmu_device_probe()
2125 smmu->num_context_irqs = num_irqs - global_irqs - pmu_irqs; in arm_smmu_device_probe()
2126 if (smmu->num_context_irqs <= 0) in arm_smmu_device_probe()
2131 smmu->irqs = devm_kcalloc(dev, smmu->num_context_irqs, in arm_smmu_device_probe()
2132 sizeof(*smmu->irqs), GFP_KERNEL); in arm_smmu_device_probe()
2133 if (!smmu->irqs) in arm_smmu_device_probe()
2135 smmu->num_context_irqs); in arm_smmu_device_probe()
2137 for (i = 0; i < smmu->num_context_irqs; i++) { in arm_smmu_device_probe()
2142 smmu->irqs[i] = irq; in arm_smmu_device_probe()
2145 err = devm_clk_bulk_get_all(dev, &smmu->clks); in arm_smmu_device_probe()
2150 smmu->num_clks = err; in arm_smmu_device_probe()
2152 err = clk_bulk_prepare_enable(smmu->num_clks, smmu->clks); in arm_smmu_device_probe()
2156 err = arm_smmu_device_cfg_probe(smmu); in arm_smmu_device_probe()
2160 if (smmu->version == ARM_SMMU_V2) { in arm_smmu_device_probe()
2161 if (smmu->num_context_banks > smmu->num_context_irqs) { in arm_smmu_device_probe()
2164 smmu->num_context_irqs, smmu->num_context_banks); in arm_smmu_device_probe()
2169 smmu->num_context_irqs = smmu->num_context_banks; in arm_smmu_device_probe()
2172 if (smmu->impl && smmu->impl->global_fault) in arm_smmu_device_probe()
2173 global_fault = smmu->impl->global_fault; in arm_smmu_device_probe()
2184 "arm-smmu global fault", smmu); in arm_smmu_device_probe()
2191 err = iommu_device_sysfs_add(&smmu->iommu, smmu->dev, NULL, in arm_smmu_device_probe()
2192 "smmu.%pa", &smmu->ioaddr); in arm_smmu_device_probe()
2198 err = iommu_device_register(&smmu->iommu, &arm_smmu_ops, in arm_smmu_device_probe()
2202 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_probe()
2206 platform_set_drvdata(pdev, smmu); in arm_smmu_device_probe()
2209 arm_smmu_rmr_install_bypass_smr(smmu); in arm_smmu_device_probe()
2211 arm_smmu_device_reset(smmu); in arm_smmu_device_probe()
2212 arm_smmu_test_smr_masks(smmu); in arm_smmu_device_probe()
2230 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_shutdown() local
2232 if (!bitmap_empty(smmu->context_map, ARM_SMMU_MAX_CBS)) in arm_smmu_device_shutdown()
2235 arm_smmu_rpm_get(smmu); in arm_smmu_device_shutdown()
2237 arm_smmu_gr0_write(smmu, ARM_SMMU_GR0_sCR0, ARM_SMMU_sCR0_CLIENTPD); in arm_smmu_device_shutdown()
2238 arm_smmu_rpm_put(smmu); in arm_smmu_device_shutdown()
2240 if (pm_runtime_enabled(smmu->dev)) in arm_smmu_device_shutdown()
2241 pm_runtime_force_suspend(smmu->dev); in arm_smmu_device_shutdown()
2243 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_device_shutdown()
2245 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_device_shutdown()
2250 struct arm_smmu_device *smmu = platform_get_drvdata(pdev); in arm_smmu_device_remove() local
2252 iommu_device_unregister(&smmu->iommu); in arm_smmu_device_remove()
2253 iommu_device_sysfs_remove(&smmu->iommu); in arm_smmu_device_remove()
2260 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_resume() local
2263 ret = clk_bulk_enable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_resume()
2267 arm_smmu_device_reset(smmu); in arm_smmu_runtime_resume()
2274 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_runtime_suspend() local
2276 clk_bulk_disable(smmu->num_clks, smmu->clks); in arm_smmu_runtime_suspend()
2284 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_pm_resume() local
2286 ret = clk_bulk_prepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_resume()
2295 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_resume()
2303 struct arm_smmu_device *smmu = dev_get_drvdata(dev); in arm_smmu_pm_suspend() local
2313 clk_bulk_unprepare(smmu->num_clks, smmu->clks); in arm_smmu_pm_suspend()
2325 .name = "arm-smmu",
2336 MODULE_DESCRIPTION("IOMMU API for ARM architected SMMU implementations");
2338 MODULE_ALIAS("platform:arm-smmu");