Lines Matching full:iommu
20 #include <linux/amd-iommu.h>
26 #include <asm/iommu.h>
97 * structure describing one IOMMU in the ACPI table. Typically followed by one
117 * A device entry describing which devices a specific IOMMU translates and
135 * An AMD IOMMU memory definition structure. It defines things like exclusion
194 * AMD IOMMU allows up to 2^16 different protection domains. This is a bitmap
234 bool translation_pre_enabled(struct amd_iommu *iommu) in translation_pre_enabled() argument
236 return (iommu->flags & AMD_IOMMU_FLAG_TRANS_PRE_ENABLED); in translation_pre_enabled()
239 static void clear_translation_pre_enabled(struct amd_iommu *iommu) in clear_translation_pre_enabled() argument
241 iommu->flags &= ~AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in clear_translation_pre_enabled()
244 static void init_translation_status(struct amd_iommu *iommu) in init_translation_status() argument
248 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in init_translation_status()
250 iommu->flags |= AMD_IOMMU_FLAG_TRANS_PRE_ENABLED; in init_translation_status()
272 struct amd_iommu *iommu; in get_global_efr() local
274 for_each_iommu(iommu) { in get_global_efr()
275 u64 tmp = iommu->features; in get_global_efr()
276 u64 tmp2 = iommu->features2; in get_global_efr()
278 if (list_is_first(&iommu->list, &amd_iommu_list)) { in get_global_efr()
289 …"Found inconsistent EFR/EFR2 %#llx,%#llx (global %#llx,%#llx) on iommu%d (%04x:%02x:%02x.%01x).\n", in get_global_efr()
291 iommu->index, iommu->pci_seg->id, in get_global_efr()
292 PCI_BUS_NUM(iommu->devid), PCI_SLOT(iommu->devid), in get_global_efr()
293 PCI_FUNC(iommu->devid)); in get_global_efr()
307 static void __init early_iommu_features_init(struct amd_iommu *iommu, in early_iommu_features_init() argument
311 iommu->features = h->efr_reg; in early_iommu_features_init()
312 iommu->features2 = h->efr_reg2; in early_iommu_features_init()
320 static u32 iommu_read_l1(struct amd_iommu *iommu, u16 l1, u8 address) in iommu_read_l1() argument
324 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_read_l1()
325 pci_read_config_dword(iommu->dev, 0xfc, &val); in iommu_read_l1()
329 static void iommu_write_l1(struct amd_iommu *iommu, u16 l1, u8 address, u32 val) in iommu_write_l1() argument
331 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16 | 1 << 31)); in iommu_write_l1()
332 pci_write_config_dword(iommu->dev, 0xfc, val); in iommu_write_l1()
333 pci_write_config_dword(iommu->dev, 0xf8, (address | l1 << 16)); in iommu_write_l1()
336 static u32 iommu_read_l2(struct amd_iommu *iommu, u8 address) in iommu_read_l2() argument
340 pci_write_config_dword(iommu->dev, 0xf0, address); in iommu_read_l2()
341 pci_read_config_dword(iommu->dev, 0xf4, &val); in iommu_read_l2()
345 static void iommu_write_l2(struct amd_iommu *iommu, u8 address, u32 val) in iommu_write_l2() argument
347 pci_write_config_dword(iommu->dev, 0xf0, (address | 1 << 8)); in iommu_write_l2()
348 pci_write_config_dword(iommu->dev, 0xf4, val); in iommu_write_l2()
353 * AMD IOMMU MMIO register space handling functions
355 * These functions are used to program the IOMMU device registers in
361 * This function set the exclusion range in the IOMMU. DMA accesses to the
364 static void iommu_set_exclusion_range(struct amd_iommu *iommu) in iommu_set_exclusion_range() argument
366 u64 start = iommu->exclusion_start & PAGE_MASK; in iommu_set_exclusion_range()
367 u64 limit = (start + iommu->exclusion_length - 1) & PAGE_MASK; in iommu_set_exclusion_range()
370 if (!iommu->exclusion_start) in iommu_set_exclusion_range()
374 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_exclusion_range()
378 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_exclusion_range()
382 static void iommu_set_cwwb_range(struct amd_iommu *iommu) in iommu_set_cwwb_range() argument
384 u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem); in iommu_set_cwwb_range()
394 memcpy_toio(iommu->mmio_base + MMIO_EXCL_BASE_OFFSET, in iommu_set_cwwb_range()
401 memcpy_toio(iommu->mmio_base + MMIO_EXCL_LIMIT_OFFSET, in iommu_set_cwwb_range()
405 /* Programs the physical address of the device table into the IOMMU hardware */
406 static void iommu_set_device_table(struct amd_iommu *iommu) in iommu_set_device_table() argument
409 u32 dev_table_size = iommu->pci_seg->dev_table_size; in iommu_set_device_table()
410 void *dev_table = (void *)get_dev_table(iommu); in iommu_set_device_table()
412 BUG_ON(iommu->mmio_base == NULL); in iommu_set_device_table()
416 memcpy_toio(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET, in iommu_set_device_table()
420 /* Generic functions to enable/disable certain features of the IOMMU. */
421 static void iommu_feature_enable(struct amd_iommu *iommu, u8 bit) in iommu_feature_enable() argument
425 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
427 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_enable()
430 static void iommu_feature_disable(struct amd_iommu *iommu, u8 bit) in iommu_feature_disable() argument
434 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
436 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_feature_disable()
439 static void iommu_set_inv_tlb_timeout(struct amd_iommu *iommu, int timeout) in iommu_set_inv_tlb_timeout() argument
443 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
446 writeq(ctrl, iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_set_inv_tlb_timeout()
450 static void iommu_enable(struct amd_iommu *iommu) in iommu_enable() argument
452 iommu_feature_enable(iommu, CONTROL_IOMMU_EN); in iommu_enable()
455 static void iommu_disable(struct amd_iommu *iommu) in iommu_disable() argument
457 if (!iommu->mmio_base) in iommu_disable()
461 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable()
464 iommu_feature_disable(iommu, CONTROL_EVT_INT_EN); in iommu_disable()
465 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable()
467 /* Disable IOMMU GA_LOG */ in iommu_disable()
468 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in iommu_disable()
469 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in iommu_disable()
471 /* Disable IOMMU PPR logging */ in iommu_disable()
472 iommu_feature_disable(iommu, CONTROL_PPRLOG_EN); in iommu_disable()
473 iommu_feature_disable(iommu, CONTROL_PPRINT_EN); in iommu_disable()
475 /* Disable IOMMU hardware itself */ in iommu_disable()
476 iommu_feature_disable(iommu, CONTROL_IOMMU_EN); in iommu_disable()
479 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); in iommu_disable()
483 * mapping and unmapping functions for the IOMMU MMIO space. Each AMD IOMMU in
498 static void __init iommu_unmap_mmio_space(struct amd_iommu *iommu) in iommu_unmap_mmio_space() argument
500 if (iommu->mmio_base) in iommu_unmap_mmio_space()
501 iounmap(iommu->mmio_base); in iommu_unmap_mmio_space()
502 release_mem_region(iommu->mmio_phys, iommu->mmio_phys_end); in iommu_unmap_mmio_space()
523 * The functions below belong to the first pass of AMD IOMMU ACPI table
547 * After reading the highest device id from the IOMMU PCI capability header
642 * the second time. In this ACPI parsing iteration we allocate IOMMU specific
666 /* Allocate per PCI segment IOMMU rlookup table. */
732 * Allocates the command buffer. This buffer is per AMD IOMMU. We can
733 * write commands to that buffer later and the IOMMU will execute them
736 static int __init alloc_command_buffer(struct amd_iommu *iommu) in alloc_command_buffer() argument
738 iommu->cmd_buf = (void *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in alloc_command_buffer()
741 return iommu->cmd_buf ? 0 : -ENOMEM; in alloc_command_buffer()
748 static void amd_iommu_restart_log(struct amd_iommu *iommu, const char *evt_type, in amd_iommu_restart_log() argument
754 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
758 pr_info_ratelimited("IOMMU %s log restarting\n", evt_type); in amd_iommu_restart_log()
760 iommu_feature_disable(iommu, cntrl_log); in amd_iommu_restart_log()
761 iommu_feature_disable(iommu, cntrl_intr); in amd_iommu_restart_log()
763 writel(status_overflow_mask, iommu->mmio_base + MMIO_STATUS_OFFSET); in amd_iommu_restart_log()
765 iommu_feature_enable(iommu, cntrl_intr); in amd_iommu_restart_log()
766 iommu_feature_enable(iommu, cntrl_log); in amd_iommu_restart_log()
770 * This function restarts event logging in case the IOMMU experienced
773 void amd_iommu_restart_event_logging(struct amd_iommu *iommu) in amd_iommu_restart_event_logging() argument
775 amd_iommu_restart_log(iommu, "Event", CONTROL_EVT_INT_EN, in amd_iommu_restart_event_logging()
781 * This function restarts event logging in case the IOMMU experienced
784 void amd_iommu_restart_ga_log(struct amd_iommu *iommu) in amd_iommu_restart_ga_log() argument
786 amd_iommu_restart_log(iommu, "GA", CONTROL_GAINT_EN, in amd_iommu_restart_ga_log()
792 * This function restarts ppr logging in case the IOMMU experienced
795 void amd_iommu_restart_ppr_log(struct amd_iommu *iommu) in amd_iommu_restart_ppr_log() argument
797 amd_iommu_restart_log(iommu, "PPR", CONTROL_PPRINT_EN, in amd_iommu_restart_ppr_log()
803 * This function resets the command buffer if the IOMMU stopped fetching
806 static void amd_iommu_reset_cmd_buffer(struct amd_iommu *iommu) in amd_iommu_reset_cmd_buffer() argument
808 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
810 writel(0x00, iommu->mmio_base + MMIO_CMD_HEAD_OFFSET); in amd_iommu_reset_cmd_buffer()
811 writel(0x00, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET); in amd_iommu_reset_cmd_buffer()
812 iommu->cmd_buf_head = 0; in amd_iommu_reset_cmd_buffer()
813 iommu->cmd_buf_tail = 0; in amd_iommu_reset_cmd_buffer()
815 iommu_feature_enable(iommu, CONTROL_CMDBUF_EN); in amd_iommu_reset_cmd_buffer()
822 static void iommu_enable_command_buffer(struct amd_iommu *iommu) in iommu_enable_command_buffer() argument
826 BUG_ON(iommu->cmd_buf == NULL); in iommu_enable_command_buffer()
828 entry = iommu_virt_to_phys(iommu->cmd_buf); in iommu_enable_command_buffer()
831 memcpy_toio(iommu->mmio_base + MMIO_CMD_BUF_OFFSET, in iommu_enable_command_buffer()
834 amd_iommu_reset_cmd_buffer(iommu); in iommu_enable_command_buffer()
840 static void iommu_disable_command_buffer(struct amd_iommu *iommu) in iommu_disable_command_buffer() argument
842 iommu_feature_disable(iommu, CONTROL_CMDBUF_EN); in iommu_disable_command_buffer()
845 static void __init free_command_buffer(struct amd_iommu *iommu) in free_command_buffer() argument
847 free_pages((unsigned long)iommu->cmd_buf, get_order(CMD_BUFFER_SIZE)); in free_command_buffer()
850 static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu, in iommu_alloc_4k_pages() argument
866 /* allocates the memory where the IOMMU will log its events to */
867 static int __init alloc_event_buffer(struct amd_iommu *iommu) in alloc_event_buffer() argument
869 iommu->evt_buf = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_event_buffer()
872 return iommu->evt_buf ? 0 : -ENOMEM; in alloc_event_buffer()
875 static void iommu_enable_event_buffer(struct amd_iommu *iommu) in iommu_enable_event_buffer() argument
879 BUG_ON(iommu->evt_buf == NULL); in iommu_enable_event_buffer()
881 entry = iommu_virt_to_phys(iommu->evt_buf) | EVT_LEN_MASK; in iommu_enable_event_buffer()
883 memcpy_toio(iommu->mmio_base + MMIO_EVT_BUF_OFFSET, in iommu_enable_event_buffer()
887 writel(0x00, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET); in iommu_enable_event_buffer()
888 writel(0x00, iommu->mmio_base + MMIO_EVT_TAIL_OFFSET); in iommu_enable_event_buffer()
890 iommu_feature_enable(iommu, CONTROL_EVT_LOG_EN); in iommu_enable_event_buffer()
896 static void iommu_disable_event_buffer(struct amd_iommu *iommu) in iommu_disable_event_buffer() argument
898 iommu_feature_disable(iommu, CONTROL_EVT_LOG_EN); in iommu_disable_event_buffer()
901 static void __init free_event_buffer(struct amd_iommu *iommu) in free_event_buffer() argument
903 free_pages((unsigned long)iommu->evt_buf, get_order(EVT_BUFFER_SIZE)); in free_event_buffer()
906 /* allocates the memory where the IOMMU will log its events to */
907 static int __init alloc_ppr_log(struct amd_iommu *iommu) in alloc_ppr_log() argument
909 iommu->ppr_log = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, in alloc_ppr_log()
912 return iommu->ppr_log ? 0 : -ENOMEM; in alloc_ppr_log()
915 static void iommu_enable_ppr_log(struct amd_iommu *iommu) in iommu_enable_ppr_log() argument
919 if (iommu->ppr_log == NULL) in iommu_enable_ppr_log()
922 iommu_feature_enable(iommu, CONTROL_PPR_EN); in iommu_enable_ppr_log()
924 entry = iommu_virt_to_phys(iommu->ppr_log) | PPR_LOG_SIZE_512; in iommu_enable_ppr_log()
926 memcpy_toio(iommu->mmio_base + MMIO_PPR_LOG_OFFSET, in iommu_enable_ppr_log()
930 writel(0x00, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET); in iommu_enable_ppr_log()
931 writel(0x00, iommu->mmio_base + MMIO_PPR_TAIL_OFFSET); in iommu_enable_ppr_log()
933 iommu_feature_enable(iommu, CONTROL_PPRLOG_EN); in iommu_enable_ppr_log()
934 iommu_feature_enable(iommu, CONTROL_PPRINT_EN); in iommu_enable_ppr_log()
937 static void __init free_ppr_log(struct amd_iommu *iommu) in free_ppr_log() argument
939 free_pages((unsigned long)iommu->ppr_log, get_order(PPR_LOG_SIZE)); in free_ppr_log()
942 static void free_ga_log(struct amd_iommu *iommu) in free_ga_log() argument
945 free_pages((unsigned long)iommu->ga_log, get_order(GA_LOG_SIZE)); in free_ga_log()
946 free_pages((unsigned long)iommu->ga_log_tail, get_order(8)); in free_ga_log()
951 static int iommu_ga_log_enable(struct amd_iommu *iommu) in iommu_ga_log_enable() argument
956 if (!iommu->ga_log) in iommu_ga_log_enable()
959 entry = iommu_virt_to_phys(iommu->ga_log) | GA_LOG_SIZE_512; in iommu_ga_log_enable()
960 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_BASE_OFFSET, in iommu_ga_log_enable()
962 entry = (iommu_virt_to_phys(iommu->ga_log_tail) & in iommu_ga_log_enable()
964 memcpy_toio(iommu->mmio_base + MMIO_GA_LOG_TAIL_OFFSET, in iommu_ga_log_enable()
966 writel(0x00, iommu->mmio_base + MMIO_GA_HEAD_OFFSET); in iommu_ga_log_enable()
967 writel(0x00, iommu->mmio_base + MMIO_GA_TAIL_OFFSET); in iommu_ga_log_enable()
970 iommu_feature_enable(iommu, CONTROL_GAINT_EN); in iommu_ga_log_enable()
971 iommu_feature_enable(iommu, CONTROL_GALOG_EN); in iommu_ga_log_enable()
974 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in iommu_ga_log_enable()
986 static int iommu_init_ga_log(struct amd_iommu *iommu) in iommu_init_ga_log() argument
991 iommu->ga_log = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
993 if (!iommu->ga_log) in iommu_init_ga_log()
996 iommu->ga_log_tail = (u8 *)__get_free_pages(GFP_KERNEL | __GFP_ZERO, in iommu_init_ga_log()
998 if (!iommu->ga_log_tail) in iommu_init_ga_log()
1003 free_ga_log(iommu); in iommu_init_ga_log()
1008 static int __init alloc_cwwb_sem(struct amd_iommu *iommu) in alloc_cwwb_sem() argument
1010 iommu->cmd_sem = iommu_alloc_4k_pages(iommu, GFP_KERNEL | __GFP_ZERO, 1); in alloc_cwwb_sem()
1012 return iommu->cmd_sem ? 0 : -ENOMEM; in alloc_cwwb_sem()
1015 static void __init free_cwwb_sem(struct amd_iommu *iommu) in free_cwwb_sem() argument
1017 if (iommu->cmd_sem) in free_cwwb_sem()
1018 free_page((unsigned long)iommu->cmd_sem); in free_cwwb_sem()
1021 static void iommu_enable_xt(struct amd_iommu *iommu) in iommu_enable_xt() argument
1030 iommu_feature_enable(iommu, CONTROL_XT_EN); in iommu_enable_xt()
1034 static void iommu_enable_gt(struct amd_iommu *iommu) in iommu_enable_gt() argument
1039 iommu_feature_enable(iommu, CONTROL_GT_EN); in iommu_enable_gt()
1052 static void set_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) in set_dev_entry_bit() argument
1054 struct dev_table_entry *dev_table = get_dev_table(iommu); in set_dev_entry_bit()
1068 static int get_dev_entry_bit(struct amd_iommu *iommu, u16 devid, u8 bit) in get_dev_entry_bit() argument
1070 struct dev_table_entry *dev_table = get_dev_table(iommu); in get_dev_entry_bit()
1075 static bool __copy_device_table(struct amd_iommu *iommu) in __copy_device_table() argument
1078 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in __copy_device_table()
1086 /* Each IOMMU use separate device table with the same size */ in __copy_device_table()
1087 lo = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET); in __copy_device_table()
1088 hi = readl(iommu->mmio_base + MMIO_DEV_TABLE_OFFSET + 4); in __copy_device_table()
1093 pr_err("The device table size of IOMMU:%d is not expected!\n", in __copy_device_table()
1094 iommu->index); in __copy_device_table()
1167 struct amd_iommu *iommu; in copy_device_table() local
1180 for_each_iommu(iommu) { in copy_device_table()
1181 if (pci_seg->id != iommu->pci_seg->id) in copy_device_table()
1183 if (!__copy_device_table(iommu)) in copy_device_table()
1192 void amd_iommu_apply_erratum_63(struct amd_iommu *iommu, u16 devid) in amd_iommu_apply_erratum_63() argument
1196 sysmgt = get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1) | in amd_iommu_apply_erratum_63()
1197 (get_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2) << 1); in amd_iommu_apply_erratum_63()
1200 set_dev_entry_bit(iommu, devid, DEV_ENTRY_IW); in amd_iommu_apply_erratum_63()
1207 static void __init set_dev_entry_from_acpi(struct amd_iommu *iommu, in set_dev_entry_from_acpi() argument
1211 set_dev_entry_bit(iommu, devid, DEV_ENTRY_INIT_PASS); in set_dev_entry_from_acpi()
1213 set_dev_entry_bit(iommu, devid, DEV_ENTRY_EINT_PASS); in set_dev_entry_from_acpi()
1215 set_dev_entry_bit(iommu, devid, DEV_ENTRY_NMI_PASS); in set_dev_entry_from_acpi()
1217 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT1); in set_dev_entry_from_acpi()
1219 set_dev_entry_bit(iommu, devid, DEV_ENTRY_SYSMGT2); in set_dev_entry_from_acpi()
1221 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT0_PASS); in set_dev_entry_from_acpi()
1223 set_dev_entry_bit(iommu, devid, DEV_ENTRY_LINT1_PASS); in set_dev_entry_from_acpi()
1225 amd_iommu_apply_erratum_63(iommu, devid); in set_dev_entry_from_acpi()
1227 amd_iommu_set_rlookup_table(iommu, devid); in set_dev_entry_from_acpi()
1338 * Takes a pointer to an AMD IOMMU entry in the ACPI table and
1341 static int __init init_iommu_from_acpi(struct amd_iommu *iommu, in init_iommu_from_acpi() argument
1350 struct amd_iommu_pci_seg *pci_seg = iommu->pci_seg; in init_iommu_from_acpi()
1364 iommu->acpi_flags = h->flags; in init_iommu_from_acpi()
1390 set_dev_entry_from_acpi(iommu, dev_i, e->flags, 0); in init_iommu_from_acpi()
1402 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1432 set_dev_entry_from_acpi(iommu, devid , e->flags, 0); in init_iommu_from_acpi()
1433 set_dev_entry_from_acpi(iommu, devid_to, e->flags, 0); in init_iommu_from_acpi()
1465 set_dev_entry_from_acpi(iommu, devid, e->flags, in init_iommu_from_acpi()
1493 set_dev_entry_from_acpi(iommu, in init_iommu_from_acpi()
1496 set_dev_entry_from_acpi(iommu, dev_i, in init_iommu_from_acpi()
1532 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1598 set_dev_entry_from_acpi(iommu, devid, e->flags, 0); in init_iommu_from_acpi()
1680 static void __init free_iommu_one(struct amd_iommu *iommu) in free_iommu_one() argument
1682 free_cwwb_sem(iommu); in free_iommu_one()
1683 free_command_buffer(iommu); in free_iommu_one()
1684 free_event_buffer(iommu); in free_iommu_one()
1685 free_ppr_log(iommu); in free_iommu_one()
1686 free_ga_log(iommu); in free_iommu_one()
1687 iommu_unmap_mmio_space(iommu); in free_iommu_one()
1692 struct amd_iommu *iommu, *next; in free_iommu_all() local
1694 for_each_iommu_safe(iommu, next) { in free_iommu_all()
1695 list_del(&iommu->list); in free_iommu_all()
1696 free_iommu_one(iommu); in free_iommu_all()
1697 kfree(iommu); in free_iommu_all()
1702 * Family15h Model 10h-1fh erratum 746 (IOMMU Logging May Stall Translations)
1707 static void amd_iommu_erratum_746_workaround(struct amd_iommu *iommu) in amd_iommu_erratum_746_workaround() argument
1716 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1717 pci_read_config_dword(iommu->dev, 0xf4, &value); in amd_iommu_erratum_746_workaround()
1723 pci_write_config_dword(iommu->dev, 0xf0, 0x90 | (1 << 8)); in amd_iommu_erratum_746_workaround()
1725 pci_write_config_dword(iommu->dev, 0xf4, value | 0x4); in amd_iommu_erratum_746_workaround()
1726 pci_info(iommu->dev, "Applying erratum 746 workaround\n"); in amd_iommu_erratum_746_workaround()
1729 pci_write_config_dword(iommu->dev, 0xf0, 0x90); in amd_iommu_erratum_746_workaround()
1733 * Family15h Model 30h-3fh (IOMMU Mishandles ATS Write Permission)
1738 static void amd_iommu_ats_write_check_workaround(struct amd_iommu *iommu) in amd_iommu_ats_write_check_workaround() argument
1748 value = iommu_read_l2(iommu, 0x47); in amd_iommu_ats_write_check_workaround()
1754 iommu_write_l2(iommu, 0x47, value | BIT(0)); in amd_iommu_ats_write_check_workaround()
1756 pci_info(iommu->dev, "Applying ATS write check workaround\n"); in amd_iommu_ats_write_check_workaround()
1760 * This function glues the initialization function for one IOMMU
1762 * hardware. It does NOT enable the IOMMU. This is done afterwards.
1764 static int __init init_iommu_one(struct amd_iommu *iommu, struct ivhd_header *h, in init_iommu_one() argument
1772 iommu->pci_seg = pci_seg; in init_iommu_one()
1774 raw_spin_lock_init(&iommu->lock); in init_iommu_one()
1775 atomic64_set(&iommu->cmd_sem_val, 0); in init_iommu_one()
1777 /* Add IOMMU to internal data structures */ in init_iommu_one()
1778 list_add_tail(&iommu->list, &amd_iommu_list); in init_iommu_one()
1779 iommu->index = amd_iommus_present++; in init_iommu_one()
1781 if (unlikely(iommu->index >= MAX_IOMMUS)) { in init_iommu_one()
1786 /* Index is fine - add IOMMU to the array */ in init_iommu_one()
1787 amd_iommus[iommu->index] = iommu; in init_iommu_one()
1790 * Copy data from ACPI table entry to the iommu struct in init_iommu_one()
1792 iommu->devid = h->devid; in init_iommu_one()
1793 iommu->cap_ptr = h->cap_ptr; in init_iommu_one()
1794 iommu->mmio_phys = h->mmio_phys; in init_iommu_one()
1802 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1804 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1818 iommu->mmio_phys_end = MMIO_REG_END_OFFSET; in init_iommu_one()
1820 iommu->mmio_phys_end = MMIO_CNTR_CONF_OFFSET; in init_iommu_one()
1836 early_iommu_features_init(iommu, h); in init_iommu_one()
1843 iommu->mmio_base = iommu_map_mmio_space(iommu->mmio_phys, in init_iommu_one()
1844 iommu->mmio_phys_end); in init_iommu_one()
1845 if (!iommu->mmio_base) in init_iommu_one()
1848 return init_iommu_from_acpi(iommu, h); in init_iommu_one()
1851 static int __init init_iommu_one_late(struct amd_iommu *iommu) in init_iommu_one_late() argument
1855 if (alloc_cwwb_sem(iommu)) in init_iommu_one_late()
1858 if (alloc_command_buffer(iommu)) in init_iommu_one_late()
1861 if (alloc_event_buffer(iommu)) in init_iommu_one_late()
1864 iommu->int_enabled = false; in init_iommu_one_late()
1866 init_translation_status(iommu); in init_iommu_one_late()
1867 if (translation_pre_enabled(iommu) && !is_kdump_kernel()) { in init_iommu_one_late()
1868 iommu_disable(iommu); in init_iommu_one_late()
1869 clear_translation_pre_enabled(iommu); in init_iommu_one_late()
1870 pr_warn("Translation was enabled for IOMMU:%d but we are not in kdump mode\n", in init_iommu_one_late()
1871 iommu->index); in init_iommu_one_late()
1874 amd_iommu_pre_enabled = translation_pre_enabled(iommu); in init_iommu_one_late()
1877 ret = amd_iommu_create_irq_domain(iommu); in init_iommu_one_late()
1883 * Make sure IOMMU is not considered to translate itself. The IVRS in init_iommu_one_late()
1886 iommu->pci_seg->rlookup_table[iommu->devid] = NULL; in init_iommu_one_late()
1918 * Iterates over all IOMMU entries in the ACPI table, allocates the
1919 * IOMMU structure and initializes it with init_iommu_one()
1925 struct amd_iommu *iommu; in init_iommu_all() local
1944 iommu = kzalloc(sizeof(struct amd_iommu), GFP_KERNEL); in init_iommu_all()
1945 if (iommu == NULL) in init_iommu_all()
1948 ret = init_iommu_one(iommu, h, table); in init_iommu_all()
1960 /* Phase 3 : Enabling IOMMU features */ in init_iommu_all()
1961 for_each_iommu(iommu) { in init_iommu_all()
1962 ret = init_iommu_one_late(iommu); in init_iommu_all()
1970 static void init_iommu_perf_ctr(struct amd_iommu *iommu) in init_iommu_perf_ctr() argument
1973 struct pci_dev *pdev = iommu->dev; in init_iommu_perf_ctr()
1980 pci_info(pdev, "IOMMU performance counters supported\n"); in init_iommu_perf_ctr()
1982 val = readl(iommu->mmio_base + MMIO_CNTR_CONF_OFFSET); in init_iommu_perf_ctr()
1983 iommu->max_banks = (u8) ((val >> 12) & 0x3f); in init_iommu_perf_ctr()
1984 iommu->max_counters = (u8) ((val >> 7) & 0xf); in init_iommu_perf_ctr()
1993 struct amd_iommu *iommu = dev_to_amd_iommu(dev); in amd_iommu_show_cap() local
1994 return sysfs_emit(buf, "%x\n", iommu->cap); in amd_iommu_show_cap()
2013 .name = "amd-iommu",
2024 * of the IOMMU Extended Feature Register [MMIO Offset 0030h].
2027 static void __init late_iommu_features_init(struct amd_iommu *iommu) in late_iommu_features_init() argument
2031 if (!(iommu->cap & (1 << IOMMU_CAP_EFR))) in late_iommu_features_init()
2035 features = readq(iommu->mmio_base + MMIO_EXT_FEATURES); in late_iommu_features_init()
2036 features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2); in late_iommu_features_init()
2057 static int __init iommu_init_pci(struct amd_iommu *iommu) in iommu_init_pci() argument
2059 int cap_ptr = iommu->cap_ptr; in iommu_init_pci()
2062 iommu->dev = pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2063 PCI_BUS_NUM(iommu->devid), in iommu_init_pci()
2064 iommu->devid & 0xff); in iommu_init_pci()
2065 if (!iommu->dev) in iommu_init_pci()
2068 /* Prevent binding other PCI device drivers to IOMMU devices */ in iommu_init_pci()
2069 iommu->dev->match_driver = false; in iommu_init_pci()
2071 pci_read_config_dword(iommu->dev, cap_ptr + MMIO_CAP_HDR_OFFSET, in iommu_init_pci()
2072 &iommu->cap); in iommu_init_pci()
2074 if (!(iommu->cap & (1 << IOMMU_CAP_IOTLB))) in iommu_init_pci()
2077 late_iommu_features_init(iommu); in iommu_init_pci()
2085 iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1; in iommu_init_pci()
2087 BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK); in iommu_init_pci()
2098 if (check_feature(FEATURE_PPR) && alloc_ppr_log(iommu)) in iommu_init_pci()
2101 if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) { in iommu_init_pci()
2107 init_iommu_perf_ctr(iommu); in iommu_init_pci()
2117 if (is_rd890_iommu(iommu->dev)) { in iommu_init_pci()
2120 iommu->root_pdev = in iommu_init_pci()
2121 pci_get_domain_bus_and_slot(iommu->pci_seg->id, in iommu_init_pci()
2122 iommu->dev->bus->number, in iommu_init_pci()
2130 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_init_pci()
2131 &iommu->stored_addr_lo); in iommu_init_pci()
2132 pci_read_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_init_pci()
2133 &iommu->stored_addr_hi); in iommu_init_pci()
2136 iommu->stored_addr_lo &= ~1; in iommu_init_pci()
2140 iommu->stored_l1[i][j] = iommu_read_l1(iommu, i, j); in iommu_init_pci()
2143 iommu->stored_l2[i] = iommu_read_l2(iommu, i); in iommu_init_pci()
2146 amd_iommu_erratum_746_workaround(iommu); in iommu_init_pci()
2147 amd_iommu_ats_write_check_workaround(iommu); in iommu_init_pci()
2149 ret = iommu_device_sysfs_add(&iommu->iommu, &iommu->dev->dev, in iommu_init_pci()
2150 amd_iommu_groups, "ivhd%d", iommu->index); in iommu_init_pci()
2154 iommu_device_register(&iommu->iommu, &amd_iommu_ops, NULL); in iommu_init_pci()
2156 return pci_enable_device(iommu->dev); in iommu_init_pci()
2197 struct amd_iommu *iommu; in amd_iommu_init_pci() local
2201 for_each_iommu(iommu) { in amd_iommu_init_pci()
2202 ret = iommu_init_pci(iommu); in amd_iommu_init_pci()
2204 pr_err("IOMMU%d: Failed to initialize IOMMU Hardware (error=%d)!\n", in amd_iommu_init_pci()
2205 iommu->index, ret); in amd_iommu_init_pci()
2209 iommu_set_cwwb_range(iommu); in amd_iommu_init_pci()
2225 for_each_iommu(iommu) in amd_iommu_init_pci()
2226 amd_iommu_flush_all_caches(iommu); in amd_iommu_init_pci()
2243 static int iommu_setup_msi(struct amd_iommu *iommu) in iommu_setup_msi() argument
2247 r = pci_enable_msi(iommu->dev); in iommu_setup_msi()
2251 r = request_threaded_irq(iommu->dev->irq, in iommu_setup_msi()
2255 iommu); in iommu_setup_msi()
2258 pci_disable_msi(iommu->dev); in iommu_setup_msi()
2327 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_unmask_irq() local
2337 writeq(xt.capxt, iommu->mmio_base + irqd->hwirq); in intcapxt_unmask_irq()
2342 struct amd_iommu *iommu = irqd->chip_data; in intcapxt_mask_irq() local
2344 writeq(0, iommu->mmio_base + irqd->hwirq); in intcapxt_mask_irq()
2366 .name = "IOMMU-MSI",
2407 static int __iommu_setup_intcapxt(struct amd_iommu *iommu, const char *devname, in __iommu_setup_intcapxt() argument
2413 int node = dev_to_node(&iommu->dev->dev); in __iommu_setup_intcapxt()
2421 info.data = iommu; in __iommu_setup_intcapxt()
2431 thread_fn, 0, devname, iommu); in __iommu_setup_intcapxt()
2441 static int iommu_setup_intcapxt(struct amd_iommu *iommu) in iommu_setup_intcapxt() argument
2445 snprintf(iommu->evt_irq_name, sizeof(iommu->evt_irq_name), in iommu_setup_intcapxt()
2446 "AMD-Vi%d-Evt", iommu->index); in iommu_setup_intcapxt()
2447 ret = __iommu_setup_intcapxt(iommu, iommu->evt_irq_name, in iommu_setup_intcapxt()
2453 snprintf(iommu->ppr_irq_name, sizeof(iommu->ppr_irq_name), in iommu_setup_intcapxt()
2454 "AMD-Vi%d-PPR", iommu->index); in iommu_setup_intcapxt()
2455 ret = __iommu_setup_intcapxt(iommu, iommu->ppr_irq_name, in iommu_setup_intcapxt()
2462 snprintf(iommu->ga_irq_name, sizeof(iommu->ga_irq_name), in iommu_setup_intcapxt()
2463 "AMD-Vi%d-GA", iommu->index); in iommu_setup_intcapxt()
2464 ret = __iommu_setup_intcapxt(iommu, iommu->ga_irq_name, in iommu_setup_intcapxt()
2472 static int iommu_init_irq(struct amd_iommu *iommu) in iommu_init_irq() argument
2476 if (iommu->int_enabled) in iommu_init_irq()
2480 ret = iommu_setup_intcapxt(iommu); in iommu_init_irq()
2481 else if (iommu->dev->msi_cap) in iommu_init_irq()
2482 ret = iommu_setup_msi(iommu); in iommu_init_irq()
2489 iommu->int_enabled = true; in iommu_init_irq()
2493 iommu_feature_enable(iommu, CONTROL_INTCAPXT_EN); in iommu_init_irq()
2495 iommu_feature_enable(iommu, CONTROL_EVT_INT_EN); in iommu_init_irq()
2651 static void iommu_init_flags(struct amd_iommu *iommu) in iommu_init_flags() argument
2653 iommu->acpi_flags & IVHD_FLAG_HT_TUN_EN_MASK ? in iommu_init_flags()
2654 iommu_feature_enable(iommu, CONTROL_HT_TUN_EN) : in iommu_init_flags()
2655 iommu_feature_disable(iommu, CONTROL_HT_TUN_EN); in iommu_init_flags()
2657 iommu->acpi_flags & IVHD_FLAG_PASSPW_EN_MASK ? in iommu_init_flags()
2658 iommu_feature_enable(iommu, CONTROL_PASSPW_EN) : in iommu_init_flags()
2659 iommu_feature_disable(iommu, CONTROL_PASSPW_EN); in iommu_init_flags()
2661 iommu->acpi_flags & IVHD_FLAG_RESPASSPW_EN_MASK ? in iommu_init_flags()
2662 iommu_feature_enable(iommu, CONTROL_RESPASSPW_EN) : in iommu_init_flags()
2663 iommu_feature_disable(iommu, CONTROL_RESPASSPW_EN); in iommu_init_flags()
2665 iommu->acpi_flags & IVHD_FLAG_ISOC_EN_MASK ? in iommu_init_flags()
2666 iommu_feature_enable(iommu, CONTROL_ISOC_EN) : in iommu_init_flags()
2667 iommu_feature_disable(iommu, CONTROL_ISOC_EN); in iommu_init_flags()
2670 * make IOMMU memory accesses cache coherent in iommu_init_flags()
2672 iommu_feature_enable(iommu, CONTROL_COHERENT_EN); in iommu_init_flags()
2675 iommu_set_inv_tlb_timeout(iommu, CTRL_INV_TO_1S); in iommu_init_flags()
2678 static void iommu_apply_resume_quirks(struct amd_iommu *iommu) in iommu_apply_resume_quirks() argument
2682 struct pci_dev *pdev = iommu->root_pdev; in iommu_apply_resume_quirks()
2684 /* RD890 BIOSes may not have completely reconfigured the iommu */ in iommu_apply_resume_quirks()
2685 if (!is_rd890_iommu(iommu->dev) || !pdev) in iommu_apply_resume_quirks()
2689 * First, we need to ensure that the iommu is enabled. This is in iommu_apply_resume_quirks()
2697 /* Enable the iommu */ in iommu_apply_resume_quirks()
2701 /* Restore the iommu BAR */ in iommu_apply_resume_quirks()
2702 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2703 iommu->stored_addr_lo); in iommu_apply_resume_quirks()
2704 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 8, in iommu_apply_resume_quirks()
2705 iommu->stored_addr_hi); in iommu_apply_resume_quirks()
2710 iommu_write_l1(iommu, i, j, iommu->stored_l1[i][j]); in iommu_apply_resume_quirks()
2714 iommu_write_l2(iommu, i, iommu->stored_l2[i]); in iommu_apply_resume_quirks()
2717 pci_write_config_dword(iommu->dev, iommu->cap_ptr + 4, in iommu_apply_resume_quirks()
2718 iommu->stored_addr_lo | 1); in iommu_apply_resume_quirks()
2721 static void iommu_enable_ga(struct amd_iommu *iommu) in iommu_enable_ga() argument
2727 iommu_feature_enable(iommu, CONTROL_GA_EN); in iommu_enable_ga()
2728 iommu->irte_ops = &irte_128_ops; in iommu_enable_ga()
2731 iommu->irte_ops = &irte_32_ops; in iommu_enable_ga()
2737 static void iommu_disable_irtcachedis(struct amd_iommu *iommu) in iommu_disable_irtcachedis() argument
2739 iommu_feature_disable(iommu, CONTROL_IRTCACHEDIS); in iommu_disable_irtcachedis()
2742 static void iommu_enable_irtcachedis(struct amd_iommu *iommu) in iommu_enable_irtcachedis() argument
2754 iommu_feature_enable(iommu, CONTROL_IRTCACHEDIS); in iommu_enable_irtcachedis()
2755 ctrl = readq(iommu->mmio_base + MMIO_CONTROL_OFFSET); in iommu_enable_irtcachedis()
2758 iommu->irtcachedis_enabled = true; in iommu_enable_irtcachedis()
2759 pr_info("iommu%d (%#06x) : IRT cache is %s\n", in iommu_enable_irtcachedis()
2760 iommu->index, iommu->devid, in iommu_enable_irtcachedis()
2761 iommu->irtcachedis_enabled ? "disabled" : "enabled"); in iommu_enable_irtcachedis()
2764 static void early_enable_iommu(struct amd_iommu *iommu) in early_enable_iommu() argument
2766 iommu_disable(iommu); in early_enable_iommu()
2767 iommu_init_flags(iommu); in early_enable_iommu()
2768 iommu_set_device_table(iommu); in early_enable_iommu()
2769 iommu_enable_command_buffer(iommu); in early_enable_iommu()
2770 iommu_enable_event_buffer(iommu); in early_enable_iommu()
2771 iommu_set_exclusion_range(iommu); in early_enable_iommu()
2772 iommu_enable_ga(iommu); in early_enable_iommu()
2773 iommu_enable_xt(iommu); in early_enable_iommu()
2774 iommu_enable_irtcachedis(iommu); in early_enable_iommu()
2775 iommu_enable(iommu); in early_enable_iommu()
2776 amd_iommu_flush_all_caches(iommu); in early_enable_iommu()
2789 struct amd_iommu *iommu; in early_enable_iommus() local
2809 for_each_iommu(iommu) { in early_enable_iommus()
2810 clear_translation_pre_enabled(iommu); in early_enable_iommus()
2811 early_enable_iommu(iommu); in early_enable_iommus()
2822 for_each_iommu(iommu) { in early_enable_iommus()
2823 iommu_disable_command_buffer(iommu); in early_enable_iommus()
2824 iommu_disable_event_buffer(iommu); in early_enable_iommus()
2825 iommu_disable_irtcachedis(iommu); in early_enable_iommus()
2826 iommu_enable_command_buffer(iommu); in early_enable_iommus()
2827 iommu_enable_event_buffer(iommu); in early_enable_iommus()
2828 iommu_enable_ga(iommu); in early_enable_iommus()
2829 iommu_enable_xt(iommu); in early_enable_iommus()
2830 iommu_enable_irtcachedis(iommu); in early_enable_iommus()
2831 iommu_set_device_table(iommu); in early_enable_iommus()
2832 amd_iommu_flush_all_caches(iommu); in early_enable_iommus()
2839 struct amd_iommu *iommu; in enable_iommus_v2() local
2841 for_each_iommu(iommu) { in enable_iommus_v2()
2842 iommu_enable_ppr_log(iommu); in enable_iommus_v2()
2843 iommu_enable_gt(iommu); in enable_iommus_v2()
2851 struct amd_iommu *iommu; in enable_iommus_vapic() local
2853 for_each_iommu(iommu) { in enable_iommus_vapic()
2858 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2862 iommu_feature_disable(iommu, CONTROL_GALOG_EN); in enable_iommus_vapic()
2863 iommu_feature_disable(iommu, CONTROL_GAINT_EN); in enable_iommus_vapic()
2870 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET); in enable_iommus_vapic()
2894 for_each_iommu(iommu) { in enable_iommus_vapic()
2895 if (iommu_init_ga_log(iommu) || in enable_iommus_vapic()
2896 iommu_ga_log_enable(iommu)) in enable_iommus_vapic()
2899 iommu_feature_enable(iommu, CONTROL_GAM_EN); in enable_iommus_vapic()
2901 iommu_feature_enable(iommu, CONTROL_SNPAVIC_EN); in enable_iommus_vapic()
2916 struct amd_iommu *iommu; in disable_iommus() local
2918 for_each_iommu(iommu) in disable_iommus()
2919 iommu_disable(iommu); in disable_iommus()
2934 struct amd_iommu *iommu; in amd_iommu_resume() local
2936 for_each_iommu(iommu) in amd_iommu_resume()
2937 iommu_apply_resume_quirks(iommu); in amd_iommu_resume()
3034 * This is the hardware init function for AMD IOMMU in the system.
3038 * This function basically parses the ACPI table for AMD IOMMU (IVRS)
3166 struct amd_iommu *iommu; in amd_iommu_enable_interrupts() local
3169 for_each_iommu(iommu) { in amd_iommu_enable_interrupts()
3170 ret = iommu_init_irq(iommu); in amd_iommu_enable_interrupts()
3206 /* Don't use IOMMU if there is Stoney Ridge graphics */ in detect_ivrs()
3212 pr_info("Disable IOMMU on Stoney Ridge\n"); in detect_ivrs()
3226 * AMD IOMMU Initialization State Machine
3289 struct amd_iommu *iommu; in state_next() local
3295 for_each_iommu(iommu) in state_next()
3296 amd_iommu_flush_all_caches(iommu); in state_next()
3365 * This is the core init function for AMD IOMMU hardware in the system.
3371 struct amd_iommu *iommu; in amd_iommu_init() local
3378 * We failed to initialize the AMD IOMMU - try fallback in amd_iommu_init()
3385 for_each_iommu(iommu) in amd_iommu_init()
3386 amd_iommu_debugfs_setup(iommu); in amd_iommu_init()
3405 pr_notice("IOMMU not currently supported when SME is active\n"); in amd_iommu_sme_check()
3412 * Early detect code. This code runs at IOMMU detection time in the DMA
3433 x86_init.iommu.iommu_init = amd_iommu_init; in amd_iommu_detect()
3440 * Parsing functions for the AMD IOMMU specific kernel command line
3474 pr_warn("amd_iommu=fullflush deprecated; use iommu.strict=1 instead\n"); in parse_amd_iommu_options()
3657 /* CPU page table size should match IOMMU guest page table size */ in amd_iommu_v2_supported()
3673 struct amd_iommu *iommu; in get_amd_iommu() local
3675 for_each_iommu(iommu) in get_amd_iommu()
3677 return iommu; in get_amd_iommu()
3683 * IOMMU EFR Performance Counter support functionality. This code allows
3684 * access to the IOMMU PC functionality.
3690 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_banks() local
3692 if (iommu) in amd_iommu_pc_get_max_banks()
3693 return iommu->max_banks; in amd_iommu_pc_get_max_banks()
3707 struct amd_iommu *iommu = get_amd_iommu(idx); in amd_iommu_pc_get_max_counters() local
3709 if (iommu) in amd_iommu_pc_get_max_counters()
3710 return iommu->max_counters; in amd_iommu_pc_get_max_counters()
3716 static int iommu_pc_get_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, in iommu_pc_get_set_reg() argument
3722 /* Make sure the IOMMU PC resource is available */ in iommu_pc_get_set_reg()
3726 /* Check for valid iommu and pc register indexing */ in iommu_pc_get_set_reg()
3727 if (WARN_ON(!iommu || (fxn > 0x28) || (fxn & 7))) in iommu_pc_get_set_reg()
3733 max_offset_lim = (u32)(((0x40 | iommu->max_banks) << 12) | in iommu_pc_get_set_reg()
3734 (iommu->max_counters << 8) | 0x28); in iommu_pc_get_set_reg()
3742 writel((u32)val, iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3743 writel((val >> 32), iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3745 *value = readl(iommu->mmio_base + offset + 4); in iommu_pc_get_set_reg()
3747 *value |= readl(iommu->mmio_base + offset); in iommu_pc_get_set_reg()
3754 int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_get_reg() argument
3756 if (!iommu) in amd_iommu_pc_get_reg()
3759 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, false); in amd_iommu_pc_get_reg()
3762 int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr, u8 fxn, u64 *value) in amd_iommu_pc_set_reg() argument
3764 if (!iommu) in amd_iommu_pc_set_reg()
3767 return iommu_pc_get_set_reg(iommu, bank, cntr, fxn, value, true); in amd_iommu_pc_set_reg()
3774 * The SNP support requires that IOMMU must be enabled, and is in amd_iommu_snp_enable()
3778 pr_err("SNP: IOMMU is disabled or configured in passthrough mode, SNP cannot be supported"); in amd_iommu_snp_enable()
3784 * affect how IOMMU driver sets up data structures and configures in amd_iommu_snp_enable()
3785 * IOMMU hardware. in amd_iommu_snp_enable()
3788 pr_err("SNP: Too late to enable SNP for IOMMU.\n"); in amd_iommu_snp_enable()
3798 /* Enforce IOMMU v1 pagetable when SNP is enabled. */ in amd_iommu_snp_enable()
3800 pr_warn("Force to using AMD IOMMU v1 page table due to SNP\n"); in amd_iommu_snp_enable()