Lines Matching +full:16 +full:- +full:bit
3 * Copyright (C) 2012-2015 Emulex. All rights reserved.
16 * - Redistributions of source code must retain the above copyright notice,
19 * - Redistributions in binary form must reproduce the above copyright
36 * linux-drivers@emulex.com
77 OCRDMA_CMD_QUERY_NSMR = 16,
122 #define OCRDMA_MAX_SGID 16
139 OCRDMA_DB_SQ_SHIFT = 16,
149 #define OCRDMA_DB_CQ_RING_ID_MASK 0x3FF /* bits 0 - 9 */
150 #define OCRDMA_DB_CQ_RING_ID_EXT_MASK 0x0C00 /* bits 10-11 of qid at 12-11 */
151 /* qid #2 msbits at 12-11 */
153 #define OCRDMA_DB_CQ_NUM_POPPED_SHIFT 16 /* bits 16 - 28 */
154 /* Rearm bit */
155 #define OCRDMA_DB_CQ_REARM_SHIFT 29 /* bit 29 */
156 /* solicited bit */
157 #define OCRDMA_DB_CQ_SOLICIT_SHIFT 31 /* bit 31 */
159 #define OCRDMA_EQ_ID_MASK 0x1FF /* bits 0 - 8 */
160 #define OCRDMA_EQ_ID_EXT_MASK 0x3e00 /* bits 9-13 */
161 #define OCRDMA_EQ_ID_EXT_MASK_SHIFT 2 /* qid bits 9-13 at 11-15 */
164 #define OCRDMA_EQ_CLR_SHIFT 9 /* bit 9 */
166 #define OCRDMA_EQ_TYPE_SHIFT 10 /* bit 10 */
168 #define OCRDMA_NUM_EQE_SHIFT 16 /* bits 16 - 28 */
169 /* Rearm bit */
170 #define OCRDMA_REARM_SHIFT 29 /* bit 29 */
172 #define OCRDMA_MQ_ID_MASK 0x7FF /* bits 0 - 10 */
174 #define OCRDMA_MQ_NUM_MQE_SHIFT 16 /* bits 16 - 29 */
188 # 2: 16K Bytes
211 #define OCRDMA_WQE_ALIGN_BYTES 16
263 OCRDMA_MQE_HDR_EMB_MASK = BIT(0),
304 ((u32)((((size_t)(_address) & (PAGE_SIZE_4K - 1)) + \
305 (size) + (PAGE_SIZE_4K - 1)) >> PAGE_SHIFT_4K))
329 OCRDMA_CREATE_EQ_VALID = BIT(29),
367 OCRDMA_MCQE_ESTATUS_SHIFT = 16,
370 OCRDMA_MCQE_CONS_MASK = BIT(27),
372 OCRDMA_MCQE_CMPL_MASK = BIT(28),
374 OCRDMA_MCQE_AE_MASK = BIT(30),
376 OCRDMA_MCQE_VALID_MASK = BIT(31)
387 OCRDMA_AE_MCQE_QPVALID = BIT(31),
390 OCRDMA_AE_MCQE_CQVALID = BIT(31),
392 OCRDMA_AE_MCQE_VALID = BIT(31),
393 OCRDMA_AE_MCQE_AE = BIT(30),
394 OCRDMA_AE_MCQE_EVENT_TYPE_SHIFT = 16,
411 OCRDMA_AE_PVID_MCQE_TAG_SHIFT = 16,
423 OCRDMA_AE_MPA_MCQE_REQ_ID_SHIFT = 16,
430 OCRDMA_AE_MPA_MCQE_EVENT_TYPE_SHIFT = 16,
434 OCRDMA_AE_MPA_MCQE_EVENT_AE_MASK = BIT(30),
436 OCRDMA_AE_MPA_MCQE_EVENT_VALID_MASK = BIT(31)
449 OCRDMA_AE_QP_MCQE_QP_ID_SHIFT = 16,
456 OCRDMA_AE_QP_MCQE_EVENT_TYPE_SHIFT = 16,
460 OCRDMA_AE_QP_MCQE_EVENT_AE_MASK = BIT(30),
462 OCRDMA_AE_QP_MCQE_EVENT_VALID_MASK = BIT(31)
540 OCRDMA_MBX_QUERY_CFG_CQ_OVERFLOW_MASK = BIT(2),
542 OCRDMA_MBX_QUERY_CFG_SRQ_SUPPORTED_MASK = BIT(3),
547 OCRDMA_MBX_QUERY_CFG_MAX_PD_SHIFT = 16,
557 OCRDMA_MBX_QUERY_CFG_MAX_RECV_SGE_SHIFT = 16,
563 OCRDMA_MBX_QUERY_CFG_MAX_IRD_PER_QP_SHIFT = 16,
570 OCRDMA_MBX_QUERY_CFG_MAX_RQE_SIZE_OFFSET = 16,
577 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_OFFSET = 16,
584 OCRDMA_MBX_QUERY_CFG_MAX_DPP_PDS_OFFSET = 16,
595 OCRDMA_MBX_QUERY_CFG_MAX_WQES_PER_WQ_OFFSET = 16,
602 OCRDMA_MBX_QUERY_CFG_MAX_CQ_OFFSET = 16,
609 OCRDMA_MBX_QUERY_CFG_MAX_SRQ_RQE_OFFSET = 16,
764 OCRDMA_CREATE_CQ_PAGE_SIZE_SHIFT = 16,
768 OCRDMA_CREATE_CQ_COALESCWM_MASK = BIT(13) | BIT(12),
769 OCRDMA_CREATE_CQ_FLAGS_NODELAY = BIT(14),
770 OCRDMA_CREATE_CQ_FLAGS_AUTO_VALID = BIT(15),
783 OCRDMA_CREATE_CQ_FLAGS_VALID = BIT(29),
784 OCRDMA_CREATE_CQ_FLAGS_EVENTABLE = BIT(31),
825 OCRDMA_CREATE_MQ_CQ_ID_SHIFT = 16,
826 OCRDMA_CREATE_MQ_RING_SIZE_SHIFT = 16,
827 OCRDMA_CREATE_MQ_VALID = BIT(31),
828 OCRDMA_CREATE_MQ_ASYNC_CQ_VALID = BIT(0)
850 OCRDMA_DESTROY_CQ_QID_BYPASS_FLUSH_SHIFT = 16,
876 OCRDMA_CREATE_QP_REQ_SQ_PAGE_SIZE_SHIFT = 16,
879 OCRDMA_CREATE_QP_REQ_QPT_MASK = BIT(31) | BIT(30) | BIT(29),
883 OCRDMA_CREATE_QP_REQ_MAX_WQE_SHIFT = 16,
889 OCRDMA_CREATE_QP_REQ_MAX_SGE_SEND_SHIFT = 16,
894 OCRDMA_CREATE_QP_REQ_FMR_EN_MASK = BIT(0),
896 OCRDMA_CREATE_QP_REQ_ZERO_LKEYEN_MASK = BIT(1),
898 OCRDMA_CREATE_QP_REQ_BIND_MEMWIN_MASK = BIT(2),
900 OCRDMA_CREATE_QP_REQ_INB_WREN_MASK = BIT(3),
902 OCRDMA_CREATE_QP_REQ_INB_RDEN_MASK = BIT(4),
904 OCRDMA_CREATE_QP_REQ_USE_SRQ_MASK = BIT(5),
906 OCRDMA_CREATE_QP_REQ_ENABLE_RPIR_MASK = BIT(6),
908 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_MASK = BIT(7),
910 OCRDMA_CREATE_QP_REQ_ENABLE_DPP_CQ_MASK = BIT(8),
911 OCRDMA_CREATE_QP_REQ_MAX_SGE_RECV_SHIFT = 16,
917 OCRDMA_CREATE_QP_REQ_MAX_ORD_SHIFT = 16,
923 OCRDMA_CREATE_QP_REQ_NUM_WQ_PAGES_SHIFT = 16,
929 OCRDMA_CREATE_QP_REQ_WQE_SIZE_SHIFT = 16,
935 OCRDMA_CREATE_QP_REQ_WQ_CQID_SHIFT = 16,
941 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_SHIFT = 16,
947 OCRDMA_CREATE_QP_REQ_DPP_CREDIT_LIMIT = 16,
997 OCRDMA_CREATE_QP_RSP_MAX_WQE_SHIFT = 16,
1003 OCRDMA_CREATE_QP_RSP_MAX_SGE_SEND_SHIFT = 16,
1007 OCRDMA_CREATE_QP_RSP_MAX_SGE_RECV_SHIFT = 16,
1013 OCRDMA_CREATE_QP_RSP_MAX_ORD_SHIFT = 16,
1019 OCRDMA_CREATE_QP_RSP_SQ_ID_SHIFT = 16,
1023 OCRDMA_CREATE_QP_RSP_DPP_ENABLED_MASK = BIT(0),
1027 OCRDMA_CREATE_QP_RSP_DPP_CREDITS_SHIFT = 16,
1060 OCRDMA_QP_PARA_QPS_VALID = BIT(0),
1061 OCRDMA_QP_PARA_SQD_ASYNC_VALID = BIT(1),
1062 OCRDMA_QP_PARA_PKEY_VALID = BIT(2),
1063 OCRDMA_QP_PARA_QKEY_VALID = BIT(3),
1064 OCRDMA_QP_PARA_PMTU_VALID = BIT(4),
1065 OCRDMA_QP_PARA_ACK_TO_VALID = BIT(5),
1066 OCRDMA_QP_PARA_RETRY_CNT_VALID = BIT(6),
1067 OCRDMA_QP_PARA_RRC_VALID = BIT(7),
1068 OCRDMA_QP_PARA_RQPSN_VALID = BIT(8),
1069 OCRDMA_QP_PARA_MAX_IRD_VALID = BIT(9),
1070 OCRDMA_QP_PARA_MAX_ORD_VALID = BIT(10),
1071 OCRDMA_QP_PARA_RNT_VALID = BIT(11),
1072 OCRDMA_QP_PARA_SQPSN_VALID = BIT(12),
1073 OCRDMA_QP_PARA_DST_QPN_VALID = BIT(13),
1074 OCRDMA_QP_PARA_MAX_WQE_VALID = BIT(14),
1075 OCRDMA_QP_PARA_MAX_RQE_VALID = BIT(15),
1076 OCRDMA_QP_PARA_SGE_SEND_VALID = BIT(16),
1077 OCRDMA_QP_PARA_SGE_RECV_VALID = BIT(17),
1078 OCRDMA_QP_PARA_SGE_WR_VALID = BIT(18),
1079 OCRDMA_QP_PARA_INB_RDEN_VALID = BIT(19),
1080 OCRDMA_QP_PARA_INB_WREN_VALID = BIT(20),
1081 OCRDMA_QP_PARA_FLOW_LBL_VALID = BIT(21),
1082 OCRDMA_QP_PARA_BIND_EN_VALID = BIT(22),
1083 OCRDMA_QP_PARA_ZLKEY_EN_VALID = BIT(23),
1084 OCRDMA_QP_PARA_FMR_EN_VALID = BIT(24),
1085 OCRDMA_QP_PARA_INBAT_EN_VALID = BIT(25),
1086 OCRDMA_QP_PARA_VLAN_EN_VALID = BIT(26),
1088 OCRDMA_MODIFY_QP_FLAGS_RD = BIT(0),
1089 OCRDMA_MODIFY_QP_FLAGS_WR = BIT(1),
1090 OCRDMA_MODIFY_QP_FLAGS_SEND = BIT(2),
1091 OCRDMA_MODIFY_QP_FLAGS_ATOMIC = BIT(3)
1100 OCRDMA_QP_PARAMS_MAX_WQE_SHIFT = 16,
1106 OCRDMA_QP_PARAMS_MAX_SGE_SEND_SHIFT = 16,
1110 OCRDMA_QP_PARAMS_FLAGS_FMR_EN = BIT(0),
1111 OCRDMA_QP_PARAMS_FLAGS_LKEY_0_EN = BIT(1),
1112 OCRDMA_QP_PARAMS_FLAGS_BIND_MW_EN = BIT(2),
1113 OCRDMA_QP_PARAMS_FLAGS_INBWR_EN = BIT(3),
1114 OCRDMA_QP_PARAMS_FLAGS_INBRD_EN = BIT(4),
1116 OCRDMA_QP_PARAMS_STATE_MASK = BIT(5) | BIT(6) | BIT(7),
1117 OCRDMA_QP_PARAMS_FLAGS_SQD_ASYNC = BIT(8),
1118 OCRDMA_QP_PARAMS_FLAGS_INB_ATEN = BIT(9),
1120 OCRDMA_QP_PARAMS_FLAGS_L3_TYPE_MASK = BIT(11) | BIT(12) | BIT(13),
1121 OCRDMA_QP_PARAMS_MAX_SGE_RECV_SHIFT = 16,
1127 OCRDMA_QP_PARAMS_MAX_ORD_SHIFT = 16,
1133 OCRDMA_QP_PARAMS_WQ_CQID_SHIFT = 16,
1178 OCRDMA_QP_PARAMS_VLAN_SHIFT = 16,
1195 u8 sgid[16];
1196 u8 dgid[16];
1216 OCRDMA_MODIFY_QP_RSP_MAX_WQE_SHIFT = 16,
1222 OCRDMA_MODIFY_QP_RSP_MAX_ORD_SHIFT = 16,
1255 OCRDMA_CREATE_SRQ_PG_SZ_SHIFT = 16,
1260 OCRDMA_CREATE_SRQ_MAX_SGE_RECV_SHIFT = 16,
1266 OCRDMA_CREATE_SRQ_NUM_RQ_PAGES_SHIFT = 16,
1287 OCRDMA_CREATE_SRQ_RSP_MAX_SGE_RECV_ALLOCATED_SHIFT = 16,
1306 OCRDMA_MODIFY_SRQ_LIMIT_SHIFT = 16,
1334 OCRDMA_QUERY_SRQ_RSP_MAX_RQE_SHIFT = 16,
1340 OCRDMA_QUERY_SRQ_RSP_SRQ_LIMIT_SHIFT = 16,
1366 OCRDMA_ALLOC_PD_ENABLE_DPP = BIT(16),
1377 OCRDMA_ALLOC_PD_RSP_DPP = BIT(16),
1440 OCRDMA_ALLOC_LKEY_ADDR_CHECK_MASK = BIT(0),
1442 OCRDMA_ALLOC_LKEY_FMR_MASK = BIT(1),
1444 OCRDMA_ALLOC_LKEY_REMOTE_INV_MASK = BIT(2),
1446 OCRDMA_ALLOC_LKEY_REMOTE_WR_MASK = BIT(3),
1448 OCRDMA_ALLOC_LKEY_REMOTE_RD_MASK = BIT(4),
1450 OCRDMA_ALLOC_LKEY_LOCAL_WR_MASK = BIT(5),
1451 OCRDMA_ALLOC_LKEY_REMOTE_ATOMIC_MASK = BIT(6),
1453 OCRDMA_ALLOC_LKEY_PBL_SIZE_SHIFT = 16,
1500 OCRDMA_REG_NSMR_NUM_PBL_SHIFT = 16,
1506 OCRDMA_REG_NSMR_HPAGE_SIZE_SHIFT = 16,
1510 OCRDMA_REG_NSMR_BIND_MEMWIN_MASK = BIT(24),
1512 OCRDMA_REG_NSMR_ZB_SHIFT_MASK = BIT(25),
1514 OCRDMA_REG_NSMR_REMOTE_INV_MASK = BIT(26),
1516 OCRDMA_REG_NSMR_REMOTE_WR_MASK = BIT(27),
1518 OCRDMA_REG_NSMR_REMOTE_RD_MASK = BIT(28),
1520 OCRDMA_REG_NSMR_LOCAL_WR_MASK = BIT(29),
1522 OCRDMA_REG_NSMR_REMOTE_ATOMIC_MASK = BIT(30),
1524 OCRDMA_REG_NSMR_LAST_MASK = BIT(31)
1546 OCRDMA_REG_NSMR_CONT_NUM_PBL_SHIFT = 16,
1551 OCRDMA_REG_NSMR_CONT_LAST_MASK = BIT(31)
1571 OCRDMA_REG_NSMR_RSP_NUM_PBL_SHIFT = 16,
1589 OCRDMA_REG_NSMR_CONT_RSP_NUM_PBL_SHIFT = 16,
1630 u8 mgid[16];
1644 u8 mgid[16];
1659 OCRDMA_CREATE_AH_PAGE_SIZE_SHIFT = 16,
1697 OCRDMA_EQE_VALID_MASK = BIT(0),
1701 OCRDMA_EQE_RESOURCE_ID_SHIFT = 16,
1748 OCRDMA_CQE_UD_XFER_LEN_SHIFT = 16,
1759 OCRDMA_CQE_BUFTAG_SHIFT = 16,
1765 OCRDMA_CQE_STATUS_SHIFT = 16,
1767 OCRDMA_CQE_VALID = BIT(31),
1768 OCRDMA_CQE_INVALIDATE = BIT(30),
1769 OCRDMA_CQE_QTYPE = BIT(29),
1770 OCRDMA_CQE_IMM = BIT(28),
1771 OCRDMA_CQE_WRITE_IMM = BIT(27),
1850 OCRDMA_WQE_TYPE_SHIFT = 16,
1910 u8 sgid[16];
1911 u8 dgid[16];
1915 #define OCRDMA_AV_VALID BIT(7)
1916 #define OCRDMA_AV_VLAN_VALID BIT(1)