hw/erdma/erdma_hw.h

1 /* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
5 /* Copyright (c) 2020-2022, Alibaba Group. */
20 /* MSI-X related. */
90 #define ERDMA_CQDB_ARM_MASK BIT_ULL(31)
95 #define ERDMA_EQDB_ARM_MASK BIT(31)
113 #define SQEBB_MASK (~(SQEBB_SIZE - 1))
114 #define SQEBB_ALIGN(size) ((size + SQEBB_SIZE - 1) & SQEBB_MASK)
134 	CMDQ_OPCODE_MODIFY_QP = 3,
146 	CMDQ_OPCODE_CONF_MTU = 3,
153 /* cmdq-SQE HDR */
189 #define ERDMA_CMD_CONFIG_DEVICE_PS_EN_MASK BIT(31)
215 	u32 rsvd1[3];
224 #define ERDMA_CMD_CREATE_CQ_DEPTH_MASK GENMASK(31, 24)
229 #define ERDMA_CMD_CREATE_CQ_MTT_CNT_MASK GENMASK(31, 16)
249 #define ERDMA_CMD_MR_VALID_MASK BIT(31)
255 #define ERDMA_CMD_REGMR_PD_MASK GENMASK(31, 12)
260 #define ERDMA_CMD_REGMR_PAGESIZE_MASK GENMASK(31, 27)
288 #define ERDMA_CMD_MODIFY_QP_STATE_MASK GENMASK(31, 24)
305 #define ERDMA_CMD_CREATE_QP_SQ_DEPTH_MASK GENMASK(31, 20)
309 #define ERDMA_CMD_CREATE_QP_RQ_DEPTH_MASK GENMASK(31, 20)
313 #define ERDMA_CMD_CREATE_QP_PAGE_SIZE_MASK GENMASK(31, 28)
318 #define ERDMA_CMD_CREATE_QP_PAGE_OFFSET_MASK GENMASK(31, 12)
323 #define ERDMA_CMD_CREATE_QP_SQDB_CFG_MASK GENMASK(31, 16)
326 #define ERDMA_CMDQ_CREATE_QP_RESP_COOKIE_MASK GENMASK_ULL(31, 0)
341 	u64 sq_mtt_entry[3];
342 	u64 rq_mtt_entry[3];
399 #define ERDMA_CMD_DEV_CAP_FLAGS_MASK GENMASK_ULL(31, 24)
405 #define ERDMA_CMD_DEV_CAP_DEFAULT_CC_MASK GENMASK_ULL(31, 28)
414 	ERDMA_DEV_CAP_FLAGS_EXTEND_DB = 1 << 3,
417 #define ERDMA_CMD_INFO0_FW_VER_MASK GENMASK_ULL(31, 0)
420 #define ERDMA_CQE_HDR_OWNER_MASK BIT(31)
438 	__be32 rsvd[3];
463 #define ERDMA_SQE_HDR_OPCODE_MASK GENMASK_ULL(31, 27)
474 #define ERDMA_SQE_MR_MTT_CNT_MASK GENMASK(31, 12)
536 #define ERDMA_CEQE_HDR_O_MASK BIT_ULL(31)
540 #define ERDMA_AEQE_HDR_O_MASK BIT(31)
547 #define ERDMA_AE_TYPE_CQ_ERR 3
561 	ERDMA_OP_SEND_WITH_IMM = 3,
590 	ERDMA_WC_RECV_STAG_INVALID_ERR = 3,
611 	ERDMA_WC_VENDOR_RQE_ADDR_VIOLATION = 3,