Lines Matching +full:supports +full:- +full:cqe
1 // SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause
3 * Copyright 2018-2021 Amazon.com, Inc. or its affiliates. All rights reserved.
74 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; in efa_com_reg_read32()
80 read_resp = mmio_read->read_resp; in efa_com_reg_read32()
82 spin_lock(&mmio_read->lock); in efa_com_reg_read32()
83 mmio_read->seq_num++; in efa_com_reg_read32()
86 read_resp->req_id = mmio_read->seq_num + 0x9aL; in efa_com_reg_read32()
89 mmio_read->seq_num); in efa_com_reg_read32()
91 writel(mmio_read_reg, edev->reg_bar + EFA_REGS_MMIO_REG_READ_OFF); in efa_com_reg_read32()
93 exp_time = jiffies + usecs_to_jiffies(mmio_read->mmio_read_timeout); in efa_com_reg_read32()
95 if (READ_ONCE(read_resp->req_id) == mmio_read->seq_num) in efa_com_reg_read32()
100 if (read_resp->req_id != mmio_read->seq_num) { in efa_com_reg_read32()
102 edev->efa_dev, in efa_com_reg_read32()
104 mmio_read->seq_num, offset, read_resp->req_id, in efa_com_reg_read32()
105 read_resp->reg_off); in efa_com_reg_read32()
110 if (read_resp->reg_off != offset) { in efa_com_reg_read32()
112 edev->efa_dev, in efa_com_reg_read32()
118 err = read_resp->reg_val; in efa_com_reg_read32()
120 spin_unlock(&mmio_read->lock); in efa_com_reg_read32()
126 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_init_sq()
127 struct efa_com_admin_sq *sq = &aq->sq; in efa_com_admin_init_sq()
128 u16 size = aq->depth * sizeof(*sq->entries); in efa_com_admin_init_sq()
133 sq->entries = in efa_com_admin_init_sq()
134 dma_alloc_coherent(aq->dmadev, size, &sq->dma_addr, GFP_KERNEL); in efa_com_admin_init_sq()
135 if (!sq->entries) in efa_com_admin_init_sq()
136 return -ENOMEM; in efa_com_admin_init_sq()
138 spin_lock_init(&sq->lock); in efa_com_admin_init_sq()
140 sq->cc = 0; in efa_com_admin_init_sq()
141 sq->pc = 0; in efa_com_admin_init_sq()
142 sq->phase = 1; in efa_com_admin_init_sq()
144 sq->db_addr = (u32 __iomem *)(edev->reg_bar + EFA_REGS_AQ_PROD_DB_OFF); in efa_com_admin_init_sq()
146 addr_high = upper_32_bits(sq->dma_addr); in efa_com_admin_init_sq()
147 addr_low = lower_32_bits(sq->dma_addr); in efa_com_admin_init_sq()
149 writel(addr_low, edev->reg_bar + EFA_REGS_AQ_BASE_LO_OFF); in efa_com_admin_init_sq()
150 writel(addr_high, edev->reg_bar + EFA_REGS_AQ_BASE_HI_OFF); in efa_com_admin_init_sq()
152 EFA_SET(&aq_caps, EFA_REGS_AQ_CAPS_AQ_DEPTH, aq->depth); in efa_com_admin_init_sq()
156 writel(aq_caps, edev->reg_bar + EFA_REGS_AQ_CAPS_OFF); in efa_com_admin_init_sq()
163 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_init_cq()
164 struct efa_com_admin_cq *cq = &aq->cq; in efa_com_admin_init_cq()
165 u16 size = aq->depth * sizeof(*cq->entries); in efa_com_admin_init_cq()
170 cq->entries = in efa_com_admin_init_cq()
171 dma_alloc_coherent(aq->dmadev, size, &cq->dma_addr, GFP_KERNEL); in efa_com_admin_init_cq()
172 if (!cq->entries) in efa_com_admin_init_cq()
173 return -ENOMEM; in efa_com_admin_init_cq()
175 spin_lock_init(&cq->lock); in efa_com_admin_init_cq()
177 cq->cc = 0; in efa_com_admin_init_cq()
178 cq->phase = 1; in efa_com_admin_init_cq()
180 addr_high = upper_32_bits(cq->dma_addr); in efa_com_admin_init_cq()
181 addr_low = lower_32_bits(cq->dma_addr); in efa_com_admin_init_cq()
183 writel(addr_low, edev->reg_bar + EFA_REGS_ACQ_BASE_LO_OFF); in efa_com_admin_init_cq()
184 writel(addr_high, edev->reg_bar + EFA_REGS_ACQ_BASE_HI_OFF); in efa_com_admin_init_cq()
186 EFA_SET(&acq_caps, EFA_REGS_ACQ_CAPS_ACQ_DEPTH, aq->depth); in efa_com_admin_init_cq()
190 aq->msix_vector_idx); in efa_com_admin_init_cq()
192 writel(acq_caps, edev->reg_bar + EFA_REGS_ACQ_CAPS_OFF); in efa_com_admin_init_cq()
200 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_admin_init_aenq()
206 ibdev_err(edev->efa_dev, "aenq handlers pointer is NULL\n"); in efa_com_admin_init_aenq()
207 return -EINVAL; in efa_com_admin_init_aenq()
210 size = EFA_ASYNC_QUEUE_DEPTH * sizeof(*aenq->entries); in efa_com_admin_init_aenq()
211 aenq->entries = dma_alloc_coherent(edev->dmadev, size, &aenq->dma_addr, in efa_com_admin_init_aenq()
213 if (!aenq->entries) in efa_com_admin_init_aenq()
214 return -ENOMEM; in efa_com_admin_init_aenq()
216 aenq->aenq_handlers = aenq_handlers; in efa_com_admin_init_aenq()
217 aenq->depth = EFA_ASYNC_QUEUE_DEPTH; in efa_com_admin_init_aenq()
218 aenq->cc = 0; in efa_com_admin_init_aenq()
219 aenq->phase = 1; in efa_com_admin_init_aenq()
221 addr_low = lower_32_bits(aenq->dma_addr); in efa_com_admin_init_aenq()
222 addr_high = upper_32_bits(aenq->dma_addr); in efa_com_admin_init_aenq()
224 writel(addr_low, edev->reg_bar + EFA_REGS_AENQ_BASE_LO_OFF); in efa_com_admin_init_aenq()
225 writel(addr_high, edev->reg_bar + EFA_REGS_AENQ_BASE_HI_OFF); in efa_com_admin_init_aenq()
227 EFA_SET(&aenq_caps, EFA_REGS_AENQ_CAPS_AENQ_DEPTH, aenq->depth); in efa_com_admin_init_aenq()
231 aenq->msix_vector_idx); in efa_com_admin_init_aenq()
232 writel(aenq_caps, edev->reg_bar + EFA_REGS_AENQ_CAPS_OFF); in efa_com_admin_init_aenq()
238 writel(edev->aenq.cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); in efa_com_admin_init_aenq()
248 spin_lock(&aq->comp_ctx_lock); in efa_com_alloc_ctx_id()
249 ctx_id = aq->comp_ctx_pool[aq->comp_ctx_pool_next]; in efa_com_alloc_ctx_id()
250 aq->comp_ctx_pool_next++; in efa_com_alloc_ctx_id()
251 spin_unlock(&aq->comp_ctx_lock); in efa_com_alloc_ctx_id()
259 spin_lock(&aq->comp_ctx_lock); in efa_com_dealloc_ctx_id()
260 aq->comp_ctx_pool_next--; in efa_com_dealloc_ctx_id()
261 aq->comp_ctx_pool[aq->comp_ctx_pool_next] = ctx_id; in efa_com_dealloc_ctx_id()
262 spin_unlock(&aq->comp_ctx_lock); in efa_com_dealloc_ctx_id()
268 u16 cmd_id = EFA_GET(&comp_ctx->user_cqe->acq_common_descriptor.command, in efa_com_put_comp_ctx()
270 u16 ctx_id = cmd_id & (aq->depth - 1); in efa_com_put_comp_ctx()
272 ibdev_dbg(aq->efa_dev, "Put completion command_id %#x\n", cmd_id); in efa_com_put_comp_ctx()
273 comp_ctx->occupied = 0; in efa_com_put_comp_ctx()
280 u16 ctx_id = cmd_id & (aq->depth - 1); in efa_com_get_comp_ctx()
282 if (aq->comp_ctx[ctx_id].occupied && capture) { in efa_com_get_comp_ctx()
284 aq->efa_dev, in efa_com_get_comp_ctx()
291 aq->comp_ctx[ctx_id].occupied = 1; in efa_com_get_comp_ctx()
292 ibdev_dbg(aq->efa_dev, in efa_com_get_comp_ctx()
296 return &aq->comp_ctx[ctx_id]; in efa_com_get_comp_ctx()
312 queue_size_mask = aq->depth - 1; in __efa_com_submit_admin_cmd()
313 pi = aq->sq.pc & queue_size_mask; in __efa_com_submit_admin_cmd()
319 cmd_id |= aq->sq.pc & ~queue_size_mask; in __efa_com_submit_admin_cmd()
322 cmd->aq_common_descriptor.command_id = cmd_id; in __efa_com_submit_admin_cmd()
323 EFA_SET(&cmd->aq_common_descriptor.flags, in __efa_com_submit_admin_cmd()
324 EFA_ADMIN_AQ_COMMON_DESC_PHASE, aq->sq.phase); in __efa_com_submit_admin_cmd()
329 return ERR_PTR(-EINVAL); in __efa_com_submit_admin_cmd()
332 comp_ctx->status = EFA_CMD_SUBMITTED; in __efa_com_submit_admin_cmd()
333 comp_ctx->comp_size = comp_size_in_bytes; in __efa_com_submit_admin_cmd()
334 comp_ctx->user_cqe = comp; in __efa_com_submit_admin_cmd()
335 comp_ctx->cmd_opcode = cmd->aq_common_descriptor.opcode; in __efa_com_submit_admin_cmd()
337 reinit_completion(&comp_ctx->wait_event); in __efa_com_submit_admin_cmd()
339 aqe = &aq->sq.entries[pi]; in __efa_com_submit_admin_cmd()
343 aq->sq.pc++; in __efa_com_submit_admin_cmd()
344 atomic64_inc(&aq->stats.submitted_cmd); in __efa_com_submit_admin_cmd()
346 if ((aq->sq.pc & queue_size_mask) == 0) in __efa_com_submit_admin_cmd()
347 aq->sq.phase = !aq->sq.phase; in __efa_com_submit_admin_cmd()
350 writel(aq->sq.pc, aq->sq.db_addr); in __efa_com_submit_admin_cmd()
357 size_t pool_size = aq->depth * sizeof(*aq->comp_ctx_pool); in efa_com_init_comp_ctxt()
358 size_t size = aq->depth * sizeof(struct efa_comp_ctx); in efa_com_init_comp_ctxt()
362 aq->comp_ctx = devm_kzalloc(aq->dmadev, size, GFP_KERNEL); in efa_com_init_comp_ctxt()
363 aq->comp_ctx_pool = devm_kzalloc(aq->dmadev, pool_size, GFP_KERNEL); in efa_com_init_comp_ctxt()
364 if (!aq->comp_ctx || !aq->comp_ctx_pool) { in efa_com_init_comp_ctxt()
365 devm_kfree(aq->dmadev, aq->comp_ctx_pool); in efa_com_init_comp_ctxt()
366 devm_kfree(aq->dmadev, aq->comp_ctx); in efa_com_init_comp_ctxt()
367 return -ENOMEM; in efa_com_init_comp_ctxt()
370 for (i = 0; i < aq->depth; i++) { in efa_com_init_comp_ctxt()
373 init_completion(&comp_ctx->wait_event); in efa_com_init_comp_ctxt()
375 aq->comp_ctx_pool[i] = i; in efa_com_init_comp_ctxt()
378 spin_lock_init(&aq->comp_ctx_lock); in efa_com_init_comp_ctxt()
380 aq->comp_ctx_pool_next = 0; in efa_com_init_comp_ctxt()
393 spin_lock(&aq->sq.lock); in efa_com_submit_admin_cmd()
394 if (!test_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state)) { in efa_com_submit_admin_cmd()
395 ibdev_err_ratelimited(aq->efa_dev, "Admin queue is closed\n"); in efa_com_submit_admin_cmd()
396 spin_unlock(&aq->sq.lock); in efa_com_submit_admin_cmd()
397 return ERR_PTR(-ENODEV); in efa_com_submit_admin_cmd()
402 spin_unlock(&aq->sq.lock); in efa_com_submit_admin_cmd()
404 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_submit_admin_cmd()
410 struct efa_admin_acq_entry *cqe) in efa_com_handle_single_admin_completion() argument
415 cmd_id = EFA_GET(&cqe->acq_common_descriptor.command, in efa_com_handle_single_admin_completion()
420 ibdev_err(aq->efa_dev, in efa_com_handle_single_admin_completion()
422 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_handle_single_admin_completion()
426 comp_ctx->status = EFA_CMD_COMPLETED; in efa_com_handle_single_admin_completion()
427 memcpy(comp_ctx->user_cqe, cqe, comp_ctx->comp_size); in efa_com_handle_single_admin_completion()
429 if (!test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state)) in efa_com_handle_single_admin_completion()
430 complete(&comp_ctx->wait_event); in efa_com_handle_single_admin_completion()
435 struct efa_admin_acq_entry *cqe; in efa_com_handle_admin_completion() local
441 queue_size_mask = aq->depth - 1; in efa_com_handle_admin_completion()
443 ci = aq->cq.cc & queue_size_mask; in efa_com_handle_admin_completion()
444 phase = aq->cq.phase; in efa_com_handle_admin_completion()
446 cqe = &aq->cq.entries[ci]; in efa_com_handle_admin_completion()
449 while ((READ_ONCE(cqe->acq_common_descriptor.flags) & in efa_com_handle_admin_completion()
456 efa_com_handle_single_admin_completion(aq, cqe); in efa_com_handle_admin_completion()
460 if (ci == aq->depth) { in efa_com_handle_admin_completion()
465 cqe = &aq->cq.entries[ci]; in efa_com_handle_admin_completion()
468 aq->cq.cc += comp_num; in efa_com_handle_admin_completion()
469 aq->cq.phase = phase; in efa_com_handle_admin_completion()
470 aq->sq.cc += comp_num; in efa_com_handle_admin_completion()
471 atomic64_add(comp_num, &aq->stats.completed_cmd); in efa_com_handle_admin_completion()
480 return -ENOMEM; in efa_com_comp_status_to_errno()
482 return -EOPNOTSUPP; in efa_com_comp_status_to_errno()
487 return -EINVAL; in efa_com_comp_status_to_errno()
489 return -EINVAL; in efa_com_comp_status_to_errno()
500 timeout = jiffies + usecs_to_jiffies(aq->completion_timeout); in efa_com_wait_and_process_admin_cq_polling()
503 spin_lock_irqsave(&aq->cq.lock, flags); in efa_com_wait_and_process_admin_cq_polling()
505 spin_unlock_irqrestore(&aq->cq.lock, flags); in efa_com_wait_and_process_admin_cq_polling()
507 if (comp_ctx->status != EFA_CMD_SUBMITTED) in efa_com_wait_and_process_admin_cq_polling()
512 aq->efa_dev, in efa_com_wait_and_process_admin_cq_polling()
515 atomic64_inc(&aq->stats.no_completion); in efa_com_wait_and_process_admin_cq_polling()
517 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_wait_and_process_admin_cq_polling()
518 err = -ETIME; in efa_com_wait_and_process_admin_cq_polling()
522 msleep(aq->poll_interval); in efa_com_wait_and_process_admin_cq_polling()
525 err = efa_com_comp_status_to_errno(comp_ctx->user_cqe->acq_common_descriptor.status); in efa_com_wait_and_process_admin_cq_polling()
537 wait_for_completion_timeout(&comp_ctx->wait_event, in efa_com_wait_and_process_admin_cq_interrupts()
538 usecs_to_jiffies(aq->completion_timeout)); in efa_com_wait_and_process_admin_cq_interrupts()
544 * 2) There is completion but the device didn't get any msi-x interrupt. in efa_com_wait_and_process_admin_cq_interrupts()
546 if (comp_ctx->status == EFA_CMD_SUBMITTED) { in efa_com_wait_and_process_admin_cq_interrupts()
547 spin_lock_irqsave(&aq->cq.lock, flags); in efa_com_wait_and_process_admin_cq_interrupts()
549 spin_unlock_irqrestore(&aq->cq.lock, flags); in efa_com_wait_and_process_admin_cq_interrupts()
551 atomic64_inc(&aq->stats.no_completion); in efa_com_wait_and_process_admin_cq_interrupts()
553 if (comp_ctx->status == EFA_CMD_COMPLETED) in efa_com_wait_and_process_admin_cq_interrupts()
555 aq->efa_dev, in efa_com_wait_and_process_admin_cq_interrupts()
556 …"The device sent a completion but the driver didn't receive any MSI-X interrupt for admin cmd %s(%… in efa_com_wait_and_process_admin_cq_interrupts()
557 efa_com_cmd_str(comp_ctx->cmd_opcode), in efa_com_wait_and_process_admin_cq_interrupts()
558 comp_ctx->cmd_opcode, comp_ctx->status, in efa_com_wait_and_process_admin_cq_interrupts()
559 comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc); in efa_com_wait_and_process_admin_cq_interrupts()
562 aq->efa_dev, in efa_com_wait_and_process_admin_cq_interrupts()
564 efa_com_cmd_str(comp_ctx->cmd_opcode), in efa_com_wait_and_process_admin_cq_interrupts()
565 comp_ctx->cmd_opcode, comp_ctx->status, in efa_com_wait_and_process_admin_cq_interrupts()
566 comp_ctx, aq->sq.pc, aq->sq.cc, aq->cq.cc); in efa_com_wait_and_process_admin_cq_interrupts()
568 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_wait_and_process_admin_cq_interrupts()
569 err = -ETIME; in efa_com_wait_and_process_admin_cq_interrupts()
573 err = efa_com_comp_status_to_errno(comp_ctx->user_cqe->acq_common_descriptor.status); in efa_com_wait_and_process_admin_cq_interrupts()
581 * Polling mode - wait until the completion is available.
582 * Async mode - wait on wait queue until the completion is ready
590 if (test_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state)) in efa_com_wait_and_process_admin_cq()
597 * efa_com_cmd_exec - Execute admin command
607 * @return - 0 on success, negative value on failure.
621 down(&aq->avail_cmds); in efa_com_cmd_exec()
623 ibdev_dbg(aq->efa_dev, "%s (opcode %d)\n", in efa_com_cmd_exec()
624 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), in efa_com_cmd_exec()
625 cmd->aq_common_descriptor.opcode); in efa_com_cmd_exec()
629 aq->efa_dev, in efa_com_cmd_exec()
631 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), in efa_com_cmd_exec()
632 cmd->aq_common_descriptor.opcode, PTR_ERR(comp_ctx)); in efa_com_cmd_exec()
634 up(&aq->avail_cmds); in efa_com_cmd_exec()
635 atomic64_inc(&aq->stats.cmd_err); in efa_com_cmd_exec()
642 aq->efa_dev, in efa_com_cmd_exec()
644 efa_com_cmd_str(cmd->aq_common_descriptor.opcode), in efa_com_cmd_exec()
645 cmd->aq_common_descriptor.opcode, in efa_com_cmd_exec()
646 comp_ctx->user_cqe->acq_common_descriptor.status, err); in efa_com_cmd_exec()
647 atomic64_inc(&aq->stats.cmd_err); in efa_com_cmd_exec()
650 up(&aq->avail_cmds); in efa_com_cmd_exec()
656 * efa_com_admin_destroy - Destroy the admin and the async events queues.
661 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_destroy()
662 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_admin_destroy()
663 struct efa_com_admin_cq *cq = &aq->cq; in efa_com_admin_destroy()
664 struct efa_com_admin_sq *sq = &aq->sq; in efa_com_admin_destroy()
667 clear_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_admin_destroy()
669 devm_kfree(edev->dmadev, aq->comp_ctx_pool); in efa_com_admin_destroy()
670 devm_kfree(edev->dmadev, aq->comp_ctx); in efa_com_admin_destroy()
672 size = aq->depth * sizeof(*sq->entries); in efa_com_admin_destroy()
673 dma_free_coherent(edev->dmadev, size, sq->entries, sq->dma_addr); in efa_com_admin_destroy()
675 size = aq->depth * sizeof(*cq->entries); in efa_com_admin_destroy()
676 dma_free_coherent(edev->dmadev, size, cq->entries, cq->dma_addr); in efa_com_admin_destroy()
678 size = aenq->depth * sizeof(*aenq->entries); in efa_com_admin_destroy()
679 dma_free_coherent(edev->dmadev, size, aenq->entries, aenq->dma_addr); in efa_com_admin_destroy()
683 * efa_com_set_admin_polling_mode - Set the admin completion queue polling mode
696 writel(mask_value, edev->reg_bar + EFA_REGS_INTR_MASK_OFF); in efa_com_set_admin_polling_mode()
698 set_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state); in efa_com_set_admin_polling_mode()
700 clear_bit(EFA_AQ_STATE_POLLING_BIT, &edev->aq.state); in efa_com_set_admin_polling_mode()
705 atomic64_t *s = (atomic64_t *)&edev->aq.stats; in efa_com_stats_init()
708 for (i = 0; i < sizeof(edev->aq.stats) / sizeof(*s); i++, s++) in efa_com_stats_init()
713 * efa_com_admin_init - Init the admin and the async queues
720 * @return - 0 on success, negative value on failure.
725 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_admin_init()
733 ibdev_err(edev->efa_dev, in efa_com_admin_init()
735 return -ENODEV; in efa_com_admin_init()
738 aq->depth = EFA_ADMIN_QUEUE_DEPTH; in efa_com_admin_init()
740 aq->dmadev = edev->dmadev; in efa_com_admin_init()
741 aq->efa_dev = edev->efa_dev; in efa_com_admin_init()
742 set_bit(EFA_AQ_STATE_POLLING_BIT, &aq->state); in efa_com_admin_init()
744 sema_init(&aq->avail_cmds, aq->depth); in efa_com_admin_init()
770 aq->completion_timeout = timeout * 100000; in efa_com_admin_init()
772 aq->completion_timeout = ADMIN_CMD_TIMEOUT_US; in efa_com_admin_init()
774 aq->poll_interval = EFA_POLL_INTERVAL_MS; in efa_com_admin_init()
776 set_bit(EFA_AQ_STATE_RUNNING_BIT, &aq->state); in efa_com_admin_init()
781 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->cq.entries), in efa_com_admin_init()
782 aq->cq.entries, aq->cq.dma_addr); in efa_com_admin_init()
784 dma_free_coherent(edev->dmadev, aq->depth * sizeof(*aq->sq.entries), in efa_com_admin_init()
785 aq->sq.entries, aq->sq.dma_addr); in efa_com_admin_init()
787 devm_kfree(edev->dmadev, aq->comp_ctx); in efa_com_admin_init()
793 * efa_com_admin_q_comp_intr_handler - admin queue interrupt handler
799 * Note: Should be called after MSI-X interrupt.
805 spin_lock_irqsave(&edev->aq.cq.lock, flags); in efa_com_admin_q_comp_intr_handler()
806 efa_com_handle_admin_completion(&edev->aq); in efa_com_admin_q_comp_intr_handler()
807 spin_unlock_irqrestore(&edev->aq.cq.lock, flags); in efa_com_admin_q_comp_intr_handler()
817 struct efa_aenq_handlers *aenq_handlers = edev->aenq.aenq_handlers; in efa_com_get_specific_aenq_cb()
819 if (group < EFA_MAX_HANDLERS && aenq_handlers->handlers[group]) in efa_com_get_specific_aenq_cb()
820 return aenq_handlers->handlers[group]; in efa_com_get_specific_aenq_cb()
822 return aenq_handlers->unimplemented_handler; in efa_com_get_specific_aenq_cb()
826 * efa_com_aenq_intr_handler - AENQ interrupt handler
835 struct efa_com_aenq *aenq = &edev->aenq; in efa_com_aenq_intr_handler()
842 ci = aenq->cc & (aenq->depth - 1); in efa_com_aenq_intr_handler()
843 phase = aenq->phase; in efa_com_aenq_intr_handler()
844 aenq_e = &aenq->entries[ci]; /* Get first entry */ in efa_com_aenq_intr_handler()
845 aenq_common = &aenq_e->aenq_common_desc; in efa_com_aenq_intr_handler()
848 while ((READ_ONCE(aenq_common->flags) & in efa_com_aenq_intr_handler()
858 aenq_common->group); in efa_com_aenq_intr_handler()
865 if (ci == aenq->depth) { in efa_com_aenq_intr_handler()
869 aenq_e = &aenq->entries[ci]; in efa_com_aenq_intr_handler()
870 aenq_common = &aenq_e->aenq_common_desc; in efa_com_aenq_intr_handler()
873 aenq->cc += processed; in efa_com_aenq_intr_handler()
874 aenq->phase = phase; in efa_com_aenq_intr_handler()
881 writel(aenq->cc, edev->reg_bar + EFA_REGS_AENQ_CONS_DB_OFF); in efa_com_aenq_intr_handler()
886 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; in efa_com_mmio_reg_read_resp_addr_init()
891 addr_high = (mmio_read->read_resp_dma_addr >> 32) & GENMASK(31, 0); in efa_com_mmio_reg_read_resp_addr_init()
892 addr_low = mmio_read->read_resp_dma_addr & GENMASK(31, 0); in efa_com_mmio_reg_read_resp_addr_init()
894 writel(addr_high, edev->reg_bar + EFA_REGS_MMIO_RESP_HI_OFF); in efa_com_mmio_reg_read_resp_addr_init()
895 writel(addr_low, edev->reg_bar + EFA_REGS_MMIO_RESP_LO_OFF); in efa_com_mmio_reg_read_resp_addr_init()
900 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; in efa_com_mmio_reg_read_init()
902 spin_lock_init(&mmio_read->lock); in efa_com_mmio_reg_read_init()
903 mmio_read->read_resp = in efa_com_mmio_reg_read_init()
904 dma_alloc_coherent(edev->dmadev, sizeof(*mmio_read->read_resp), in efa_com_mmio_reg_read_init()
905 &mmio_read->read_resp_dma_addr, GFP_KERNEL); in efa_com_mmio_reg_read_init()
906 if (!mmio_read->read_resp) in efa_com_mmio_reg_read_init()
907 return -ENOMEM; in efa_com_mmio_reg_read_init()
911 mmio_read->read_resp->req_id = 0; in efa_com_mmio_reg_read_init()
912 mmio_read->seq_num = 0; in efa_com_mmio_reg_read_init()
913 mmio_read->mmio_read_timeout = EFA_REG_READ_TIMEOUT_US; in efa_com_mmio_reg_read_init()
920 struct efa_com_mmio_read *mmio_read = &edev->mmio_read; in efa_com_mmio_reg_read_destroy()
922 dma_free_coherent(edev->dmadev, sizeof(*mmio_read->read_resp), in efa_com_mmio_reg_read_destroy()
923 mmio_read->read_resp, mmio_read->read_resp_dma_addr); in efa_com_mmio_reg_read_destroy()
942 ibdev_dbg(edev->efa_dev, "efa device version: %d.%d\n", in efa_com_validate_version()
951 ibdev_err(edev->efa_dev, in efa_com_validate_version()
952 "EFA version is lower than the minimal version the driver supports\n"); in efa_com_validate_version()
953 return -EOPNOTSUPP; in efa_com_validate_version()
957 edev->efa_dev, in efa_com_validate_version()
979 ibdev_err(edev->efa_dev, in efa_com_validate_version()
980 "EFA ctrl version is lower than the minimal ctrl version the driver supports\n"); in efa_com_validate_version()
981 return -EOPNOTSUPP; in efa_com_validate_version()
988 * efa_com_get_dma_width - Retrieve physical dma address width the device
989 * supports.
1003 ibdev_dbg(edev->efa_dev, "DMA width: %d\n", width); in efa_com_get_dma_width()
1006 ibdev_err(edev->efa_dev, "DMA width illegal value: %d\n", width); in efa_com_get_dma_width()
1007 return -EINVAL; in efa_com_get_dma_width()
1010 edev->dma_addr_bits = width; in efa_com_get_dma_width()
1025 ibdev_dbg(edev->efa_dev, "Reset indication val %d\n", val); in wait_for_reset_state()
1029 return -ETIME; in wait_for_reset_state()
1033 * efa_com_dev_reset - Perform device FLR to the device.
1037 * @return - 0 on success, negative value on failure.
1050 ibdev_err(edev->efa_dev, in efa_com_dev_reset()
1052 return -EINVAL; in efa_com_dev_reset()
1057 ibdev_err(edev->efa_dev, "Invalid timeout value\n"); in efa_com_dev_reset()
1058 return -EINVAL; in efa_com_dev_reset()
1064 writel(reset_val, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); in efa_com_dev_reset()
1071 ibdev_err(edev->efa_dev, "Reset indication didn't turn on\n"); in efa_com_dev_reset()
1076 writel(0, edev->reg_bar + EFA_REGS_DEV_CTL_OFF); in efa_com_dev_reset()
1079 ibdev_err(edev->efa_dev, "Reset indication didn't turn off\n"); in efa_com_dev_reset()
1086 edev->aq.completion_timeout = timeout * 100000; in efa_com_dev_reset()
1088 edev->aq.completion_timeout = ADMIN_CMD_TIMEOUT_US; in efa_com_dev_reset()
1097 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_create_eq()
1104 params->entry_size_in_bytes / 4); in efa_com_create_eq()
1105 cmd.depth = params->depth; in efa_com_create_eq()
1106 cmd.event_bitmask = params->event_bitmask; in efa_com_create_eq()
1107 cmd.msix_vec = params->msix_vec; in efa_com_create_eq()
1109 efa_com_set_dma_addr(params->dma_addr, &cmd.ba.mem_addr_high, in efa_com_create_eq()
1118 ibdev_err_ratelimited(edev->efa_dev, in efa_com_create_eq()
1123 result->eqn = resp.eqn; in efa_com_create_eq()
1131 struct efa_com_admin_queue *aq = &edev->aq; in efa_com_destroy_eq()
1137 cmd.eqn = params->eqn; in efa_com_destroy_eq()
1145 ibdev_err_ratelimited(edev->efa_dev, in efa_com_destroy_eq()
1146 "Failed to destroy EQ-%u [%d]\n", cmd.eqn, in efa_com_destroy_eq()
1154 EFA_SET(&val, EFA_REGS_EQ_DB_EQN, eeq->eqn); in efa_com_arm_eq()
1157 writel(val, edev->reg_bar + EFA_REGS_EQ_DB_OFF); in efa_com_arm_eq()
1168 ci = eeq->cc & (eeq->depth - 1); in efa_com_eq_comp_intr_handler()
1169 phase = eeq->phase; in efa_com_eq_comp_intr_handler()
1170 eqe = &eeq->eqes[ci]; in efa_com_eq_comp_intr_handler()
1173 while ((READ_ONCE(eqe->common) & EFA_ADMIN_EQE_PHASE_MASK) == phase) { in efa_com_eq_comp_intr_handler()
1180 eeq->cb(eeq, eqe); in efa_com_eq_comp_intr_handler()
1186 if (ci == eeq->depth) { in efa_com_eq_comp_intr_handler()
1191 eqe = &eeq->eqes[ci]; in efa_com_eq_comp_intr_handler()
1194 eeq->cc += processed; in efa_com_eq_comp_intr_handler()
1195 eeq->phase = phase; in efa_com_eq_comp_intr_handler()
1196 efa_com_arm_eq(eeq->edev, eeq); in efa_com_eq_comp_intr_handler()
1202 .eqn = eeq->eqn, in efa_com_eq_destroy()
1206 dma_free_coherent(edev->dmadev, eeq->depth * sizeof(*eeq->eqes), in efa_com_eq_destroy()
1207 eeq->eqes, eeq->dma_addr); in efa_com_eq_destroy()
1218 params.entry_size_in_bytes = sizeof(*eeq->eqes); in efa_com_eq_init()
1223 eeq->eqes = dma_alloc_coherent(edev->dmadev, in efa_com_eq_init()
1224 params.depth * sizeof(*eeq->eqes), in efa_com_eq_init()
1226 if (!eeq->eqes) in efa_com_eq_init()
1227 return -ENOMEM; in efa_com_eq_init()
1233 eeq->eqn = result.eqn; in efa_com_eq_init()
1234 eeq->edev = edev; in efa_com_eq_init()
1235 eeq->dma_addr = params.dma_addr; in efa_com_eq_init()
1236 eeq->phase = 1; in efa_com_eq_init()
1237 eeq->depth = params.depth; in efa_com_eq_init()
1238 eeq->cb = cb; in efa_com_eq_init()
1244 dma_free_coherent(edev->dmadev, params.depth * sizeof(*eeq->eqes), in efa_com_eq_init()
1245 eeq->eqes, params.dma_addr); in efa_com_eq_init()