Lines Matching full:adc
106 int (*config)(struct mcp3911 *adc);
107 int (*get_osr)(struct mcp3911 *adc, u32 *val);
108 int (*set_osr)(struct mcp3911 *adc, u32 val);
109 int (*enable_offset)(struct mcp3911 *adc, bool enable);
110 int (*get_offset)(struct mcp3911 *adc, int channel, int *val);
111 int (*set_offset)(struct mcp3911 *adc, int channel, int val);
112 int (*set_scale)(struct mcp3911 *adc, int channel, u32 val);
133 static int mcp3911_read(struct mcp3911 *adc, u8 reg, u32 *val, u8 len) in mcp3911_read() argument
137 reg = MCP3911_REG_READ(reg, adc->dev_addr); in mcp3911_read()
138 ret = spi_write_then_read(adc->spi, ®, 1, val, len); in mcp3911_read()
144 dev_dbg(&adc->spi->dev, "reading 0x%x from register 0x%lx\n", *val, in mcp3911_read()
149 static int mcp3911_write(struct mcp3911 *adc, u8 reg, u32 val, u8 len) in mcp3911_write() argument
151 dev_dbg(&adc->spi->dev, "writing 0x%x to register 0x%x\n", val, reg); in mcp3911_write()
155 val |= MCP3911_REG_WRITE(reg, adc->dev_addr); in mcp3911_write()
157 return spi_write(adc->spi, &val, len + 1); in mcp3911_write()
160 static int mcp3911_update(struct mcp3911 *adc, u8 reg, u32 mask, u32 val, u8 len) in mcp3911_update() argument
165 ret = mcp3911_read(adc, reg, &tmp, len); in mcp3911_update()
171 return mcp3911_write(adc, reg, val, len); in mcp3911_update()
174 static int mcp3910_enable_offset(struct mcp3911 *adc, bool enable) in mcp3910_enable_offset() argument
179 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, value, 3); in mcp3910_enable_offset()
182 static int mcp3910_get_offset(struct mcp3911 *adc, int channel, int *val) in mcp3910_get_offset() argument
184 return mcp3911_read(adc, MCP3910_OFFCAL(channel), val, 3); in mcp3910_get_offset()
187 static int mcp3910_set_offset(struct mcp3911 *adc, int channel, int val) in mcp3910_set_offset() argument
191 ret = mcp3911_write(adc, MCP3910_OFFCAL(channel), val, 3); in mcp3910_set_offset()
195 return adc->chip->enable_offset(adc, 1); in mcp3910_set_offset()
198 static int mcp3911_enable_offset(struct mcp3911 *adc, bool enable) in mcp3911_enable_offset() argument
203 return mcp3911_update(adc, MCP3911_REG_STATUSCOM, mask, value, 2); in mcp3911_enable_offset()
206 static int mcp3911_get_offset(struct mcp3911 *adc, int channel, int *val) in mcp3911_get_offset() argument
208 return mcp3911_read(adc, MCP3911_OFFCAL(channel), val, 3); in mcp3911_get_offset()
211 static int mcp3911_set_offset(struct mcp3911 *adc, int channel, int val) in mcp3911_set_offset() argument
215 ret = mcp3911_write(adc, MCP3911_OFFCAL(channel), val, 3); in mcp3911_set_offset()
219 return adc->chip->enable_offset(adc, 1); in mcp3911_set_offset()
222 static int mcp3910_get_osr(struct mcp3911 *adc, u32 *val) in mcp3910_get_osr() argument
227 ret = mcp3911_read(adc, MCP3910_REG_CONFIG0, val, 3); in mcp3910_get_osr()
236 static int mcp3910_set_osr(struct mcp3911 *adc, u32 val) in mcp3910_set_osr() argument
241 return mcp3911_update(adc, MCP3910_REG_CONFIG0, mask, osr, 3); in mcp3910_set_osr()
244 static int mcp3911_set_osr(struct mcp3911 *adc, u32 val) in mcp3911_set_osr() argument
249 return mcp3911_update(adc, MCP3911_REG_CONFIG, mask, osr, 2); in mcp3911_set_osr()
252 static int mcp3911_get_osr(struct mcp3911 *adc, u32 *val) in mcp3911_get_osr() argument
257 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, val, 2); in mcp3911_get_osr()
266 static int mcp3910_set_scale(struct mcp3911 *adc, int channel, u32 val) in mcp3910_set_scale() argument
268 return mcp3911_update(adc, MCP3910_REG_GAIN, in mcp3910_set_scale()
273 static int mcp3911_set_scale(struct mcp3911 *adc, int channel, u32 val) in mcp3911_set_scale() argument
275 return mcp3911_update(adc, MCP3911_REG_GAIN, in mcp3911_set_scale()
319 struct mcp3911 *adc = iio_priv(indio_dev); in mcp3911_read_raw() local
322 guard(mutex)(&adc->lock); in mcp3911_read_raw()
325 ret = mcp3911_read(adc, in mcp3911_read_raw()
333 ret = adc->chip->get_offset(adc, channel->channel, val); in mcp3911_read_raw()
339 ret = adc->chip->get_osr(adc, val); in mcp3911_read_raw()
345 *val = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][0]; in mcp3911_read_raw()
346 *val2 = mcp3911_scale_table[ilog2(adc->gain[channel->channel])][1]; in mcp3911_read_raw()
357 struct mcp3911 *adc = iio_priv(indio_dev); in mcp3911_write_raw() local
359 guard(mutex)(&adc->lock); in mcp3911_write_raw()
366 adc->gain[channel->channel] = BIT(i); in mcp3911_write_raw()
367 return adc->chip->set_scale(adc, channel->channel, i); in mcp3911_write_raw()
375 return adc->chip->set_offset(adc, channel->channel, val); in mcp3911_write_raw()
379 return adc->chip->set_osr(adc, i); in mcp3911_write_raw()
388 static int mcp3911_calc_scale_table(struct mcp3911 *adc) in mcp3911_calc_scale_table() argument
390 struct device *dev = &adc->spi->dev; in mcp3911_calc_scale_table()
396 if (adc->vref) { in mcp3911_calc_scale_table()
397 ret = regulator_get_voltage(adc->vref); in mcp3911_calc_scale_table()
503 struct mcp3911 *adc = iio_priv(indio_dev); in mcp3911_trigger_handler() local
504 struct device *dev = &adc->spi->dev; in mcp3911_trigger_handler()
507 .tx_buf = &adc->tx_buf, in mcp3911_trigger_handler()
510 .rx_buf = adc->rx_buf, in mcp3911_trigger_handler()
511 .len = (adc->chip->num_channels - 1) * 3, in mcp3911_trigger_handler()
518 guard(mutex)(&adc->lock); in mcp3911_trigger_handler()
519 adc->tx_buf = MCP3911_REG_READ(MCP3911_CHANNEL(0), adc->dev_addr); in mcp3911_trigger_handler()
520 ret = spi_sync_transfer(adc->spi, xfer, ARRAY_SIZE(xfer)); in mcp3911_trigger_handler()
529 adc->scan.channels[i] = get_unaligned_be24(&adc->rx_buf[scan_chan->channel * 3]); in mcp3911_trigger_handler()
532 iio_push_to_buffers_with_timestamp(indio_dev, &adc->scan, in mcp3911_trigger_handler()
547 static int mcp3911_config(struct mcp3911 *adc) in mcp3911_config() argument
549 struct device *dev = &adc->spi->dev; in mcp3911_config()
553 ret = mcp3911_read(adc, MCP3911_REG_CONFIG, ®val, 2); in mcp3911_config()
558 if (adc->vref) { in mcp3911_config()
567 if (adc->clki) { in mcp3911_config()
575 ret = mcp3911_write(adc, MCP3911_REG_CONFIG, regval, 2); in mcp3911_config()
579 ret = mcp3911_read(adc, MCP3911_REG_STATUSCOM, ®val, 2); in mcp3911_config()
596 ret = mcp3911_write(adc, MCP3911_REG_STATUSCOM, regval, 2); in mcp3911_config()
601 ret = mcp3911_read(adc, MCP3911_REG_GAIN, ®val, 1); in mcp3911_config()
605 for (int i = 0; i < adc->chip->num_channels - 1; i++) { in mcp3911_config()
606 adc->gain[i] = 1; in mcp3911_config()
610 return mcp3911_write(adc, MCP3911_REG_GAIN, regval, 1); in mcp3911_config()
613 static int mcp3910_config(struct mcp3911 *adc) in mcp3910_config() argument
615 struct device *dev = &adc->spi->dev; in mcp3910_config()
619 ret = mcp3911_read(adc, MCP3910_REG_CONFIG1, ®val, 3); in mcp3910_config()
624 if (adc->vref) { in mcp3910_config()
633 if (adc->clki) { in mcp3910_config()
641 ret = mcp3911_write(adc, MCP3910_REG_CONFIG1, regval, 3); in mcp3910_config()
645 ret = mcp3911_read(adc, MCP3910_REG_STATUSCOM, ®val, 3); in mcp3910_config()
659 ret = mcp3911_write(adc, MCP3910_REG_STATUSCOM, regval, 3); in mcp3910_config()
664 ret = mcp3911_read(adc, MCP3910_REG_GAIN, ®val, 3); in mcp3910_config()
668 for (int i = 0; i < adc->chip->num_channels - 1; i++) { in mcp3910_config()
669 adc->gain[i] = 1; in mcp3910_config()
672 ret = mcp3911_write(adc, MCP3910_REG_GAIN, regval, 3); in mcp3910_config()
677 return adc->chip->enable_offset(adc, 0); in mcp3910_config()
687 struct mcp3911 *adc = iio_trigger_get_drvdata(trig); in mcp3911_set_trigger_state() local
690 enable_irq(adc->spi->irq); in mcp3911_set_trigger_state()
692 disable_irq(adc->spi->irq); in mcp3911_set_trigger_state()
706 struct mcp3911 *adc; in mcp3911_probe() local
709 indio_dev = devm_iio_device_alloc(dev, sizeof(*adc)); in mcp3911_probe()
713 adc = iio_priv(indio_dev); in mcp3911_probe()
714 adc->spi = spi; in mcp3911_probe()
715 adc->chip = spi_get_device_match_data(spi); in mcp3911_probe()
717 adc->vref = devm_regulator_get_optional(dev, "vref"); in mcp3911_probe()
718 if (IS_ERR(adc->vref)) { in mcp3911_probe()
719 if (PTR_ERR(adc->vref) == -ENODEV) { in mcp3911_probe()
720 adc->vref = NULL; in mcp3911_probe()
722 return dev_err_probe(dev, PTR_ERR(adc->vref), "failed to get regulator\n"); in mcp3911_probe()
726 ret = regulator_enable(adc->vref); in mcp3911_probe()
730 ret = devm_add_action_or_reset(dev, mcp3911_cleanup_regulator, adc->vref); in mcp3911_probe()
735 adc->clki = devm_clk_get_enabled(dev, NULL); in mcp3911_probe()
736 if (IS_ERR(adc->clki)) { in mcp3911_probe()
737 if (PTR_ERR(adc->clki) == -ENOENT) { in mcp3911_probe()
738 adc->clki = NULL; in mcp3911_probe()
740 return dev_err_probe(dev, PTR_ERR(adc->clki), "failed to get adc clk\n"); in mcp3911_probe()
748 ret = device_property_read_u32(dev, "microchip,device-addr", &adc->dev_addr); in mcp3911_probe()
750 device_property_read_u32(dev, "device-addr", &adc->dev_addr); in mcp3911_probe()
751 if (adc->dev_addr > 3) { in mcp3911_probe()
754 adc->dev_addr); in mcp3911_probe()
756 dev_dbg(dev, "use device address %i\n", adc->dev_addr); in mcp3911_probe()
758 ret = adc->chip->config(adc); in mcp3911_probe()
762 ret = mcp3911_calc_scale_table(adc); in mcp3911_probe()
767 for (int i = 0; i < adc->chip->num_channels - 1; i++) { in mcp3911_probe()
768 adc->gain[i] = 1; in mcp3911_probe()
769 ret = mcp3911_update(adc, MCP3911_REG_GAIN, in mcp3911_probe()
781 indio_dev->channels = adc->chip->channels; in mcp3911_probe()
782 indio_dev->num_channels = adc->chip->num_channels; in mcp3911_probe()
784 mutex_init(&adc->lock); in mcp3911_probe()
787 adc->trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, in mcp3911_probe()
789 if (!adc->trig) in mcp3911_probe()
792 adc->trig->ops = &mcp3911_trigger_ops; in mcp3911_probe()
793 iio_trigger_set_drvdata(adc->trig, adc); in mcp3911_probe()
794 ret = devm_iio_trigger_register(dev, adc->trig); in mcp3911_probe()
805 indio_dev->name, adc->trig); in mcp3911_probe()