Lines Matching +full:1 +full:st
33 #define AD7192_REG_MODE 1 /* Mode Register (RW, 24-bit */
56 #define AD7192_STAT_CH2 BIT(1) /* Channel 2 */
57 #define AD7192_STAT_CH1 BIT(0) /* Channel 1 */
75 #define AD7192_MODE_SINGLE 1 /* Single Conversion Mode */
86 #define AD7192_CLK_EXT_MCLK2 1 /* External Clock applied to MCLK2 */
105 #define AD7192_CH_AIN3P_AIN4M BIT(1) /* AIN3(+) - AIN4(-) */
142 #define AD7192_GPOCON_P1DAT BIT(1) /* P1 state */
149 #define AD7192_NO_SYNC_FILTER 1
209 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set_syscalib_mode() local
211 st->syscalib_mode[chan->channel] = mode; in ad7192_set_syscalib_mode()
219 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_get_syscalib_mode() local
221 return st->syscalib_mode[chan->channel]; in ad7192_get_syscalib_mode()
229 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_write_syscalib() local
237 temp = st->syscalib_mode[chan->channel]; in ad7192_write_syscalib()
240 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_ZERO, in ad7192_write_syscalib()
243 ret = ad_sd_calibrate(&st->sd, AD7192_MODE_CAL_SYS_FULL, in ad7192_write_syscalib()
277 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_channel() local
279 st->conf &= ~AD7192_CONF_CHAN_MASK; in ad7192_set_channel()
280 st->conf |= FIELD_PREP(AD7192_CONF_CHAN_MASK, channel); in ad7192_set_channel()
282 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_channel()
288 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_set_mode() local
290 st->mode &= ~AD7192_MODE_SEL_MASK; in ad7192_set_mode()
291 st->mode |= FIELD_PREP(AD7192_MODE_SEL_MASK, mode); in ad7192_set_mode()
293 return ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_mode()
298 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_append_status() local
299 unsigned int mode = st->mode; in ad7192_append_status()
305 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, mode); in ad7192_append_status()
309 st->mode = mode; in ad7192_append_status()
316 struct ad7192_state *st = ad_sigma_delta_to_ad7192(sd); in ad7192_disable_all() local
317 u32 conf = st->conf; in ad7192_disable_all()
322 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_disable_all()
326 st->conf = conf; in ad7192_disable_all()
355 static int ad7192_calibrate_all(struct ad7192_state *st) in ad7192_calibrate_all() argument
357 return ad_sd_calibrate_all(&st->sd, ad7192_calib_arr, in ad7192_calibrate_all()
367 static int ad7192_of_clock_select(struct ad7192_state *st) in ad7192_of_clock_select() argument
369 struct device_node *np = st->sd.spi->dev.of_node; in ad7192_of_clock_select()
375 if (!st->mclk) { in ad7192_of_clock_select()
390 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_setup() local
397 ret = ad_sd_reset(&st->sd, 48); in ad7192_setup()
403 ret = ad_sd_read_reg(&st->sd, AD7192_REG_ID, 1, &id); in ad7192_setup()
409 if (id != st->chip_info->chip_id) in ad7192_setup()
410 dev_warn(&st->sd.spi->dev, "device ID query failed (0x%X != 0x%X)\n", in ad7192_setup()
411 id, st->chip_info->chip_id); in ad7192_setup()
413 st->mode = FIELD_PREP(AD7192_MODE_SEL_MASK, AD7192_MODE_IDLE) | in ad7192_setup()
414 FIELD_PREP(AD7192_MODE_CLKSRC_MASK, st->clock_sel) | in ad7192_setup()
417 st->conf = FIELD_PREP(AD7192_CONF_GAIN_MASK, 0); in ad7192_setup()
421 st->mode |= AD7192_MODE_REJ60; in ad7192_setup()
424 if (refin2_en && st->chip_info->chip_id != CHIPID_AD7195) in ad7192_setup()
425 st->conf |= AD7192_CONF_REFSEL; in ad7192_setup()
427 st->conf &= ~AD7192_CONF_CHOP; in ad7192_setup()
431 st->conf |= AD7192_CONF_BUF; in ad7192_setup()
435 st->conf |= AD7192_CONF_UNIPOLAR; in ad7192_setup()
440 st->conf |= AD7192_CONF_BURN; in ad7192_setup()
442 dev_warn(&st->sd.spi->dev, in ad7192_setup()
446 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_setup()
450 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_setup()
454 ret = ad7192_calibrate_all(st); in ad7192_setup()
459 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) { in ad7192_setup()
460 scale_uv = ((u64)st->int_vref_mv * 100000000) in ad7192_setup()
462 !FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf)); in ad7192_setup()
465 st->scale_avail[i][1] = do_div(scale_uv, 100000000) * 10; in ad7192_setup()
466 st->scale_avail[i][0] = scale_uv; in ad7192_setup()
469 st->oversampling_ratio_avail[0] = 1; in ad7192_setup()
470 st->oversampling_ratio_avail[1] = 2; in ad7192_setup()
471 st->oversampling_ratio_avail[2] = 8; in ad7192_setup()
472 st->oversampling_ratio_avail[3] = 16; in ad7192_setup()
482 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_ac_excitation() local
484 return sysfs_emit(buf, "%ld\n", FIELD_GET(AD7192_CONF_ACX, st->conf)); in ad7192_show_ac_excitation()
492 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_bridge_switch() local
495 FIELD_GET(AD7192_GPOCON_BPDSW, st->gpocon)); in ad7192_show_bridge_switch()
504 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_set() local
520 st->gpocon |= AD7192_GPOCON_BPDSW; in ad7192_set()
522 st->gpocon &= ~AD7192_GPOCON_BPDSW; in ad7192_set()
524 ad_sd_write_reg(&st->sd, AD7192_REG_GPOCON, 1, st->gpocon); in ad7192_set()
528 st->conf |= AD7192_CONF_ACX; in ad7192_set()
530 st->conf &= ~AD7192_CONF_ACX; in ad7192_set()
532 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set()
543 static int ad7192_compute_f_order(struct ad7192_state *st, bool sinc3_en, bool chop_en) in ad7192_compute_f_order() argument
547 avg_factor_selected = FIELD_GET(AD7192_MODE_AVG_MASK, st->mode); in ad7192_compute_f_order()
550 return 1; in ad7192_compute_f_order()
552 oversampling_ratio = st->oversampling_ratio_avail[avg_factor_selected]; in ad7192_compute_f_order()
555 return AD7192_SYNC3_FILTER + oversampling_ratio - 1; in ad7192_compute_f_order()
557 return AD7192_SYNC4_FILTER + oversampling_ratio - 1; in ad7192_compute_f_order()
560 static int ad7192_get_f_order(struct ad7192_state *st) in ad7192_get_f_order() argument
564 sinc3_en = FIELD_GET(AD7192_MODE_SINC3, st->mode); in ad7192_get_f_order()
565 chop_en = FIELD_GET(AD7192_CONF_CHOP, st->conf); in ad7192_get_f_order()
567 return ad7192_compute_f_order(st, sinc3_en, chop_en); in ad7192_get_f_order()
570 static int ad7192_compute_f_adc(struct ad7192_state *st, bool sinc3_en, in ad7192_compute_f_adc() argument
573 unsigned int f_order = ad7192_compute_f_order(st, sinc3_en, chop_en); in ad7192_compute_f_adc()
575 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_compute_f_adc()
576 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); in ad7192_compute_f_adc()
579 static int ad7192_get_f_adc(struct ad7192_state *st) in ad7192_get_f_adc() argument
581 unsigned int f_order = ad7192_get_f_order(st); in ad7192_get_f_adc()
583 return DIV_ROUND_CLOSEST(st->fclk, in ad7192_get_f_adc()
584 f_order * FIELD_GET(AD7192_MODE_RATE_MASK, st->mode)); in ad7192_get_f_adc()
587 static void ad7192_get_available_filter_freq(struct ad7192_state *st, in ad7192_get_available_filter_freq() argument
593 fadc = ad7192_compute_f_adc(st, false, true); in ad7192_get_available_filter_freq()
596 fadc = ad7192_compute_f_adc(st, true, true); in ad7192_get_available_filter_freq()
597 freq[1] = DIV_ROUND_CLOSEST(fadc * 240, 1024); in ad7192_get_available_filter_freq()
599 fadc = ad7192_compute_f_adc(st, false, false); in ad7192_get_available_filter_freq()
602 fadc = ad7192_compute_f_adc(st, true, false); in ad7192_get_available_filter_freq()
611 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_show_filter_avail() local
615 ad7192_get_available_filter_freq(st, freq_avail); in ad7192_show_filter_avail()
621 buf[len - 1] = '\n'; in ad7192_show_filter_avail()
663 static int ad7192_set_3db_filter_freq(struct ad7192_state *st, in ad7192_set_3db_filter_freq() argument
673 ad7192_get_available_filter_freq(st, freq_avail); in ad7192_set_3db_filter_freq()
685 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
687 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
689 case 1: in ad7192_set_3db_filter_freq()
690 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
692 st->conf |= AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
695 st->mode &= ~AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
697 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
700 st->mode |= AD7192_MODE_SINC3; in ad7192_set_3db_filter_freq()
702 st->conf &= ~AD7192_CONF_CHOP; in ad7192_set_3db_filter_freq()
706 ret = ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_set_3db_filter_freq()
710 return ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, st->conf); in ad7192_set_3db_filter_freq()
713 static int ad7192_get_3db_filter_freq(struct ad7192_state *st) in ad7192_get_3db_filter_freq() argument
717 fadc = ad7192_get_f_adc(st); in ad7192_get_3db_filter_freq()
719 if (FIELD_GET(AD7192_CONF_CHOP, st->conf)) in ad7192_get_3db_filter_freq()
721 if (FIELD_GET(AD7192_MODE_SINC3, st->mode)) in ad7192_get_3db_filter_freq()
733 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_read_raw() local
734 bool unipolar = FIELD_GET(AD7192_CONF_UNIPOLAR, st->conf); in ad7192_read_raw()
735 u8 gain = FIELD_GET(AD7192_CONF_GAIN_MASK, st->conf); in ad7192_read_raw()
743 mutex_lock(&st->lock); in ad7192_read_raw()
744 *val = st->scale_avail[gain][0]; in ad7192_read_raw()
745 *val2 = st->scale_avail[gain][1]; in ad7192_read_raw()
746 mutex_unlock(&st->lock); in ad7192_read_raw()
757 *val = -(1 << (chan->scan_type.realbits - 1)); in ad7192_read_raw()
765 *val = DIV_ROUND_CLOSEST(ad7192_get_f_adc(st), 1024); in ad7192_read_raw()
768 *val = ad7192_get_3db_filter_freq(st); in ad7192_read_raw()
772 *val = st->oversampling_ratio_avail[FIELD_GET(AD7192_MODE_AVG_MASK, st->mode)]; in ad7192_read_raw()
785 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_write_raw() local
796 mutex_lock(&st->lock); in ad7192_write_raw()
797 for (i = 0; i < ARRAY_SIZE(st->scale_avail); i++) in ad7192_write_raw()
798 if (val2 == st->scale_avail[i][1]) { in ad7192_write_raw()
800 tmp = st->conf; in ad7192_write_raw()
801 st->conf &= ~AD7192_CONF_GAIN_MASK; in ad7192_write_raw()
802 st->conf |= FIELD_PREP(AD7192_CONF_GAIN_MASK, i); in ad7192_write_raw()
803 if (tmp == st->conf) in ad7192_write_raw()
805 ad_sd_write_reg(&st->sd, AD7192_REG_CONF, in ad7192_write_raw()
806 3, st->conf); in ad7192_write_raw()
807 ad7192_calibrate_all(st); in ad7192_write_raw()
810 mutex_unlock(&st->lock); in ad7192_write_raw()
818 div = st->fclk / (val * ad7192_get_f_order(st) * 1024); in ad7192_write_raw()
819 if (div < 1 || div > 1023) { in ad7192_write_raw()
824 st->mode &= ~AD7192_MODE_RATE_MASK; in ad7192_write_raw()
825 st->mode |= FIELD_PREP(AD7192_MODE_RATE_MASK, div); in ad7192_write_raw()
826 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, 3, st->mode); in ad7192_write_raw()
829 ret = ad7192_set_3db_filter_freq(st, val, val2 / 1000); in ad7192_write_raw()
833 mutex_lock(&st->lock); in ad7192_write_raw()
834 for (i = 0; i < ARRAY_SIZE(st->oversampling_ratio_avail); i++) in ad7192_write_raw()
835 if (val == st->oversampling_ratio_avail[i]) { in ad7192_write_raw()
837 tmp = st->mode; in ad7192_write_raw()
838 st->mode &= ~AD7192_MODE_AVG_MASK; in ad7192_write_raw()
839 st->mode |= FIELD_PREP(AD7192_MODE_AVG_MASK, i); in ad7192_write_raw()
840 if (tmp == st->mode) in ad7192_write_raw()
842 ad_sd_write_reg(&st->sd, AD7192_REG_MODE, in ad7192_write_raw()
843 3, st->mode); in ad7192_write_raw()
846 mutex_unlock(&st->lock); in ad7192_write_raw()
880 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_read_avail() local
884 *vals = (int *)st->scale_avail; in ad7192_read_avail()
887 *length = ARRAY_SIZE(st->scale_avail) * 2; in ad7192_read_avail()
891 *vals = (int *)st->oversampling_ratio_avail; in ad7192_read_avail()
893 *length = ARRAY_SIZE(st->oversampling_ratio_avail); in ad7192_read_avail()
903 struct ad7192_state *st = iio_priv(indio_dev); in ad7192_update_scan_mode() local
904 u32 conf = st->conf; in ad7192_update_scan_mode()
912 ret = ad_sd_write_reg(&st->sd, AD7192_REG_CONF, 3, conf); in ad7192_update_scan_mode()
916 st->conf = conf; in ad7192_update_scan_mode()
945 .differential = ((_channel2) == -1 ? 0 : 1), \
946 .indexed = 1, \
973 __AD719x_CHANNEL(_si, _channel1, -1, _address, IIO_VOLTAGE, 0, \
977 __AD719x_CHANNEL(_si, 0, -1, _address, IIO_TEMP, 0, 0, 0, NULL)
988 AD7193_DIFF_CHANNEL(_si, _channel1, -1, _address)
991 AD719x_DIFF_CHANNEL(0, 1, 2, AD7192_CH_AIN1P_AIN2M),
992 AD719x_DIFF_CHANNEL(1, 3, 4, AD7192_CH_AIN3P_AIN4M),
995 AD719x_CHANNEL(4, 1, AD7192_CH_AIN1),
1003 AD7193_DIFF_CHANNEL(0, 1, 2, AD7193_CH_AIN1P_AIN2M),
1004 AD7193_DIFF_CHANNEL(1, 3, 4, AD7193_CH_AIN3P_AIN4M),
1009 AD7193_CHANNEL(6, 1, AD7193_CH_AIN1),
1058 struct ad7192_state *st; in ad7192_probe() local
1067 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); in ad7192_probe()
1071 st = iio_priv(indio_dev); in ad7192_probe()
1073 mutex_init(&st->lock); in ad7192_probe()
1075 st->avdd = devm_regulator_get(&spi->dev, "avdd"); in ad7192_probe()
1076 if (IS_ERR(st->avdd)) in ad7192_probe()
1077 return PTR_ERR(st->avdd); in ad7192_probe()
1079 ret = regulator_enable(st->avdd); in ad7192_probe()
1085 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->avdd); in ad7192_probe()
1093 st->vref = devm_regulator_get_optional(&spi->dev, "vref"); in ad7192_probe()
1094 if (IS_ERR(st->vref)) { in ad7192_probe()
1095 if (PTR_ERR(st->vref) != -ENODEV) in ad7192_probe()
1096 return PTR_ERR(st->vref); in ad7192_probe()
1098 ret = regulator_get_voltage(st->avdd); in ad7192_probe()
1103 ret = regulator_enable(st->vref); in ad7192_probe()
1109 ret = devm_add_action_or_reset(&spi->dev, ad7192_reg_disable, st->vref); in ad7192_probe()
1113 ret = regulator_get_voltage(st->vref); in ad7192_probe()
1118 st->int_vref_mv = ret / 1000; in ad7192_probe()
1120 st->chip_info = of_device_get_match_data(&spi->dev); in ad7192_probe()
1121 if (!st->chip_info) in ad7192_probe()
1122 st->chip_info = (void *)spi_get_device_id(spi)->driver_data; in ad7192_probe()
1123 indio_dev->name = st->chip_info->name; in ad7192_probe()
1125 indio_dev->channels = st->chip_info->channels; in ad7192_probe()
1126 indio_dev->num_channels = st->chip_info->num_channels; in ad7192_probe()
1127 indio_dev->info = st->chip_info->info; in ad7192_probe()
1129 ret = ad_sd_init(&st->sd, indio_dev, spi, &ad7192_sigma_delta_info); in ad7192_probe()
1137 st->fclk = AD7192_INT_FREQ_MHZ; in ad7192_probe()
1139 st->mclk = devm_clk_get_optional_enabled(&spi->dev, "mclk"); in ad7192_probe()
1140 if (IS_ERR(st->mclk)) in ad7192_probe()
1141 return PTR_ERR(st->mclk); in ad7192_probe()
1143 st->clock_sel = ad7192_of_clock_select(st); in ad7192_probe()
1145 if (st->clock_sel == AD7192_CLK_EXT_MCLK1_2 || in ad7192_probe()
1146 st->clock_sel == AD7192_CLK_EXT_MCLK2) { in ad7192_probe()
1147 st->fclk = clk_get_rate(st->mclk); in ad7192_probe()
1148 if (!ad7192_valid_external_frequency(st->fclk)) { in ad7192_probe()