Lines Matching defs:etmv4_config
843 struct etmv4_config { struct
844 u32 mode;
845 u32 pe_sel;
846 u32 cfg;
847 u32 eventctrl0;
848 u32 eventctrl1;
849 u32 stall_ctrl;
850 u32 ts_ctrl;
851 u32 syncfreq;
852 u32 ccctlr;
853 u32 bb_ctrl;
854 u32 vinst_ctrl;
855 u32 viiectlr;
856 u32 vissctlr;
857 u32 vipcssctlr;
858 u8 seq_idx;
859 u32 seq_ctrl[ETM_MAX_SEQ_STATES];
860 u32 seq_rst;
861 u32 seq_state;
862 u8 cntr_idx;
863 u32 cntrldvr[ETMv4_MAX_CNTR];
864 u32 cntr_ctrl[ETMv4_MAX_CNTR];
865 u32 cntr_val[ETMv4_MAX_CNTR];
866 u8 res_idx;
867 u32 res_ctrl[ETM_MAX_RES_SEL];
868 u8 ss_idx;
869 u32 ss_ctrl[ETM_MAX_SS_CMP];
870 u32 ss_status[ETM_MAX_SS_CMP];
871 u32 ss_pe_cmp[ETM_MAX_SS_CMP];
872 u8 addr_idx;
873 u64 addr_val[ETM_MAX_SINGLE_ADDR_CMP];
874 u64 addr_acc[ETM_MAX_SINGLE_ADDR_CMP];
875 u8 addr_type[ETM_MAX_SINGLE_ADDR_CMP];
876 u8 ctxid_idx;
877 u64 ctxid_pid[ETMv4_MAX_CTXID_CMP];
878 u32 ctxid_mask0;
879 u32 ctxid_mask1;
880 u8 vmid_idx;
881 u64 vmid_val[ETM_MAX_VMID_CMP];
882 u32 vmid_mask0;
883 u32 vmid_mask1;
884 u32 ext_inp;
885 u8 s_ex_level;