Lines Matching +full:layer +full:- +full:alpha +full:- +full:mode

1 /* SPDX-License-Identifier: GPL-2.0 */
5  * Copyright (C) 2017 - 2020 Xilinx, Inc.
8  * - Hyun Woo Kwon <hyun.kwon@xilinx.com>
9  * - Laurent Pinchart <laurent.pinchart@ideasonboard.com>
36  * enum zynqmp_dpsub_layer_id - Layer identifier
37  * @ZYNQMP_DPSUB_LAYER_VID: Video layer
38  * @ZYNQMP_DPSUB_LAYER_GFX: Graphics layer
46  * enum zynqmp_dpsub_layer_mode - Layer mode
47  * @ZYNQMP_DPSUB_LAYER_NONLIVE: non-live (memory) mode
48  * @ZYNQMP_DPSUB_LAYER_LIVE: live (stream) mode
61 					bool enable, u32 alpha);
63 u32 *zynqmp_disp_layer_drm_formats(struct zynqmp_disp_layer *layer,
65 void zynqmp_disp_layer_enable(struct zynqmp_disp_layer *layer,
66 			      enum zynqmp_dpsub_layer_mode mode);
67 void zynqmp_disp_layer_disable(struct zynqmp_disp_layer *layer);
68 void zynqmp_disp_layer_set_format(struct zynqmp_disp_layer *layer,
70 int zynqmp_disp_layer_update(struct zynqmp_disp_layer *layer,