drm/xe/xe_tile.c

1 // SPDX-License-Identifier: MIT
19  * DOC: Multi-tile Design
22  * world, a 'tile' is pretty close to what most people would think of as being
24  * that's what is referred to as a "multi-tile device."  In such cases, pretty
25  * much all hardware is replicated per-tile, although certain responsibilities
26  * like PCI communication, reporting of interrupts to the OS, etc. are handled
27  * solely by the "root tile."  A multi-tile platform takes care of tying the
29  * are forwarded to the root tile, the per-tile vram is combined into a single
33  * the subset of a GPU/tile that is responsible for implementing graphics
34  * and/or media operations.  The GT is where a lot of the driver implementation
38  * Historically most Intel devices were single-tile devices that contained a
39  * single GT.  PVC is an example of an Intel platform built on a multi-tile
44  * single GPU.  This is important from a software perspective because multi-GT
45  * platforms like MTL only replicate a subset of the GPU hardware and behave
46  * differently than multi-tile platforms like PVC where nearly everything is
49  * Per-tile functionality (shared by all GTs within the tile):
50  *  - Complete 4MB MMIO space (containing SGunit/SoC registers, GT
52  *  - Global GTT
53  *  - VRAM (if discrete)
54  *  - Interrupt flows
55  *  - Migration context
56  *  - kernel batchbuffer pool
57  *  - Primary GT
58  *  - Media GT (if media version >= 13)
60  * Per-GT functionality:
61  *  - GuC
62  *  - Hardware engines
63  *  - Programmable hardware units (subslices, EUs)
64  *  - GSI subset of registers (multiple copies of these registers reside
66  *    offsets --- 0 for render, 0x380000 for media)
67  *  - Multicast register steering
68  *  - TLBs to cache page table translations
69  *  - Reset capability
70  *  - Low-level power management (e.g., C6)
71  *  - Clock frequency
72  *  - MOCS and PAT programming
76  * xe_tile_alloc - Perform per-tile memory allocation
79  * Allocates various per-tile data structures using DRM-managed allocations.
82  * Returns -ENOMEM if allocations fail, otherwise 0.
86 	struct drm_device *drm = &tile_to_xe(tile)->drm;  in xe_tile_alloc()
88 	tile->mem.ggtt = drmm_kzalloc(drm, sizeof(*tile->mem.ggtt),  in xe_tile_alloc()
90 	if (!tile->mem.ggtt)  in xe_tile_alloc()
91 		return -ENOMEM;  in xe_tile_alloc()
92 	tile->mem.ggtt->tile = tile;  in xe_tile_alloc()
94 	tile->mem.vram_mgr = drmm_kzalloc(drm, sizeof(*tile->mem.vram_mgr), GFP_KERNEL);  in xe_tile_alloc()
95 	if (!tile->mem.vram_mgr)  in xe_tile_alloc()
96 		return -ENOMEM;  in xe_tile_alloc()
102  * xe_tile_init_early - Initialize the tile and primary GT
107  * Initializes per-tile resources that don't require any interactions with the
116 	tile->xe = xe;  in xe_tile_init_early()
117 	tile->id = id;  in xe_tile_init_early()
123 	tile->primary_gt = xe_gt_alloc(tile);  in xe_tile_init_early()
124 	if (IS_ERR(tile->primary_gt))  in xe_tile_init_early()
125 		return PTR_ERR(tile->primary_gt);  in xe_tile_init_early()
135 	if (tile->mem.vram.usable_size) {  in tile_ttm_mgr_init()
136 		err = xe_ttm_vram_mgr_init(tile, tile->mem.vram_mgr);  in tile_ttm_mgr_init()
139 		xe->info.mem_region_mask |= BIT(tile->id) << 1;  in tile_ttm_mgr_init()
146  * xe_tile_init_noalloc - Init tile up to the point where allocations can happen.
152  * overwritten as it is usually put at the start of VRAM.
155  * GT-specific operations, and thus does not need to hold GT forcewake.
169 	tile->mem.kernel_bb_pool = xe_sa_bo_manager_init(tile, SZ_1M, 16);  in xe_tile_init_noalloc()
170 	if (IS_ERR(tile->mem.kernel_bb_pool)) {  in xe_tile_init_noalloc()
171 		err = PTR_ERR(tile->mem.kernel_bb_pool);  in xe_tile_init_noalloc()
185 	xe_migrate_wait(tile->migrate);  in xe_tile_migrate_wait()