Lines Matching +full:is +full:- +full:decoded +full:- +full:cs
1 // SPDX-License-Identifier: MIT
35 return gt_to_xe(lrc->fence_ctx.gt); in lrc_to_xe()
64 * The per-platform tables are u8-encoded in @data. Decode @data and set the
65 * addresses' offset and commands in @regs. The following encoding is used
69 * [7]: create NOPs - number of NOPs are set in lower bits
75 * Addresses: these are decoded after a MI_LOAD_REGISTER_IMM command by "count"
77 * is used for offsets smaller than 0x200 while the latter is for values bigger
100 const u32 base = hwe->mmio_base; in set_offsets()
121 xe_gt_assert(hwe->gt, count); in set_offsets()
134 } while (--count); in set_offsets()
537 struct xe_device *xe = gt_to_xe(hwe->gt); in lrc_ring_mi_mode()
561 return lrc->ring.size; in xe_lrc_pphwsp_offset()
587 /* The seqno is stored in the driver-defined portion of PPHWSP */ in __xe_lrc_seqno_offset()
593 /* The start seqno is stored in the driver-defined portion of PPHWSP */ in __xe_lrc_start_seqno_offset()
599 /* The parallel is stored in the driver-defined portion of PPHWSP */ in __xe_lrc_parallel_offset()
611 struct iosys_map map = lrc->bo->vmap; \
619 return xe_bo_ggtt_addr(lrc->bo) + __xe_lrc_##elem##_offset(lrc); \
658 struct xe_device *xe = gt_to_xe(hwe->gt); in empty_lrc_data()
662 data = kzalloc(xe_lrc_size(xe, hwe->class), GFP_KERNEL); in empty_lrc_data()
666 /* 1st page: Per-Process of HW status Page */ in empty_lrc_data()
668 set_offsets(regs, reg_offsets(xe, hwe->class), hwe); in empty_lrc_data()
677 u64 desc = xe_vm_pdp4_descriptor(vm, lrc->tile); in xe_lrc_set_ppgtt()
689 struct xe_gt *gt = hwe->gt; in xe_lrc_init()
697 lrc->flags = 0; in xe_lrc_init()
700 * FIXME: Perma-pinning LRC as we don't yet support moving GGTT address in xe_lrc_init()
703 lrc->bo = xe_bo_create_pin_map(xe, tile, vm, in xe_lrc_init()
704 ring_size + xe_lrc_size(xe, hwe->class), in xe_lrc_init()
708 if (IS_ERR(lrc->bo)) in xe_lrc_init()
709 return PTR_ERR(lrc->bo); in xe_lrc_init()
711 lrc->tile = gt_to_tile(hwe->gt); in xe_lrc_init()
712 lrc->ring.size = ring_size; in xe_lrc_init()
713 lrc->ring.tail = 0; in xe_lrc_init()
715 xe_hw_fence_ctx_init(&lrc->fence_ctx, hwe->gt, in xe_lrc_init()
716 hwe->fence_irq, hwe->name); in xe_lrc_init()
718 if (!gt->default_lrc[hwe->class]) { in xe_lrc_init()
721 err = -ENOMEM; in xe_lrc_init()
727 * Init Per-Process of HW status Page, LRC / context state to known in xe_lrc_init()
734 gt->default_lrc[hwe->class] + LRC_PPHWSP_SIZE, in xe_lrc_init()
735 xe_lrc_size(xe, hwe->class) - LRC_PPHWSP_SIZE); in xe_lrc_init()
738 xe_lrc_size(xe, hwe->class)); in xe_lrc_init()
745 if (vm->xef) in xe_lrc_init()
746 xe_drm_client_add_bo(vm->xef->client, lrc->bo); in xe_lrc_init()
751 xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); in xe_lrc_init()
753 RING_CTL_SIZE(lrc->ring.size) | RING_VALID); in xe_lrc_init()
754 if (xe->info.has_asid && vm) in xe_lrc_init()
755 xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID, vm->usm.asid); in xe_lrc_init()
757 lrc->desc = LRC_VALID; in xe_lrc_init()
758 lrc->desc |= LRC_LEGACY_64B_CONTEXT << LRC_ADDRESSING_MODE_SHIFT; in xe_lrc_init()
765 lrc->desc |= LRC_PRIVILEGE; in xe_lrc_init()
768 lrc->desc |= (u64)hwe->instance << ENGINE_INSTANCE_SHIFT; in xe_lrc_init()
769 lrc->desc |= (u64)hwe->class << ENGINE_CLASS_SHIFT; in xe_lrc_init()
776 xe_map_write32(lrc_to_xe(lrc), &map, lrc->fence_ctx.next_seqno - 1); in xe_lrc_init()
779 xe_map_write32(lrc_to_xe(lrc), &map, lrc->fence_ctx.next_seqno - 1); in xe_lrc_init()
790 xe_hw_fence_ctx_finish(&lrc->fence_ctx); in xe_lrc_finish()
791 xe_bo_lock(lrc->bo, false); in xe_lrc_finish()
792 xe_bo_unpin(lrc->bo); in xe_lrc_finish()
793 xe_bo_unlock(lrc->bo); in xe_lrc_finish()
794 xe_bo_put(lrc->bo); in xe_lrc_finish()
810 const u32 tail = lrc->ring.tail; in xe_lrc_ring_space()
811 const u32 size = lrc->ring.size; in xe_lrc_ring_space()
813 return ((head - tail - 1) & (size - 1)) + 1; in xe_lrc_ring_space()
821 iosys_map_incr(&ring, lrc->ring.tail); in __xe_lrc_write_ring()
823 lrc->ring.tail = (lrc->ring.tail + size) & (lrc->ring.size - 1); in __xe_lrc_write_ring()
838 xe_assert(xe, lrc->ring.tail < lrc->ring.size); in xe_lrc_write_ring()
839 rhs = lrc->ring.size - lrc->ring.tail; in xe_lrc_write_ring()
842 __xe_lrc_write_ring(lrc, ring, data + rhs, size - rhs); in xe_lrc_write_ring()
856 return lrc->desc | xe_lrc_ggtt_addr(lrc); in xe_lrc_descriptor()
866 return &xe_hw_fence_create(&lrc->fence_ctx, in xe_lrc_create_seqno_fence()
867 __xe_lrc_seqno_map(lrc))->dma; in xe_lrc_create_seqno_fence()
906 /* 3DSTATE_SO_DECL_LIST has a 9-bit dword length rather than 8 */ in instr_dw()
954 inst_header, (numdw - 1) / 2); in dump_mi_command()
956 drm_printf(p, " - %#6x = %#010x\n", dw[i], dw[i + 1]); in dump_mi_command()
981 * Make sure we haven't mis-parsed a number of dwords that exceeds the in dump_gfxpipe_command()
1125 if (!gt->default_lrc[hwe_class]) { in xe_lrc_dump_default()
1131 * Skip the beginning of the LRC since it contains the per-process in xe_lrc_dump_default()
1134 dw = gt->default_lrc[hwe_class] + LRC_PPHWSP_SIZE; in xe_lrc_dump_default()
1135 remaining_dw = (xe_lrc_size(gt_to_xe(gt), hwe_class) - LRC_PPHWSP_SIZE) / 4; in xe_lrc_dump_default()
1150 remaining_dw -= num_dw; in xe_lrc_dump_default()
1214 struct xe_gt *gt = q->hwe->gt; in xe_lrc_emit_hwe_state_instructions()
1220 * At the moment we only need to emit non-register state for the RCS in xe_lrc_emit_hwe_state_instructions()
1223 if (q->hwe->class != XE_ENGINE_CLASS_RENDER) in xe_lrc_emit_hwe_state_instructions()
1233 xe_gt_dbg(gt, "No non-register state to emit on graphics ver %d.%02d\n", in xe_lrc_emit_hwe_state_instructions()
1248 * Xe2's SVG context is the same as the one on DG2 / MTL in xe_lrc_emit_hwe_state_instructions()
1249 * except that 3DSTATE_DRAWING_RECTANGLE (non-pipelined) has in xe_lrc_emit_hwe_state_instructions()
1258 bb->cs[bb->len] = instr; in xe_lrc_emit_hwe_state_instructions()
1260 bb->cs[bb->len] |= (num_dw - 2); in xe_lrc_emit_hwe_state_instructions()
1262 bb->len += num_dw; in xe_lrc_emit_hwe_state_instructions()