Lines Matching +full:0 +full:x280
24 #define LRC_VALID (1 << 0)
72 * [5:0]: Number of NOPs or registers to set values to in case of
77 * is used for offsets smaller than 0x200 while the latter is for values bigger
82 * [6:0]: Register offset, without considering the engine base.
93 #define POSTED BIT(0) in set_offsets()
94 #define REG(x) (((x) >> 2) | BUILD_BUG_ON_ZERO(x >= 0x200)) in set_offsets()
96 (((x) >> 9) | BIT(7) | BUILD_BUG_ON_ZERO(x >= 0x10000)), \ in set_offsets()
97 (((x) >> 2) & 0x7f) in set_offsets()
98 #define END 0 in set_offsets()
111 count = *data & 0x3f; in set_offsets()
123 u32 offset = 0; in set_offsets()
132 regs[0] = base + (offset << 2); in set_offsets()
137 *regs = MI_BATCH_BUFFER_END | BIT(0); in set_offsets()
143 REG16(0x244),
144 REG(0x034),
145 REG(0x030),
146 REG(0x038),
147 REG(0x03c),
148 REG(0x168),
149 REG(0x140),
150 REG(0x110),
151 REG(0x1c0),
152 REG(0x1c4),
153 REG(0x1c8),
154 REG(0x180),
155 REG16(0x2b4),
159 REG16(0x3a8),
160 REG16(0x28c),
161 REG16(0x288),
162 REG16(0x284),
163 REG16(0x280),
164 REG16(0x27c),
165 REG16(0x278),
166 REG16(0x274),
167 REG16(0x270),
175 REG16(0x244),
176 REG(0x034),
177 REG(0x030),
178 REG(0x038),
179 REG(0x03c),
180 REG(0x168),
181 REG(0x140),
182 REG(0x110),
183 REG(0x1c0),
184 REG(0x1c4),
185 REG(0x1c8),
186 REG(0x180),
187 REG16(0x2b4),
188 REG(0x120),
189 REG(0x124),
193 REG16(0x3a8),
194 REG16(0x28c),
195 REG16(0x288),
196 REG16(0x284),
197 REG16(0x280),
198 REG16(0x27c),
199 REG16(0x278),
200 REG16(0x274),
201 REG16(0x270),
209 REG16(0x244),
210 REG(0x034),
211 REG(0x030),
212 REG(0x038),
213 REG(0x03c),
214 REG(0x168),
215 REG(0x140),
216 REG(0x110),
217 REG(0x1c0),
218 REG(0x1c4),
219 REG(0x1c8),
220 REG(0x180),
221 REG16(0x2b4),
225 REG16(0x3a8),
226 REG16(0x28c),
227 REG16(0x288),
228 REG16(0x284),
229 REG16(0x280),
230 REG16(0x27c),
231 REG16(0x278),
232 REG16(0x274),
233 REG16(0x270),
236 REG(0x1b0),
237 REG16(0x5a8),
238 REG16(0x5ac),
241 LRI(1, 0),
242 REG(0x0c8),
246 REG16(0x588),
247 REG16(0x588),
248 REG16(0x588),
249 REG16(0x588),
250 REG16(0x588),
251 REG16(0x588),
252 REG(0x028),
253 REG(0x09c),
254 REG(0x0c0),
255 REG(0x178),
256 REG(0x17c),
257 REG16(0x358),
258 REG(0x170),
259 REG(0x150),
260 REG(0x154),
261 REG(0x158),
262 REG16(0x41c),
263 REG16(0x600),
264 REG16(0x604),
265 REG16(0x608),
266 REG16(0x60c),
267 REG16(0x610),
268 REG16(0x614),
269 REG16(0x618),
270 REG16(0x61c),
271 REG16(0x620),
272 REG16(0x624),
273 REG16(0x628),
274 REG16(0x62c),
275 REG16(0x630),
276 REG16(0x634),
277 REG16(0x638),
278 REG16(0x63c),
279 REG16(0x640),
280 REG16(0x644),
281 REG16(0x648),
282 REG16(0x64c),
283 REG16(0x650),
284 REG16(0x654),
285 REG16(0x658),
286 REG16(0x65c),
287 REG16(0x660),
288 REG16(0x664),
289 REG16(0x668),
290 REG16(0x66c),
291 REG16(0x670),
292 REG16(0x674),
293 REG16(0x678),
294 REG16(0x67c),
295 REG(0x068),
296 REG(0x084),
305 REG16(0x244),
306 REG(0x034),
307 REG(0x030),
308 REG(0x038),
309 REG(0x03c),
310 REG(0x168),
311 REG(0x140),
312 REG(0x110),
313 REG(0x1c0),
314 REG(0x1c4),
315 REG(0x1c8),
316 REG(0x180),
317 REG16(0x2b4),
321 REG16(0x3a8),
322 REG16(0x28c),
323 REG16(0x288),
324 REG16(0x284),
325 REG16(0x280),
326 REG16(0x27c),
327 REG16(0x278),
328 REG16(0x274),
329 REG16(0x270),
332 REG(0x1b0),
333 REG16(0x5a8),
334 REG16(0x5ac),
337 LRI(1, 0),
338 REG(0x0c8),
346 REG16(0x244),
347 REG(0x034),
348 REG(0x030),
349 REG(0x038),
350 REG(0x03c),
351 REG(0x168),
352 REG(0x140),
353 REG(0x110),
354 REG(0x1c0),
355 REG(0x1c4),
356 REG(0x1c8),
357 REG(0x180),
358 REG16(0x2b4),
359 REG(0x120),
360 REG(0x124),
364 REG16(0x3a8),
365 REG16(0x28c),
366 REG16(0x288),
367 REG16(0x284),
368 REG16(0x280),
369 REG16(0x27c),
370 REG16(0x278),
371 REG16(0x274),
372 REG16(0x270),
375 REG(0x1b0),
376 REG16(0x5a8),
377 REG16(0x5ac),
380 LRI(1, 0),
381 REG(0x0c8),
389 REG16(0x244),
390 REG(0x034),
391 REG(0x030),
392 REG(0x038),
393 REG(0x03c),
394 REG(0x168),
395 REG(0x140),
396 REG(0x110),
397 REG(0x1c0),
398 REG(0x1c4),
399 REG(0x1c8),
400 REG(0x180),
401 REG16(0x2b4),
402 REG(0x120),
403 REG(0x124),
407 REG16(0x3a8),
408 REG16(0x28c),
409 REG16(0x288),
410 REG16(0x284),
411 REG16(0x280),
412 REG16(0x27c),
413 REG16(0x278),
414 REG16(0x274),
415 REG16(0x270),
419 REG16(0x5a8),
420 REG16(0x5ac),
423 LRI(1, 0),
424 REG(0x0c8),
430 NOP(1), /* [0x00] */ \
431 LRI(15, POSTED), /* [0x01] */ \
432 REG16(0x244), /* [0x02] CTXT_SR_CTL */ \
433 REG(0x034), /* [0x04] RING_BUFFER_HEAD */ \
434 REG(0x030), /* [0x06] RING_BUFFER_TAIL */ \
435 REG(0x038), /* [0x08] RING_BUFFER_START */ \
436 REG(0x03c), /* [0x0a] RING_BUFFER_CONTROL */ \
437 REG(0x168), /* [0x0c] BB_ADDR_UDW */ \
438 REG(0x140), /* [0x0e] BB_ADDR */ \
439 REG(0x110), /* [0x10] BB_STATE */ \
440 REG(0x1c0), /* [0x12] BB_PER_CTX_PTR */ \
441 REG(0x1c4), /* [0x14] RCS_INDIRECT_CTX */ \
442 REG(0x1c8), /* [0x16] RCS_INDIRECT_CTX_OFFSET */ \
443 REG(0x180), /* [0x18] CCID */ \
444 REG16(0x2b4), /* [0x1a] SEMAPHORE_TOKEN */ \
445 REG(0x120), /* [0x1c] PRT_BB_STATE */ \
446 REG(0x124), /* [0x1e] PRT_BB_STATE_UDW */ \
448 NOP(1), /* [0x20] */ \
449 LRI(9, POSTED), /* [0x21] */ \
450 REG16(0x3a8), /* [0x22] CTX_TIMESTAMP */ \
451 REG16(0x3ac), /* [0x24] CTX_TIMESTAMP_UDW */ \
452 REG(0x108), /* [0x26] INDIRECT_RING_STATE */ \
453 REG16(0x284), /* [0x28] dummy reg */ \
454 REG16(0x280), /* [0x2a] CS_ACC_CTR_THOLD */ \
455 REG16(0x27c), /* [0x2c] CS_CTX_SYS_PASID */ \
456 REG16(0x278), /* [0x2e] CS_CTX_ASID */ \
457 REG16(0x274), /* [0x30] PTBP_UDW */ \
458 REG16(0x270) /* [0x32] PTBP_LDW */
463 NOP(2), /* [0x34] */
464 LRI(2, POSTED), /* [0x36] */
465 REG16(0x5a8), /* [0x37] CONTEXT_SCHEDULING_ATTRIBUTES */
466 REG16(0x5ac), /* [0x39] PREEMPTION_STATUS */
468 NOP(6), /* [0x41] */
469 LRI(1, 0), /* [0x47] */
470 REG(0x0c8), /* [0x48] R_PWR_CLK_STATE */
478 NOP(4 + 8 + 1), /* [0x34] */
479 LRI(2, POSTED), /* [0x41] */
480 REG16(0x200), /* [0x42] BCS_SWCTRL */
481 REG16(0x204), /* [0x44] BLIT_CCTL */
540 return 0x70; in lrc_ring_mi_mode()
542 return 0x60; in lrc_ring_mi_mode()
556 return 0; in __xe_lrc_ring_offset()
683 #define PVC_CTX_ASID (0x2e + 1)
684 #define PVC_CTX_ACC_CTR_THOLD (0x2a + 1)
697 lrc->flags = 0; in xe_lrc_init()
713 lrc->ring.tail = 0; in xe_lrc_init()
732 xe_map_memset(xe, &map, 0, 0, LRC_PPHWSP_SIZE); /* PPHWSP */ in xe_lrc_init()
737 xe_map_memcpy_to(xe, &map, 0, init_data, in xe_lrc_init()
750 xe_lrc_write_ctx_reg(lrc, CTX_RING_HEAD, 0); in xe_lrc_init()
781 return 0; in xe_lrc_init()
822 xe_map_memcpy_to(xe, &ring, 0, data, size); in __xe_lrc_write_ring()
903 GFXPIPE_SINGLE_DW_CMD(0, 0)) in instr_dw()
910 /* Most instructions have the # of dwords (minus 2) in 7:0 */ in instr_dw()
1137 while (remaining_dw > 0) { in xe_lrc_dump_default()
1217 int state_table_size = 0; in xe_lrc_emit_hwe_state_instructions()
1238 for (int i = 0; i < state_table_size; i++) { in xe_lrc_emit_hwe_state_instructions()
1244 xe_gt_assert(gt, num_dw != 0); in xe_lrc_emit_hwe_state_instructions()