Lines Matching full:value
487 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
489 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
491 return value; in tegra_sor_readl()
494 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
497 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
498 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
545 u32 value; in tegra_clk_sor_pad_set_parent() local
547 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
548 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
552 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
556 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_clk_sor_pad_set_parent()
560 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
570 u32 value; in tegra_clk_sor_pad_get_parent() local
572 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
574 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { in tegra_clk_sor_pad_get_parent()
648 u32 value; in tegra_sor_power_up_lanes() local
654 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
657 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
660 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
664 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
666 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
669 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
671 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
673 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
676 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_power_up_lanes()
678 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
683 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_up_lanes()
684 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_up_lanes()
690 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_up_lanes()
699 u32 value; in tegra_sor_power_down_lanes() local
702 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
703 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down_lanes()
705 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
708 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down_lanes()
710 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
715 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down_lanes()
716 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down_lanes()
722 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down_lanes()
730 u32 value; in tegra_sor_dp_precharge() local
733 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
736 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
739 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
743 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
745 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
748 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
750 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
752 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
756 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
757 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_precharge()
759 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
764 u32 mask = 0x08, adj = 0, value; in tegra_sor_dp_term_calibrate() local
767 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
768 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
769 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
771 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
772 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_dp_term_calibrate()
773 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
778 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
779 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
780 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
781 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
785 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
786 if (value & SOR_PLL1_TERM_COMPOUT) in tegra_sor_dp_term_calibrate()
792 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
793 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_dp_term_calibrate()
794 value |= SOR_PLL1_TMDS_TERMADJ(adj); in tegra_sor_dp_term_calibrate()
795 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
798 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
799 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_dp_term_calibrate()
800 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
808 u32 pattern = 0, tx_pu = 0, value; in tegra_sor_dp_link_apply_training() local
811 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
826 value = SOR_DP_TPG_SCRAMBLER_GALIOS | in tegra_sor_dp_link_apply_training()
831 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
836 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
841 value = SOR_DP_TPG_SCRAMBLER_NONE | in tegra_sor_dp_link_apply_training()
850 value |= SOR_DP_TPG_CHANNEL_CODING; in tegra_sor_dp_link_apply_training()
852 pattern = pattern << 8 | value; in tegra_sor_dp_link_apply_training()
863 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
864 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_link_apply_training()
865 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_link_apply_training()
866 value |= SOR_DP_PADCTL_TX_PU(tx_pu); in tegra_sor_dp_link_apply_training()
867 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
878 u32 value; in tegra_sor_dp_link_configure() local
885 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
886 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_dp_link_configure()
887 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_dp_link_configure()
888 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_link_configure()
890 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
891 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_dp_link_configure()
892 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_dp_link_configure()
895 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_dp_link_configure()
897 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_link_configure()
902 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
903 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_dp_link_configure()
907 value |= SOR_PLL1_LOADADJ(0x3); in tegra_sor_dp_link_configure()
911 value |= SOR_PLL1_LOADADJ(0x4); in tegra_sor_dp_link_configure()
915 value |= SOR_PLL1_LOADADJ(0x6); in tegra_sor_dp_link_configure()
919 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
922 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
925 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
927 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_link_configure()
929 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_link_configure()
971 u32 value; in tegra_sor_setup_pwm() local
973 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
974 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
975 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
976 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
978 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
979 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
980 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
981 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
982 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
983 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
988 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
989 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
1000 unsigned long value, timeout; in tegra_sor_attach() local
1003 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1004 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
1005 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
1006 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1010 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
1011 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
1012 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
1018 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
1019 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
1030 unsigned long value, timeout; in tegra_sor_wakeup() local
1036 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
1037 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
1039 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
1050 u32 value; in tegra_sor_power_up() local
1052 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1053 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
1054 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
1059 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
1060 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
1247 u32 value; in tegra_sor_apply_config() local
1249 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1250 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_apply_config()
1251 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1252 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
1254 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1255 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_apply_config()
1256 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1258 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_apply_config()
1259 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1261 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_apply_config()
1262 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1265 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1267 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
1269 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_apply_config()
1270 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_apply_config()
1271 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
1273 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1274 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1275 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1276 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
1278 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1279 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
1280 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1281 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
1290 u32 value; in tegra_sor_mode_set() local
1292 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1293 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; in tegra_sor_mode_set()
1294 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_mode_set()
1295 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_mode_set()
1297 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | in tegra_sor_mode_set()
1301 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1304 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
1307 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1310 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
1314 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; in tegra_sor_mode_set()
1318 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; in tegra_sor_mode_set()
1322 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; in tegra_sor_mode_set()
1326 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1330 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_mode_set()
1334 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1338 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1345 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1346 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1352 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_mode_set()
1353 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1359 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_mode_set()
1360 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1366 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_mode_set()
1367 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1375 unsigned long value, timeout; in tegra_sor_detach() local
1378 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1379 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
1380 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1386 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1387 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
1391 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
1395 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1396 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
1397 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1401 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1402 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
1403 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1409 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1410 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
1416 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
1424 unsigned long value, timeout; in tegra_sor_power_down() local
1427 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1428 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
1429 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
1430 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1435 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1436 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
1442 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
1452 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1453 value |= SOR_PLL2_PORT_POWERDOWN; in tegra_sor_power_down()
1454 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1458 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1459 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_power_down()
1460 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1462 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1463 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
1464 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
1465 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1474 u32 value; in tegra_sor_crc_wait() local
1479 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1480 if (value & SOR_CRCA_VALID) in tegra_sor_crc_wait()
1496 u32 value; in tegra_sor_show_crc() local
1505 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1506 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_show_crc()
1507 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1509 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1510 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_show_crc()
1511 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1513 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1514 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_show_crc()
1515 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1522 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1524 seq_printf(s, "%08x\n", value); in tegra_sor_show_crc()
1852 u32 value = 0; in tegra_sor_hdmi_subpack() local
1856 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1858 return value; in tegra_sor_hdmi_subpack()
1867 u32 value; in tegra_sor_hdmi_write_infopack() local
1888 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
1891 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
1902 value = tegra_sor_hdmi_subpack(&ptr[i], num); in tegra_sor_hdmi_write_infopack()
1903 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1907 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); in tegra_sor_hdmi_write_infopack()
1908 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
1918 u32 value; in tegra_sor_hdmi_setup_avi_infoframe() local
1922 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1923 value &= ~INFOFRAME_CTRL_SINGLE; in tegra_sor_hdmi_setup_avi_infoframe()
1924 value &= ~INFOFRAME_CTRL_OTHER; in tegra_sor_hdmi_setup_avi_infoframe()
1925 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1926 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1944 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1945 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1946 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
1947 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
1972 u32 value; in tegra_sor_audio_prepare() local
1979 value = SOR_INT_CODEC_SCRATCH1 | SOR_INT_CODEC_SCRATCH0; in tegra_sor_audio_prepare()
1980 tegra_sor_writel(sor, value, SOR_INT_ENABLE); in tegra_sor_audio_prepare()
1981 tegra_sor_writel(sor, value, SOR_INT_MASK); in tegra_sor_audio_prepare()
1985 value = SOR_AUDIO_HDA_PRESENSE_ELDV | SOR_AUDIO_HDA_PRESENSE_PD; in tegra_sor_audio_prepare()
1986 tegra_sor_writel(sor, value, SOR_AUDIO_HDA_PRESENSE); in tegra_sor_audio_prepare()
1998 u32 value; in tegra_sor_audio_enable() local
2000 value = tegra_sor_readl(sor, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2003 value &= ~SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_MASK); in tegra_sor_audio_enable()
2004 value |= SOR_AUDIO_CNTRL_SOURCE_SELECT(SOURCE_SELECT_HDA); in tegra_sor_audio_enable()
2008 value &= ~SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2010 value |= SOR_AUDIO_CNTRL_INJECT_NULLSMPL; in tegra_sor_audio_enable()
2012 value |= SOR_AUDIO_CNTRL_AFIFO_FLUSH; in tegra_sor_audio_enable()
2014 tegra_sor_writel(sor, value, SOR_AUDIO_CNTRL); in tegra_sor_audio_enable()
2024 u32 value; in tegra_sor_hdmi_enable_audio_infoframe() local
2043 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2044 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2045 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_enable_audio_infoframe()
2046 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_enable_audio_infoframe()
2053 u32 value; in tegra_sor_hdmi_audio_enable() local
2059 value = SOR_HDMI_SPARE_ACR_PRIORITY_HIGH | in tegra_sor_hdmi_audio_enable()
2062 tegra_sor_writel(sor, value, SOR_HDMI_SPARE); in tegra_sor_hdmi_audio_enable()
2065 value = SOR_HDMI_ACR_SUBPACK_LOW_SB1(0); in tegra_sor_hdmi_audio_enable()
2066 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_LOW); in tegra_sor_hdmi_audio_enable()
2069 value = SOR_HDMI_ACR_SUBPACK_HIGH_ENABLE; in tegra_sor_hdmi_audio_enable()
2070 tegra_sor_writel(sor, value, SOR_HDMI_ACR_0441_SUBPACK_HIGH); in tegra_sor_hdmi_audio_enable()
2073 value = SOR_HDMI_AUDIO_N_RESET | SOR_HDMI_AUDIO_N_LOOKUP; in tegra_sor_hdmi_audio_enable()
2074 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2076 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2077 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0320); in tegra_sor_hdmi_audio_enable()
2089 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2090 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0480); in tegra_sor_hdmi_audio_enable()
2093 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2094 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_0960); in tegra_sor_hdmi_audio_enable()
2097 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2098 tegra_sor_writel(sor, value, SOR_AUDIO_AVAL_1920); in tegra_sor_hdmi_audio_enable()
2101 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2102 value &= ~SOR_HDMI_AUDIO_N_RESET; in tegra_sor_hdmi_audio_enable()
2103 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_N); in tegra_sor_hdmi_audio_enable()
2110 u32 value; in tegra_sor_hdmi_disable_audio_infoframe() local
2112 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2113 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_disable_audio_infoframe()
2114 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2136 u32 value; in tegra_sor_hdmi_disable_scrambling() local
2138 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2139 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_disable_scrambling()
2140 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_disable_scrambling()
2141 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2162 u32 value; in tegra_sor_hdmi_enable_scrambling() local
2164 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2165 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_enable_scrambling()
2166 value |= SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_enable_scrambling()
2167 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2209 u32 value; in tegra_sor_hdmi_disable() local
2223 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2226 value &= ~SOR1_TIMING_CYA; in tegra_sor_hdmi_disable()
2228 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2230 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2256 u32 value; in tegra_sor_hdmi_enable() local
2284 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2285 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_hdmi_enable()
2286 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2290 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2291 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_hdmi_enable()
2292 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2294 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2295 value &= ~SOR_PLL0_VCOPD; in tegra_sor_hdmi_enable()
2296 value &= ~SOR_PLL0_PWR; in tegra_sor_hdmi_enable()
2297 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2299 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2300 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()
2301 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2305 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2306 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_hdmi_enable()
2307 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_hdmi_enable()
2308 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2312 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2313 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()
2315 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2318 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2319 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
2325 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()
2327 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2330 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2331 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
2337 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2338 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_hdmi_enable()
2339 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_hdmi_enable()
2343 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; in tegra_sor_hdmi_enable()
2346 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; in tegra_sor_hdmi_enable()
2349 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
2350 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2355 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2356 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_hdmi_enable()
2357 value |= SOR_DP_LINKCTL_LANE_COUNT(4); in tegra_sor_hdmi_enable()
2358 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2360 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2361 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2362 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_hdmi_enable()
2363 value &= ~SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_hdmi_enable()
2364 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_hdmi_enable()
2365 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2367 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
2369 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2371 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | in tegra_sor_hdmi_enable()
2373 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2374 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2378 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()
2379 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2383 for (value = 0, i = 0; i < 5; i++) in tegra_sor_hdmi_enable()
2384 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2388 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2432 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2436 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; in tegra_sor_hdmi_enable()
2438 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2443 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | in tegra_sor_hdmi_enable()
2445 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2453 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | in tegra_sor_hdmi_enable()
2455 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2457 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); in tegra_sor_hdmi_enable()
2458 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2460 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2461 value |= H_PULSE2_ENABLE; in tegra_sor_hdmi_enable()
2462 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2474 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2475 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2476 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2477 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2480 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2481 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2482 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2492 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2493 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_hdmi_enable()
2494 value &= ~SOR_PLL0_FILTER_MASK; in tegra_sor_hdmi_enable()
2495 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_hdmi_enable()
2496 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2497 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2498 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2499 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2502 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2503 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_hdmi_enable()
2504 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_hdmi_enable()
2505 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2506 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2507 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_hdmi_enable()
2508 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2510 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2511 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; in tegra_sor_hdmi_enable()
2512 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; in tegra_sor_hdmi_enable()
2513 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; in tegra_sor_hdmi_enable()
2514 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; in tegra_sor_hdmi_enable()
2515 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2516 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2517 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2518 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2519 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2521 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2525 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2527 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2531 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2533 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2534 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_hdmi_enable()
2535 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_hdmi_enable()
2536 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2537 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2539 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2540 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; in tegra_sor_hdmi_enable()
2541 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2542 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2545 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2546 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2547 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2551 value = VSYNC_H_POSITION(1); in tegra_sor_hdmi_enable()
2552 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2555 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2556 value &= ~DITHER_CONTROL_MASK; in tegra_sor_hdmi_enable()
2557 value &= ~BASE_COLOR_SIZE_MASK; in tegra_sor_hdmi_enable()
2561 value |= BASE_COLOR_SIZE_666; in tegra_sor_hdmi_enable()
2565 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2569 value |= BASE_COLOR_SIZE_101010; in tegra_sor_hdmi_enable()
2573 value |= BASE_COLOR_SIZE_121212; in tegra_sor_hdmi_enable()
2578 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2582 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2585 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2586 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_hdmi_enable()
2587 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2588 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2595 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2596 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; in tegra_sor_hdmi_enable()
2597 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; in tegra_sor_hdmi_enable()
2598 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2601 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2602 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; in tegra_sor_hdmi_enable()
2603 value |= SOR_HEAD_STATE_COLORSPACE_RGB; in tegra_sor_hdmi_enable()
2604 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2611 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2612 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2613 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2620 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2623 value |= SOR1_TIMING_CYA; in tegra_sor_hdmi_enable()
2625 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2627 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2630 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2631 value &= ~PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2632 value |= PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2633 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2657 u32 value; in tegra_sor_dp_disable() local
2681 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2682 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2683 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_disable()
2686 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_disable()
2687 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_disable()
2688 value &= ~SOR_STATE_ASY_SUBOWNER_MASK; in tegra_sor_dp_disable()
2689 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_dp_disable()
2690 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_disable()
2726 u32 value; in tegra_sor_dp_enable() local
2767 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2768 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_dp_enable()
2769 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2773 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2774 value |= SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_dp_enable()
2775 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2777 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2778 value &= ~(SOR_PLL0_VCOPD | SOR_PLL0_PWR); in tegra_sor_dp_enable()
2779 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2781 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2782 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_dp_enable()
2783 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_dp_enable()
2784 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2788 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2789 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_dp_enable()
2790 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_dp_enable()
2791 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2793 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2794 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_dp_enable()
2797 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_dp_enable()
2799 value |= SOR_CLK_CNTRL_DP_CLK_SEL_DIFF_DPCLK; in tegra_sor_dp_enable()
2801 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_dp_enable()
2805 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2808 value |= SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2810 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_enable()
2812 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_enable()
2813 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_enable()
2818 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2819 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_dp_enable()
2820 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_dp_enable()
2821 value |= SOR_PLL0_ICHPMP(0x1); in tegra_sor_dp_enable()
2822 value |= SOR_PLL0_VCOCAP(0x3); in tegra_sor_dp_enable()
2823 value |= SOR_PLL0_RESISTOR_EXT; in tegra_sor_dp_enable()
2824 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2827 for (value = 0, i = 0; i < 5; i++) in tegra_sor_dp_enable()
2828 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2832 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_dp_enable()
2866 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_dp_enable()
2867 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_dp_enable()
2868 value |= SOR_STATE_ASY_PROTOCOL_DP_A; in tegra_sor_dp_enable()
2869 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_dp_enable()
2872 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2873 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_dp_enable()
2874 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_dp_enable()
2901 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_dp_enable()
2903 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_dp_enable()
2922 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
2923 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2924 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_dp_enable()
3644 u32 value; in tegra_sor_parse_dt() local
3648 err = of_property_read_u32(np, "nvidia,interface", &value); in tegra_sor_parse_dt()
3652 sor->index = value; in tegra_sor_parse_dt()
3683 u32 value; in tegra_sor_irq() local
3685 value = tegra_sor_readl(sor, SOR_INT_STATUS); in tegra_sor_irq()
3686 tegra_sor_writel(sor, value, SOR_INT_STATUS); in tegra_sor_irq()
3688 if (value & SOR_INT_CODEC_SCRATCH0) { in tegra_sor_irq()
3689 value = tegra_sor_readl(sor, SOR_AUDIO_HDA_CODEC_SCRATCH0); in tegra_sor_irq()
3691 if (value & SOR_AUDIO_HDA_CODEC_SCRATCH0_VALID) { in tegra_sor_irq()
3694 format = value & SOR_AUDIO_HDA_CODEC_SCRATCH0_FMT_MASK; in tegra_sor_irq()