Lines Matching +full:preemphasis +full:- +full:width
1 // SPDX-License-Identifier: GPL-2.0-only
7 #include <linux/clk-provider.h>
53 u8 preemphasis[4]; member
72 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
87 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
102 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
117 .preemphasis = { 0x00, 0x17, 0x17, 0x17 },
132 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
151 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
166 .preemphasis = { 0x01, 0x02, 0x02, 0x02 },
181 .preemphasis = { 0x10, 0x3e, 0x3e, 0x3e },
196 .preemphasis = { 0x02, 0x3f, 0x3f, 0x3f },
216 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
231 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
246 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
261 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
276 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
295 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
310 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
325 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
340 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
355 .preemphasis = { 0x00, 0x00, 0x00, 0x00 },
487 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
489 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
497 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
498 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
505 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
507 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
511 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
534 * Implementing ->set_parent() here isn't really required because the parent
544 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent()
568 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent()
602 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
604 return ERR_PTR(-ENOMEM); in tegra_clk_sor_pad_register()
606 pad->sor = sor; in tegra_clk_sor_pad_register()
610 init.parent_names = tegra_clk_sor_pad_parents[sor->index]; in tegra_clk_sor_pad_register()
611 init.num_parents = ARRAY_SIZE(tegra_clk_sor_pad_parents[sor->index]); in tegra_clk_sor_pad_register()
614 pad->hw.init = &init; in tegra_clk_sor_pad_register()
616 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
623 struct drm_dp_link *link = &sor->link; in tegra_sor_filter_rates()
627 for (i = 0; i < link->num_rates; i++) { in tegra_sor_filter_rates()
628 switch (link->rates[i]) { in tegra_sor_filter_rates()
636 link->rates[i]); in tegra_sor_filter_rates()
637 link->rates[i] = 0; in tegra_sor_filter_rates()
654 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
657 value &= ~(SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
658 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2])); in tegra_sor_power_up_lanes()
660 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[3]) | in tegra_sor_power_up_lanes()
661 SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[2]); in tegra_sor_power_up_lanes()
664 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
666 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[1]); in tegra_sor_power_up_lanes()
669 value &= ~SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
671 value |= SOR_DP_PADCTL_PD_TXD(sor->soc->lane_map[0]); in tegra_sor_power_up_lanes()
673 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_up_lanes()
691 return -ETIMEDOUT; in tegra_sor_power_up_lanes()
702 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
705 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down_lanes()
723 return -ETIMEDOUT; in tegra_sor_power_down_lanes()
732 /* pre-charge all used lanes */ in tegra_sor_dp_precharge()
733 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
736 value &= ~(SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
737 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2])); in tegra_sor_dp_precharge()
739 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[3]) | in tegra_sor_dp_precharge()
740 SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[2]); in tegra_sor_dp_precharge()
743 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
745 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[1]); in tegra_sor_dp_precharge()
748 value &= ~SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
750 value |= SOR_DP_PADCTL_CM_TXD(sor->soc->lane_map[0]); in tegra_sor_dp_precharge()
752 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
756 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
759 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_precharge()
767 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
769 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
771 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
773 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
778 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
781 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
785 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
792 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
795 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_term_calibrate()
798 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
800 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_term_calibrate()
807 const struct tegra_sor_soc *soc = sor->soc; in tegra_sor_dp_link_apply_training()
811 for (value = 0, i = 0; i < link->lanes; i++) { in tegra_sor_dp_link_apply_training()
812 u8 vs = link->train.request.voltage_swing[i]; in tegra_sor_dp_link_apply_training()
813 u8 pe = link->train.request.pre_emphasis[i]; in tegra_sor_dp_link_apply_training()
814 u8 pc = link->train.request.post_cursor[i]; in tegra_sor_dp_link_apply_training()
815 u8 shift = sor->soc->lane_map[i] << 3; in tegra_sor_dp_link_apply_training()
817 voltage_swing |= soc->voltage_swing[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
818 pre_emphasis |= soc->pre_emphasis[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
819 post_cursor |= soc->post_cursor[pc][vs][pe] << shift; in tegra_sor_dp_link_apply_training()
821 if (sor->soc->tx_pu[pc][vs][pe] > tx_pu) in tegra_sor_dp_link_apply_training()
822 tx_pu = sor->soc->tx_pu[pc][vs][pe]; in tegra_sor_dp_link_apply_training()
824 switch (link->train.pattern) { in tegra_sor_dp_link_apply_training()
846 return -EINVAL; in tegra_sor_dp_link_apply_training()
849 if (link->caps.channel_coding) in tegra_sor_dp_link_apply_training()
858 if (link->caps.tps3_supported) in tegra_sor_dp_link_apply_training()
863 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
867 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_link_apply_training()
881 rate = drm_dp_link_rate_to_bw_code(link->rate); in tegra_sor_dp_link_configure()
882 lanes = link->lanes; in tegra_sor_dp_link_configure()
894 if (link->caps.enhanced_framing) in tegra_sor_dp_link_configure()
902 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
919 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_dp_link_configure()
924 if (link->edp == 0) in tegra_sor_dp_link_configure()
933 dev_err(sor->dev, "failed to power down lanes: %d\n", err); in tegra_sor_dp_link_configure()
937 /* power up and pre-charge lanes */ in tegra_sor_dp_link_configure()
940 dev_err(sor->dev, "failed to power up %u lane%s: %d\n", in tegra_sor_dp_link_configure()
995 return -ETIMEDOUT; in tegra_sor_setup_pwm()
1025 return -ETIMEDOUT; in tegra_sor_attach()
1045 return -ETIMEDOUT; in tegra_sor_wakeup()
1066 return -ETIMEDOUT; in tegra_sor_power_up()
1090 const u64 f = params->precision; in tegra_sor_compute_params()
1093 active_sym = params->ratio * tu_size; in tegra_sor_compute_params()
1095 frac = active_sym - active_count; in tegra_sor_compute_params()
1100 frac = f - frac; in tegra_sor_compute_params()
1123 approx = active_count + (active_frac * (f - 1)) * f; in tegra_sor_compute_params()
1135 error = div_s64(active_sym - approx, tu_size); in tegra_sor_compute_params()
1136 error *= params->num_clocks; in tegra_sor_compute_params()
1138 if (error <= 0 && abs(error) < params->error) { in tegra_sor_compute_params()
1139 params->active_count = div_u64(active_count, f); in tegra_sor_compute_params()
1140 params->active_polarity = active_polarity; in tegra_sor_compute_params()
1141 params->active_frac = active_frac; in tegra_sor_compute_params()
1142 params->error = abs(error); in tegra_sor_compute_params()
1143 params->tu_size = tu_size; in tegra_sor_compute_params()
1157 const u64 f = 100000, link_rate = link->rate * 1000; in tegra_sor_compute_config()
1158 const u64 pclk = (u64)mode->clock * 1000; in tegra_sor_compute_config()
1164 if (!link_rate || !link->lanes || !pclk || !config->bits_per_pixel) in tegra_sor_compute_config()
1165 return -EINVAL; in tegra_sor_compute_config()
1167 input = pclk * config->bits_per_pixel; in tegra_sor_compute_config()
1168 output = link_rate * 8 * link->lanes; in tegra_sor_compute_config()
1171 return -ERANGE; in tegra_sor_compute_config()
1175 params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk); in tegra_sor_compute_config()
1180 for (i = params.tu_size; i >= 32; i--) in tegra_sor_compute_config()
1185 config->active_polarity = 0; in tegra_sor_compute_config()
1186 config->active_count = params.active_count; in tegra_sor_compute_config()
1189 config->active_count--; in tegra_sor_compute_config()
1191 config->tu_size = params.tu_size; in tegra_sor_compute_config()
1192 config->active_frac = 1; in tegra_sor_compute_config()
1194 config->active_polarity = params.active_polarity; in tegra_sor_compute_config()
1195 config->active_count = params.active_count; in tegra_sor_compute_config()
1196 config->active_frac = params.active_frac; in tegra_sor_compute_config()
1197 config->tu_size = params.tu_size; in tegra_sor_compute_config()
1200 dev_dbg(sor->dev, in tegra_sor_compute_config()
1202 config->active_polarity, config->active_count, in tegra_sor_compute_config()
1203 config->tu_size, config->active_frac); in tegra_sor_compute_config()
1205 watermark = params.ratio * config->tu_size * (f - params.ratio); in tegra_sor_compute_config()
1209 config->watermark = watermark + (config->bits_per_pixel / 8) + 2; in tegra_sor_compute_config()
1210 num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) * in tegra_sor_compute_config()
1211 (link->lanes * 8); in tegra_sor_compute_config()
1213 if (config->watermark > 30) { in tegra_sor_compute_config()
1214 config->watermark = 30; in tegra_sor_compute_config()
1215 dev_err(sor->dev, in tegra_sor_compute_config()
1217 config->watermark); in tegra_sor_compute_config()
1218 } else if (config->watermark > num_syms_per_line) { in tegra_sor_compute_config()
1219 config->watermark = num_syms_per_line; in tegra_sor_compute_config()
1220 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
1221 config->watermark); in tegra_sor_compute_config()
1225 num = ((mode->htotal - mode->hdisplay) - 7) * link_rate; in tegra_sor_compute_config()
1226 config->hblank_symbols = div_u64(num, pclk); in tegra_sor_compute_config()
1228 if (link->caps.enhanced_framing) in tegra_sor_compute_config()
1229 config->hblank_symbols -= 3; in tegra_sor_compute_config()
1231 config->hblank_symbols -= 12 / link->lanes; in tegra_sor_compute_config()
1234 num = (mode->hdisplay - 25) * link_rate; in tegra_sor_compute_config()
1235 config->vblank_symbols = div_u64(num, pclk); in tegra_sor_compute_config()
1236 config->vblank_symbols -= 36 / link->lanes + 4; in tegra_sor_compute_config()
1238 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
1239 config->vblank_symbols); in tegra_sor_compute_config()
1251 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
1256 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
1259 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
1262 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
1264 if (config->active_polarity) in tegra_sor_apply_config()
1275 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
1280 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
1288 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
1298 SOR_STATE_ASY_OWNER(dc->pipe + 1); in tegra_sor_mode_set()
1300 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in tegra_sor_mode_set()
1303 if (mode->flags & DRM_MODE_FLAG_NHSYNC) in tegra_sor_mode_set()
1306 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in tegra_sor_mode_set()
1309 if (mode->flags & DRM_MODE_FLAG_NVSYNC) in tegra_sor_mode_set()
1312 switch (state->bpc) { in tegra_sor_mode_set()
1345 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1346 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1348 /* sync end = sync width - 1 */ in tegra_sor_mode_set()
1349 vse = mode->vsync_end - mode->vsync_start - 1; in tegra_sor_mode_set()
1350 hse = mode->hsync_end - mode->hsync_start - 1; in tegra_sor_mode_set()
1353 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1356 vbe = vse + (mode->vtotal - mode->vsync_end); in tegra_sor_mode_set()
1357 hbe = hse + (mode->htotal - mode->hsync_end); in tegra_sor_mode_set()
1360 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1363 vbs = vbe + mode->vdisplay; in tegra_sor_mode_set()
1364 hbs = hbe + mode->hdisplay; in tegra_sor_mode_set()
1367 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1370 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1392 return -ETIMEDOUT; in tegra_sor_detach()
1417 return -ETIMEDOUT; in tegra_sor_detach()
1443 return -ETIMEDOUT; in tegra_sor_power_down()
1446 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1448 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1452 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1454 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1458 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1460 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1462 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1465 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1486 return -ETIMEDOUT; in tegra_sor_crc_wait()
1491 struct drm_info_node *node = s->private; in tegra_sor_show_crc()
1492 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc()
1493 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1494 struct drm_device *drm = node->minor->dev; in tegra_sor_show_crc()
1500 if (!crtc || !crtc->state->active) { in tegra_sor_show_crc()
1501 err = -EBUSY; in tegra_sor_show_crc()
1653 struct drm_info_node *node = s->private; in tegra_sor_show_regs()
1654 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs()
1655 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1656 struct drm_device *drm = node->minor->dev; in tegra_sor_show_regs()
1662 if (!crtc || !crtc->state->active) { in tegra_sor_show_regs()
1663 err = -EBUSY; in tegra_sor_show_regs()
1670 seq_printf(s, "%-38s %#05x %08x\n", tegra_sor_regs[i].name, in tegra_sor_show_regs()
1688 struct drm_minor *minor = connector->dev->primary; in tegra_sor_late_register()
1689 struct dentry *root = connector->debugfs_entry; in tegra_sor_late_register()
1692 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1694 if (!sor->debugfs_files) in tegra_sor_late_register()
1695 return -ENOMEM; in tegra_sor_late_register()
1698 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1700 drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1711 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1712 connector->debugfs_entry, in tegra_sor_early_unregister()
1713 connector->dev->primary); in tegra_sor_early_unregister()
1714 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1715 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1726 if (connector->state) { in tegra_sor_connector_reset()
1727 __drm_atomic_helper_connector_destroy_state(connector->state); in tegra_sor_connector_reset()
1728 kfree(connector->state); in tegra_sor_connector_reset()
1731 __drm_atomic_helper_connector_reset(connector, &state->base); in tegra_sor_connector_reset()
1740 if (sor->aux) in tegra_sor_connector_detect()
1741 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1749 struct tegra_sor_state *state = to_sor_state(connector->state); in tegra_sor_connector_duplicate_state()
1756 __drm_atomic_helper_connector_duplicate_state(connector, ©->base); in tegra_sor_connector_duplicate_state()
1758 return ©->base; in tegra_sor_connector_duplicate_state()
1778 if (sor->aux) in tegra_sor_connector_get_modes()
1779 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1783 if (sor->aux) in tegra_sor_connector_get_modes()
1784 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1808 struct tegra_dc *dc = to_tegra_dc(conn_state->crtc); in tegra_sor_encoder_atomic_check()
1809 unsigned long pclk = crtc_state->mode.clock * 1000; in tegra_sor_encoder_atomic_check()
1814 info = &output->connector.display_info; in tegra_sor_encoder_atomic_check()
1821 state->link_speed = 20; in tegra_sor_encoder_atomic_check()
1822 state->pclk = pclk / 2; in tegra_sor_encoder_atomic_check()
1824 state->link_speed = 10; in tegra_sor_encoder_atomic_check()
1825 state->pclk = pclk; in tegra_sor_encoder_atomic_check()
1828 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1831 dev_err(output->dev, "failed to setup CRTC state: %d\n", err); in tegra_sor_encoder_atomic_check()
1835 switch (info->bpc) { in tegra_sor_encoder_atomic_check()
1838 state->bpc = info->bpc; in tegra_sor_encoder_atomic_check()
1842 DRM_DEBUG_KMS("%u bits-per-color not supported\n", info->bpc); in tegra_sor_encoder_atomic_check()
1843 state->bpc = 8; in tegra_sor_encoder_atomic_check()
1855 for (i = size; i > 0; i--) in tegra_sor_hdmi_subpack()
1856 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1883 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
1896 * - subpack_low: bytes 0 - 3 in tegra_sor_hdmi_write_infopack()
1897 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00) in tegra_sor_hdmi_write_infopack()
1900 size_t rem = size - i, num = min_t(size_t, rem, 4); in tegra_sor_hdmi_write_infopack()
1905 num = min_t(size_t, rem - num, 3); in tegra_sor_hdmi_write_infopack()
1929 &sor->output.connector, mode); in tegra_sor_hdmi_setup_avi_infoframe()
1931 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1937 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
1954 size_t length = drm_eld_size(sor->output.connector.eld), i; in tegra_sor_write_eld()
1957 tegra_sor_writel(sor, i << 8 | sor->output.connector.eld[i], in tegra_sor_write_eld()
2007 if (sor->format.channels != 2) in tegra_sor_audio_enable()
2029 dev_err(sor->dev, "failed to setup audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2033 frame.channels = sor->format.channels; in tegra_sor_hdmi_enable_audio_infoframe()
2037 dev_err(sor->dev, "failed to pack audio infoframe: %d\n", err); in tegra_sor_hdmi_enable_audio_infoframe()
2076 value = (24000 * 4096) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2089 value = (24000 * 6144) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2093 value = (24000 * 12288) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2097 value = (24000 * 24576) / (128 * sor->format.sample_rate / 1000); in tegra_sor_hdmi_audio_enable()
2127 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2128 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2129 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2146 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2147 drm_scdc_set_scrambling(&sor->output.connector, false); in tegra_sor_hdmi_scdc_disable()
2154 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2155 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2172 drm_scdc_set_high_tmds_clock_ratio(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2173 drm_scdc_set_scrambling(&sor->output.connector, true); in tegra_sor_hdmi_scdc_enable()
2182 if (!drm_scdc_get_scrambling_status(&sor->output.connector)) { in tegra_sor_hdmi_scdc_work()
2187 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2192 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2195 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2197 if (mode->clock >= 340000 && scdc->supported) { in tegra_sor_hdmi_scdc_start()
2198 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2200 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2207 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_hdmi_disable()
2217 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2225 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2228 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2236 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2238 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2240 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2242 host1x_client_suspend(&sor->client); in tegra_sor_hdmi_disable()
2249 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_hdmi_enable()
2259 state = to_sor_state(output->connector.state); in tegra_sor_hdmi_enable()
2260 mode = &encoder->crtc->state->adjusted_mode; in tegra_sor_hdmi_enable()
2261 pclk = mode->clock * 1000; in tegra_sor_hdmi_enable()
2263 err = host1x_client_resume(&sor->client); in tegra_sor_hdmi_enable()
2265 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_hdmi_enable()
2270 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2272 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2276 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2278 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2280 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2284 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2286 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2290 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2292 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2294 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2297 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2299 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2301 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2305 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2308 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2312 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2315 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2341 if (mode->clock < 340000) { in tegra_sor_hdmi_enable()
2376 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2384 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2397 err = clk_set_parent(sor->clk_pad, sor->clk_dp); in tegra_sor_hdmi_enable()
2399 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_hdmi_enable()
2406 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2408 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_hdmi_enable()
2414 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2416 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_hdmi_enable()
2422 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2424 if (mode->clock >= 340000) in tegra_sor_hdmi_enable()
2429 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2431 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2432 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2435 if (mode->clock < 75000) in tegra_sor_hdmi_enable()
2441 max_ac = ((mode->htotal - mode->hdisplay) - SOR_REKEY - 18) / 32; in tegra_sor_hdmi_enable()
2447 if (!dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2450 (mode->hsync_end - mode->hsync_start) + in tegra_sor_hdmi_enable()
2451 (mode->htotal - mode->hsync_end) - 10; in tegra_sor_hdmi_enable()
2468 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2480 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2482 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2485 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2487 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2488 mode->clock * 1000); in tegra_sor_hdmi_enable()
2492 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2496 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2497 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2498 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2499 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2502 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2505 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2506 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2508 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2510 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2515 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2516 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2517 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2518 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2519 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2521 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2522 settings->drive_current[2] << 16 | in tegra_sor_hdmi_enable()
2523 settings->drive_current[1] << 8 | in tegra_sor_hdmi_enable()
2524 settings->drive_current[0] << 0; in tegra_sor_hdmi_enable()
2527 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2528 settings->preemphasis[2] << 16 | in tegra_sor_hdmi_enable()
2529 settings->preemphasis[1] << 8 | in tegra_sor_hdmi_enable()
2530 settings->preemphasis[0] << 0; in tegra_sor_hdmi_enable()
2533 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2536 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2537 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2539 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2541 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2542 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2545 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2547 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2549 if (!dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2559 switch (state->bpc) { in tegra_sor_hdmi_enable()
2577 WARN(1, "%u bits-per-color not supported\n", state->bpc); in tegra_sor_hdmi_enable()
2587 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2592 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2595 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2598 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2601 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2604 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2617 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2622 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2625 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2629 if (dc->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2630 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2633 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2640 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2655 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_dp_disable()
2660 if (output->panel) in tegra_sor_dp_disable()
2661 drm_panel_disable(output->panel); in tegra_sor_dp_disable()
2667 if (output->connector.status != connector_status_disconnected) { in tegra_sor_dp_disable()
2668 err = drm_dp_link_power_down(sor->aux, &sor->link); in tegra_sor_dp_disable()
2670 dev_err(sor->dev, "failed to power down link: %d\n", in tegra_sor_dp_disable()
2676 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_dp_disable()
2682 value &= ~SOR_ENABLE(sor->index); in tegra_sor_dp_disable()
2694 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_disable()
2696 dev_err(sor->dev, "failed to set safe clock: %d\n", err); in tegra_sor_dp_disable()
2700 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_dp_disable()
2702 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_dp_disable()
2704 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_dp_disable()
2706 err = drm_dp_aux_disable(sor->aux); in tegra_sor_dp_disable()
2708 dev_err(sor->dev, "failed disable DPAUX: %d\n", err); in tegra_sor_dp_disable()
2710 if (output->panel) in tegra_sor_dp_disable()
2711 drm_panel_unprepare(output->panel); in tegra_sor_dp_disable()
2713 host1x_client_suspend(&sor->client); in tegra_sor_dp_disable()
2719 struct tegra_dc *dc = to_tegra_dc(encoder->crtc); in tegra_sor_dp_enable()
2729 state = to_sor_state(output->connector.state); in tegra_sor_dp_enable()
2730 mode = &encoder->crtc->state->adjusted_mode; in tegra_sor_dp_enable()
2731 info = &output->connector.display_info; in tegra_sor_dp_enable()
2733 err = host1x_client_resume(&sor->client); in tegra_sor_dp_enable()
2735 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_dp_enable()
2740 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_dp_enable()
2742 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_dp_enable()
2744 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_dp_enable()
2746 dev_err(sor->dev, "failed to power on LVDS rail: %d\n", err); in tegra_sor_dp_enable()
2750 err = drm_dp_aux_enable(sor->aux); in tegra_sor_dp_enable()
2752 dev_err(sor->dev, "failed to enable DPAUX: %d\n", err); in tegra_sor_dp_enable()
2754 err = drm_dp_link_probe(sor->aux, &sor->link); in tegra_sor_dp_enable()
2756 dev_err(sor->dev, "failed to probe DP link: %d\n", err); in tegra_sor_dp_enable()
2760 err = drm_dp_link_choose(&sor->link, mode, info); in tegra_sor_dp_enable()
2762 dev_err(sor->dev, "failed to choose link: %d\n", err); in tegra_sor_dp_enable()
2764 if (output->panel) in tegra_sor_dp_enable()
2765 drm_panel_prepare(output->panel); in tegra_sor_dp_enable()
2767 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2769 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2773 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2775 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_dp_enable()
2777 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2779 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2781 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2784 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2788 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2791 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_dp_enable()
2796 if (output->panel) in tegra_sor_dp_enable()
2807 if (output->panel) in tegra_sor_dp_enable()
2818 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2824 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_dp_enable()
2828 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_dp_enable()
2841 err = clk_set_parent(sor->clk_pad, sor->clk_parent); in tegra_sor_dp_enable()
2843 dev_err(sor->dev, "failed to select pad parent clock: %d\n", in tegra_sor_dp_enable()
2850 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_dp_enable()
2852 dev_err(sor->dev, "failed to select SOR parent clock: %d\n", in tegra_sor_dp_enable()
2858 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_dp_enable()
2860 dev_err(sor->dev, "failed to select output parent clock: %d\n", in tegra_sor_dp_enable()
2865 /* use DP-A protocol */ in tegra_sor_dp_enable()
2878 err = drm_dp_link_train(&sor->link); in tegra_sor_dp_enable()
2880 dev_err(sor->dev, "link training failed: %d\n", err); in tegra_sor_dp_enable()
2882 dev_dbg(sor->dev, "link training succeeded\n"); in tegra_sor_dp_enable()
2884 err = drm_dp_link_power_up(sor->aux, &sor->link); in tegra_sor_dp_enable()
2886 dev_err(sor->dev, "failed to power up DP link: %d\n", err); in tegra_sor_dp_enable()
2890 config.bits_per_pixel = state->bpc * 3; in tegra_sor_dp_enable()
2892 err = tegra_sor_compute_config(sor, mode, &config, &sor->link); in tegra_sor_dp_enable()
2894 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_dp_enable()
2899 if (output->panel) { in tegra_sor_dp_enable()
2908 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_dp_enable()
2915 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_dp_enable()
2920 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_dp_enable()
2923 value |= SOR_ENABLE(sor->index); in tegra_sor_dp_enable()
2930 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_dp_enable()
2932 if (output->panel) in tegra_sor_dp_enable()
2933 drm_panel_enable(output->panel); in tegra_sor_dp_enable()
2957 return devm_add_action_or_reset(sor->dev, tegra_sor_disable_regulator, reg); in tegra_sor_enable_regulator()
2964 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_hdmi_probe()
2965 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_hdmi_probe()
2966 return dev_err_probe(sor->dev, PTR_ERR(sor->avdd_io_supply), in tegra_sor_hdmi_probe()
2969 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2971 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2976 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_hdmi_probe()
2977 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_hdmi_probe()
2978 return dev_err_probe(sor->dev, PTR_ERR(sor->vdd_pll_supply), in tegra_sor_hdmi_probe()
2981 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2983 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2988 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2989 if (IS_ERR(sor->hdmi_supply)) in tegra_sor_hdmi_probe()
2990 return dev_err_probe(sor->dev, PTR_ERR(sor->hdmi_supply), in tegra_sor_hdmi_probe()
2993 err = tegra_sor_enable_regulator(sor, sor->hdmi_supply); in tegra_sor_hdmi_probe()
2995 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
2999 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
3015 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io-hdmi-dp"); in tegra_sor_dp_probe()
3016 if (IS_ERR(sor->avdd_io_supply)) in tegra_sor_dp_probe()
3017 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_dp_probe()
3019 err = tegra_sor_enable_regulator(sor, sor->avdd_io_supply); in tegra_sor_dp_probe()
3023 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-hdmi-dp-pll"); in tegra_sor_dp_probe()
3024 if (IS_ERR(sor->vdd_pll_supply)) in tegra_sor_dp_probe()
3025 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_dp_probe()
3027 err = tegra_sor_enable_regulator(sor, sor->vdd_pll_supply); in tegra_sor_dp_probe()
3041 struct drm_device *drm = dev_get_drvdata(client->host); in tegra_sor_init()
3048 if (!sor->aux) { in tegra_sor_init()
3049 if (sor->ops == &tegra_sor_hdmi_ops) { in tegra_sor_init()
3053 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
3058 if (sor->output.panel) { in tegra_sor_init()
3068 sor->link.ops = &tegra_sor_dp_link_ops; in tegra_sor_init()
3069 sor->link.aux = sor->aux; in tegra_sor_init()
3072 sor->output.dev = sor->dev; in tegra_sor_init()
3074 drm_connector_init_with_ddc(drm, &sor->output.connector, in tegra_sor_init()
3077 sor->output.ddc); in tegra_sor_init()
3078 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
3080 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
3082 drm_simple_encoder_init(drm, &sor->output.encoder, encoder); in tegra_sor_init()
3083 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
3085 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
3086 &sor->output.encoder); in tegra_sor_init()
3087 drm_connector_register(&sor->output.connector); in tegra_sor_init()
3089 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
3091 dev_err(client->dev, "failed to initialize output: %d\n", err); in tegra_sor_init()
3095 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
3097 if (sor->aux) { in tegra_sor_init()
3098 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
3100 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
3106 * XXX: Remove this reset once proper hand-over from firmware to in tegra_sor_init()
3109 if (sor->rst) { in tegra_sor_init()
3110 err = pm_runtime_resume_and_get(sor->dev); in tegra_sor_init()
3112 dev_err(sor->dev, "failed to get runtime PM: %d\n", err); in tegra_sor_init()
3116 err = reset_control_acquire(sor->rst); in tegra_sor_init()
3118 dev_err(sor->dev, "failed to acquire SOR reset: %d\n", in tegra_sor_init()
3123 err = reset_control_assert(sor->rst); in tegra_sor_init()
3125 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
3131 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
3133 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
3139 if (sor->rst) { in tegra_sor_init()
3140 err = reset_control_deassert(sor->rst); in tegra_sor_init()
3142 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
3144 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3148 reset_control_release(sor->rst); in tegra_sor_init()
3149 pm_runtime_put(sor->dev); in tegra_sor_init()
3152 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
3154 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3158 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
3160 clk_disable_unprepare(sor->clk_safe); in tegra_sor_init()
3161 clk_disable_unprepare(sor->clk); in tegra_sor_init()
3168 if (sor->rst) in tegra_sor_init()
3169 pm_runtime_put(sor->dev); in tegra_sor_init()
3179 tegra_output_exit(&sor->output); in tegra_sor_exit()
3181 if (sor->aux) { in tegra_sor_exit()
3182 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
3184 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
3189 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
3190 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
3191 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
3199 struct device *dev = client->dev; in tegra_sor_runtime_suspend()
3202 if (sor->rst) { in tegra_sor_runtime_suspend()
3203 err = reset_control_assert(sor->rst); in tegra_sor_runtime_suspend()
3209 reset_control_release(sor->rst); in tegra_sor_runtime_suspend()
3214 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_suspend()
3223 struct device *dev = client->dev; in tegra_sor_runtime_resume()
3232 err = clk_prepare_enable(sor->clk); in tegra_sor_runtime_resume()
3240 if (sor->rst) { in tegra_sor_runtime_resume()
3241 err = reset_control_acquire(sor->rst); in tegra_sor_runtime_resume()
3247 err = reset_control_deassert(sor->rst); in tegra_sor_runtime_resume()
3257 reset_control_release(sor->rst); in tegra_sor_runtime_resume()
3259 clk_disable_unprepare(sor->clk); in tegra_sor_runtime_resume()
3629 { .compatible = "nvidia,tegra194-sor", .data = &tegra194_sor },
3630 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
3631 { .compatible = "nvidia,tegra210-sor1", .data = &tegra210_sor1 },
3632 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
3633 { .compatible = "nvidia,tegra132-sor", .data = &tegra132_sor },
3634 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
3641 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
3647 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
3652 sor->index = value; in tegra_sor_parse_dt()
3658 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
3660 if (!sor->soc->supports_audio) in tegra_sor_parse_dt()
3661 sor->index = 0; in tegra_sor_parse_dt()
3663 sor->index = 1; in tegra_sor_parse_dt()
3666 err = of_property_read_u32_array(np, "nvidia,xbar-cfg", xbar_cfg, 5); in tegra_sor_parse_dt()
3668 /* fall back to default per-SoC XBAR configuration */ in tegra_sor_parse_dt()
3670 sor->xbar_cfg[i] = sor->soc->xbar_cfg[i]; in tegra_sor_parse_dt()
3674 sor->xbar_cfg[i] = xbar_cfg[i]; in tegra_sor_parse_dt()
3696 tegra_hda_parse_format(format, &sor->format); in tegra_sor_irq()
3698 if (sor->ops->audio_enable) in tegra_sor_irq()
3699 sor->ops->audio_enable(sor); in tegra_sor_irq()
3701 if (sor->ops->audio_disable) in tegra_sor_irq()
3702 sor->ops->audio_disable(sor); in tegra_sor_irq()
3715 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
3717 return -ENOMEM; in tegra_sor_probe()
3719 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
3720 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
3722 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
3723 sor->soc->num_settings * in tegra_sor_probe()
3724 sizeof(*sor->settings), in tegra_sor_probe()
3726 if (!sor->settings) in tegra_sor_probe()
3727 return -ENOMEM; in tegra_sor_probe()
3729 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
3731 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0); in tegra_sor_probe()
3733 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
3736 if (!sor->aux) in tegra_sor_probe()
3737 return -EPROBE_DEFER; in tegra_sor_probe()
3739 if (get_device(sor->aux->dev)) in tegra_sor_probe()
3740 sor->output.ddc = &sor->aux->ddc; in tegra_sor_probe()
3743 if (!sor->aux) { in tegra_sor_probe()
3744 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
3745 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
3746 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
3747 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
3748 dev_err(&pdev->dev, "LVDS not supported yet\n"); in tegra_sor_probe()
3749 return -ENODEV; in tegra_sor_probe()
3751 dev_err(&pdev->dev, "unknown (non-DP) support\n"); in tegra_sor_probe()
3752 return -ENODEV; in tegra_sor_probe()
3755 np = of_parse_phandle(pdev->dev.of_node, "nvidia,panel", 0); in tegra_sor_probe()
3762 sor->ops = &tegra_sor_dp_ops; in tegra_sor_probe()
3763 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
3770 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3772 dev_err_probe(&pdev->dev, err, "failed to probe output\n"); in tegra_sor_probe()
3776 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3777 err = sor->ops->probe(sor); in tegra_sor_probe()
3779 dev_err(&pdev->dev, "failed to probe %s: %d\n", in tegra_sor_probe()
3780 sor->ops->name, err); in tegra_sor_probe()
3785 sor->regs = devm_platform_ioremap_resource(pdev, 0); in tegra_sor_probe()
3786 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3787 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3795 sor->irq = err; in tegra_sor_probe()
3797 err = devm_request_irq(sor->dev, sor->irq, tegra_sor_irq, 0, in tegra_sor_probe()
3798 dev_name(sor->dev), sor); in tegra_sor_probe()
3800 dev_err(&pdev->dev, "failed to request IRQ: %d\n", err); in tegra_sor_probe()
3804 sor->rst = devm_reset_control_get_exclusive_released(&pdev->dev, "sor"); in tegra_sor_probe()
3805 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3806 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3808 if (err != -EBUSY || WARN_ON(!pdev->dev.pm_domain)) { in tegra_sor_probe()
3809 dev_err(&pdev->dev, "failed to get reset control: %d\n", in tegra_sor_probe()
3820 sor->rst = NULL; in tegra_sor_probe()
3823 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3824 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3825 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3826 dev_err(&pdev->dev, "failed to get module clock: %d\n", err); in tegra_sor_probe()
3830 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3831 struct device_node *np = pdev->dev.of_node; in tegra_sor_probe()
3839 if (of_property_match_string(np, "clock-names", "out") < 0) in tegra_sor_probe()
3844 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3845 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3846 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3847 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3853 sor->clk_out = sor->clk; in tegra_sor_probe()
3856 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3857 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3858 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3859 dev_err(&pdev->dev, "failed to get parent clock: %d\n", err); in tegra_sor_probe()
3863 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3864 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3865 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3866 dev_err(&pdev->dev, "failed to get safe clock: %d\n", err); in tegra_sor_probe()
3870 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3871 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3872 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3873 dev_err(&pdev->dev, "failed to get DP clock: %d\n", err); in tegra_sor_probe()
3881 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3882 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3883 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3884 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3893 sor->clk_pad = NULL; in tegra_sor_probe()
3901 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3903 dev_err(&pdev->dev, "failed to use safe clock: %d\n", err); in tegra_sor_probe()
3908 pm_runtime_enable(&pdev->dev); in tegra_sor_probe()
3910 host1x_client_init(&sor->client); in tegra_sor_probe()
3911 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3912 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3918 if (!sor->clk_pad) { in tegra_sor_probe()
3921 name = devm_kasprintf(sor->dev, GFP_KERNEL, "sor%u_pad_clkout", in tegra_sor_probe()
3922 sor->index); in tegra_sor_probe()
3924 err = -ENOMEM; in tegra_sor_probe()
3928 err = host1x_client_resume(&sor->client); in tegra_sor_probe()
3930 dev_err(sor->dev, "failed to resume: %d\n", err); in tegra_sor_probe()
3934 sor->clk_pad = tegra_clk_sor_pad_register(sor, name); in tegra_sor_probe()
3935 host1x_client_suspend(&sor->client); in tegra_sor_probe()
3938 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3939 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3940 dev_err(sor->dev, "failed to register SOR pad clock: %d\n", in tegra_sor_probe()
3945 err = __host1x_client_register(&sor->client); in tegra_sor_probe()
3947 dev_err(&pdev->dev, "failed to register host1x client: %d\n", in tegra_sor_probe()
3955 host1x_client_exit(&sor->client); in tegra_sor_probe()
3956 pm_runtime_disable(&pdev->dev); in tegra_sor_probe()
3958 if (sor->aux) in tegra_sor_probe()
3959 sor->output.ddc = NULL; in tegra_sor_probe()
3961 tegra_output_remove(&sor->output); in tegra_sor_probe()
3963 if (sor->aux) in tegra_sor_probe()
3964 put_device(sor->aux->dev); in tegra_sor_probe()
3973 host1x_client_unregister(&sor->client); in tegra_sor_remove()
3975 pm_runtime_disable(&pdev->dev); in tegra_sor_remove()
3977 if (sor->aux) { in tegra_sor_remove()
3978 put_device(sor->aux->dev); in tegra_sor_remove()
3979 sor->output.ddc = NULL; in tegra_sor_remove()
3982 tegra_output_remove(&sor->output); in tegra_sor_remove()
3990 err = tegra_output_suspend(&sor->output); in tegra_sor_suspend()
3996 if (sor->hdmi_supply) { in tegra_sor_suspend()
3997 err = regulator_disable(sor->hdmi_supply); in tegra_sor_suspend()
3999 tegra_output_resume(&sor->output); in tegra_sor_suspend()
4012 if (sor->hdmi_supply) { in tegra_sor_resume()
4013 err = regulator_enable(sor->hdmi_supply); in tegra_sor_resume()
4018 err = tegra_output_resume(&sor->output); in tegra_sor_resume()
4022 if (sor->hdmi_supply) in tegra_sor_resume()
4023 regulator_disable(sor->hdmi_supply); in tegra_sor_resume()
4037 .name = "tegra-sor",