Lines Matching full:pll1
44 u32 pll1; member
142 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
157 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
175 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
189 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
203 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
220 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
238 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
257 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
276 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
299 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(0),
317 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
336 .pll1 = SOR_PLL_PE_EN | SOR_PLL_LOADADJ(3) |
355 .pll1 = SOR_PLL_LOADADJ(3) | SOR_PLL_TMDS_TERMADJ(7)
839 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1); in tegra_hdmi_setup_tmds()