Lines Matching +full:layer +full:- +full:primary
1 // SPDX-License-Identifier: GPL-2.0
15 #include <linux/media-bus-format.h>
45 #define CRTC_MASK GENMASK(NB_CRTC - 1, 0)
60 #define LAY_OFS (ldev->caps.layer_ofs)
64 #define LTDC_LCR 0x0004 /* Layer Count */
85 /* Layer register offsets */
86 #define LTDC_L1C0R (ldev->caps.layer_regs[0]) /* L1 configuration 0 */
87 #define LTDC_L1C1R (ldev->caps.layer_regs[1]) /* L1 configuration 1 */
88 #define LTDC_L1RCR (ldev->caps.layer_regs[2]) /* L1 reload control */
89 #define LTDC_L1CR (ldev->caps.layer_regs[3]) /* L1 control register */
90 #define LTDC_L1WHPCR (ldev->caps.layer_regs[4]) /* L1 window horizontal position configuration */
91 #define LTDC_L1WVPCR (ldev->caps.layer_regs[5]) /* L1 window vertical position configuration */
92 #define LTDC_L1CKCR (ldev->caps.layer_regs[6]) /* L1 color keying configuration */
93 #define LTDC_L1PFCR (ldev->caps.layer_regs[7]) /* L1 pixel format configuration */
94 #define LTDC_L1CACR (ldev->caps.layer_regs[8]) /* L1 constant alpha configuration */
95 #define LTDC_L1DCCR (ldev->caps.layer_regs[9]) /* L1 default color configuration */
96 #define LTDC_L1BFCR (ldev->caps.layer_regs[10]) /* L1 blending factors configuration */
97 #define LTDC_L1BLCR (ldev->caps.layer_regs[11]) /* L1 burst length configuration */
98 #define LTDC_L1PCR (ldev->caps.layer_regs[12]) /* L1 planar configuration */
99 #define LTDC_L1CFBAR (ldev->caps.layer_regs[13]) /* L1 color frame buffer address */
100 #define LTDC_L1CFBLR (ldev->caps.layer_regs[14]) /* L1 color frame buffer length */
101 #define LTDC_L1CFBLNR (ldev->caps.layer_regs[15]) /* L1 color frame buffer line number */
102 #define LTDC_L1AFBA0R (ldev->caps.layer_regs[16]) /* L1 auxiliary frame buffer address 0 */
103 #define LTDC_L1AFBA1R (ldev->caps.layer_regs[17]) /* L1 auxiliary frame buffer address 1 */
104 #define LTDC_L1AFBLR (ldev->caps.layer_regs[18]) /* L1 auxiliary frame buffer length */
105 #define LTDC_L1AFBLNR (ldev->caps.layer_regs[19]) /* L1 auxiliary frame buffer line number */
106 #define LTDC_L1CLUTWR (ldev->caps.layer_regs[20]) /* L1 CLUT write */
107 #define LTDC_L1CYR0R (ldev->caps.layer_regs[21]) /* L1 Conversion YCbCr RGB 0 */
108 #define LTDC_L1CYR1R (ldev->caps.layer_regs[22]) /* L1 Conversion YCbCr RGB 1 */
109 #define LTDC_L1FPF0R (ldev->caps.layer_regs[23]) /* L1 Flexible Pixel Format 0 */
110 #define LTDC_L1FPF1R (ldev->caps.layer_regs[24]) /* L1 Flexible Pixel Format 1 */
128 #define GCR_PCPOL BIT(28) /* Pixel Clock POLarity-Inverted */
129 #define GCR_DEPOL BIT(29) /* Data Enable POLarity-High */
130 #define GCR_VSPOL BIT(30) /* Vertical Synchro POLarity-High */
131 #define GCR_HSPOL BIT(31) /* Horizontal Synchro POLarity-High */
152 #define GC2R_DVAEN BIT(2) /* Dual-View Ability ENabled */
153 #define GC2R_DPAEN BIT(3) /* Dual-Port Ability ENabled */
186 #define LXCR_LEN BIT(0) /* Layer ENable */
188 #define LXCR_CLUTEN BIT(4) /* Color Look-Up Table ENable */
212 #define LXCR_C1R_YSPA BIT(1) /* Ycbcr 420 Semi-Planar Ability */
213 #define LXCR_C1R_YFPA BIT(2) /* Ycbcr 420 Full-Planar Ability */
222 #define YCM_SP 0x1 /* Semi-Planar 420 */
223 #define YCM_FP 0x2 /* Full-Planar 420 */
224 #define LxPCR_YCEN BIT(3) /* YCbCr-to-RGB Conversion Enable */
235 #define BF2_1PAXCA 0x007 /* 1 - (Pixel Alpha x Constant Alpha) */
236 #define BF2_1CA 0x005 /* 1 - Constant Alpha */
365 /* Layer register offsets */
486 return (struct ltdc_device *)crtc->dev->dev_private; in crtc_to_ltdc()
491 return (struct ltdc_device *)plane->dev->dev_private; in plane_to_ltdc()
496 return (struct ltdc_device *)enc->dev->dev_private; in encoder_to_ltdc()
555 u32 lofs = plane->index * LAY_OFS, ret = PF_FLEXIBLE; in ltdc_set_flexible_pixel_format()
595 regmap_write(ldev->regmap, LTDC_L1FPF0R + lofs, in ltdc_set_flexible_pixel_format()
598 regmap_write(ldev->regmap, LTDC_L1FPF1R + lofs, in ltdc_set_flexible_pixel_format()
606 * All non-alpha color formats derived from native alpha color formats are
617 struct drm_plane_state *state = plane->state; in ltdc_set_ycbcr_config()
618 u32 lofs = plane->index * LAY_OFS; in ltdc_set_ycbcr_config()
651 if (state->color_range == DRM_COLOR_YCBCR_LIMITED_RANGE) in ltdc_set_ycbcr_config()
657 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, val); in ltdc_set_ycbcr_config()
663 struct drm_plane_state *state = plane->state; in ltdc_set_ycbcr_coeffs()
664 enum drm_color_encoding enc = state->color_encoding; in ltdc_set_ycbcr_coeffs()
665 enum drm_color_range ran = state->color_range; in ltdc_set_ycbcr_coeffs()
666 u32 lofs = plane->index * LAY_OFS; in ltdc_set_ycbcr_coeffs()
681 regmap_write(ldev->regmap, LTDC_L1CYR0R + lofs, in ltdc_set_ycbcr_coeffs()
683 regmap_write(ldev->regmap, LTDC_L1CYR1R + lofs, in ltdc_set_ycbcr_coeffs()
693 if (ldev->crc_skip_count < CRC_SKIP_FRAMES) { in ltdc_irq_crc_handle()
694 ldev->crc_skip_count++; in ltdc_irq_crc_handle()
699 ret = regmap_read(ldev->regmap, LTDC_CCRCR, &crc); in ltdc_irq_crc_handle()
710 struct ltdc_device *ldev = ddev->dev_private; in ltdc_irq_thread()
714 if (ldev->irq_status & ISR_LIF) { in ltdc_irq_thread()
718 if (ldev->crc_active) in ltdc_irq_thread()
722 mutex_lock(&ldev->err_lock); in ltdc_irq_thread()
723 if (ldev->irq_status & ISR_TERRIF) in ltdc_irq_thread()
724 ldev->transfer_err++; in ltdc_irq_thread()
725 if (ldev->irq_status & ISR_FUEIF) in ltdc_irq_thread()
726 ldev->fifo_err++; in ltdc_irq_thread()
727 if (ldev->irq_status & ISR_FUWIF) in ltdc_irq_thread()
728 ldev->fifo_warn++; in ltdc_irq_thread()
729 mutex_unlock(&ldev->err_lock); in ltdc_irq_thread()
737 struct ltdc_device *ldev = ddev->dev_private; in ltdc_irq()
744 ldev->irq_status = readl_relaxed(ldev->regs + LTDC_ISR); in ltdc_irq()
745 writel_relaxed(ldev->irq_status, ldev->regs + LTDC_ICR); in ltdc_irq()
761 if (!crtc->state->color_mgmt_changed || !crtc->state->gamma_lut) in ltdc_crtc_update_clut()
764 lut = (struct drm_color_lut *)crtc->state->gamma_lut->data; in ltdc_crtc_update_clut()
767 val = ((lut->red << 8) & 0xff0000) | (lut->green & 0xff00) | in ltdc_crtc_update_clut()
768 (lut->blue >> 8) | (i << 24); in ltdc_crtc_update_clut()
769 regmap_write(ldev->regmap, LTDC_L1CLUTWR, val); in ltdc_crtc_update_clut()
777 struct drm_device *ddev = crtc->dev; in ltdc_crtc_atomic_enable()
781 pm_runtime_get_sync(ddev->dev); in ltdc_crtc_atomic_enable()
784 regmap_write(ldev->regmap, LTDC_BCCR, BCCR_BCBLACK); in ltdc_crtc_atomic_enable()
787 regmap_set_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE); in ltdc_crtc_atomic_enable()
790 if (!ldev->caps.plane_reg_shadow) in ltdc_crtc_atomic_enable()
791 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); in ltdc_crtc_atomic_enable()
800 struct drm_device *ddev = crtc->dev; in ltdc_crtc_atomic_disable()
808 for (layer_index = 0; layer_index < ldev->caps.nb_layers; layer_index++) in ltdc_crtc_atomic_disable()
809 regmap_write_bits(ldev->regmap, LTDC_L1CR + layer_index * LAY_OFS, in ltdc_crtc_atomic_disable()
813 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_FUWIE | IER_FUEIE | IER_RRIE | IER_TERRIE); in ltdc_crtc_atomic_disable()
816 if (!ldev->caps.plane_reg_shadow) in ltdc_crtc_atomic_disable()
817 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_IMR); in ltdc_crtc_atomic_disable()
819 pm_runtime_put_sync(ddev->dev); in ltdc_crtc_atomic_disable()
822 mutex_lock(&ldev->err_lock); in ltdc_crtc_atomic_disable()
823 ldev->transfer_err = 0; in ltdc_crtc_atomic_disable()
824 ldev->fifo_err = 0; in ltdc_crtc_atomic_disable()
825 ldev->fifo_warn = 0; in ltdc_crtc_atomic_disable()
826 mutex_unlock(&ldev->err_lock); in ltdc_crtc_atomic_disable()
836 int target = mode->clock * 1000; in ltdc_crtc_mode_valid()
837 int target_min = target - CLK_TOLERANCE_HZ; in ltdc_crtc_mode_valid()
841 result = clk_round_rate(ldev->pixel_clk, target); in ltdc_crtc_mode_valid()
846 if (result > ldev->caps.pad_max_freq_hz) in ltdc_crtc_mode_valid()
851 * - this is important for panels because panel clock tolerances are in ltdc_crtc_mode_valid()
854 * - the hdmi preferred mode will be accepted too, but userland will in ltdc_crtc_mode_valid()
857 if (mode->type & DRM_MODE_TYPE_PREFERRED) in ltdc_crtc_mode_valid()
875 int rate = mode->clock * 1000; in ltdc_crtc_mode_fixup()
877 if (clk_set_rate(ldev->pixel_clk, rate) < 0) { in ltdc_crtc_mode_fixup()
882 adjusted_mode->clock = clk_get_rate(ldev->pixel_clk) / 1000; in ltdc_crtc_mode_fixup()
885 mode->clock, adjusted_mode->clock); in ltdc_crtc_mode_fixup()
893 struct drm_device *ddev = crtc->dev; in ltdc_crtc_mode_set_nofb()
898 struct drm_display_mode *mode = &crtc->state->adjusted_mode; in ltdc_crtc_mode_set_nofb()
908 if (en_iter->crtc == crtc) { in ltdc_crtc_mode_set_nofb()
915 list_for_each_entry(br_iter, &encoder->bridge_chain, chain_node) in ltdc_crtc_mode_set_nofb()
916 if (br_iter->encoder == encoder) { in ltdc_crtc_mode_set_nofb()
924 if (connector->encoder == encoder) in ltdc_crtc_mode_set_nofb()
929 if (bridge && bridge->timings) { in ltdc_crtc_mode_set_nofb()
930 bus_flags = bridge->timings->input_bus_flags; in ltdc_crtc_mode_set_nofb()
932 bus_flags = connector->display_info.bus_flags; in ltdc_crtc_mode_set_nofb()
933 if (connector->display_info.num_bus_formats) in ltdc_crtc_mode_set_nofb()
934 bus_formats = connector->display_info.bus_formats[0]; in ltdc_crtc_mode_set_nofb()
937 if (!pm_runtime_active(ddev->dev)) { in ltdc_crtc_mode_set_nofb()
938 ret = pm_runtime_get_sync(ddev->dev); in ltdc_crtc_mode_set_nofb()
945 DRM_DEBUG_DRIVER("CRTC:%d mode:%s\n", crtc->base.id, mode->name); in ltdc_crtc_mode_set_nofb()
946 DRM_DEBUG_DRIVER("Video mode: %dx%d", mode->hdisplay, mode->vdisplay); in ltdc_crtc_mode_set_nofb()
948 mode->hsync_start - mode->hdisplay, in ltdc_crtc_mode_set_nofb()
949 mode->htotal - mode->hsync_end, in ltdc_crtc_mode_set_nofb()
950 mode->hsync_end - mode->hsync_start, in ltdc_crtc_mode_set_nofb()
951 mode->vsync_start - mode->vdisplay, in ltdc_crtc_mode_set_nofb()
952 mode->vtotal - mode->vsync_end, in ltdc_crtc_mode_set_nofb()
953 mode->vsync_end - mode->vsync_start); in ltdc_crtc_mode_set_nofb()
956 hsync = mode->hsync_end - mode->hsync_start - 1; in ltdc_crtc_mode_set_nofb()
957 vsync = mode->vsync_end - mode->vsync_start - 1; in ltdc_crtc_mode_set_nofb()
958 accum_hbp = mode->htotal - mode->hsync_start - 1; in ltdc_crtc_mode_set_nofb()
959 accum_vbp = mode->vtotal - mode->vsync_start - 1; in ltdc_crtc_mode_set_nofb()
960 accum_act_w = accum_hbp + mode->hdisplay; in ltdc_crtc_mode_set_nofb()
961 accum_act_h = accum_vbp + mode->vdisplay; in ltdc_crtc_mode_set_nofb()
962 total_width = mode->htotal - 1; in ltdc_crtc_mode_set_nofb()
963 total_height = mode->vtotal - 1; in ltdc_crtc_mode_set_nofb()
968 if (mode->flags & DRM_MODE_FLAG_PHSYNC) in ltdc_crtc_mode_set_nofb()
971 if (mode->flags & DRM_MODE_FLAG_PVSYNC) in ltdc_crtc_mode_set_nofb()
980 regmap_update_bits(ldev->regmap, LTDC_GCR, in ltdc_crtc_mode_set_nofb()
985 regmap_update_bits(ldev->regmap, LTDC_SSCR, SSCR_VSH | SSCR_HSW, val); in ltdc_crtc_mode_set_nofb()
989 regmap_update_bits(ldev->regmap, LTDC_BPCR, BPCR_AVBP | BPCR_AHBP, val); in ltdc_crtc_mode_set_nofb()
993 regmap_update_bits(ldev->regmap, LTDC_AWCR, AWCR_AAW | AWCR_AAH, val); in ltdc_crtc_mode_set_nofb()
997 regmap_update_bits(ldev->regmap, LTDC_TWCR, TWCR_TOTALH | TWCR_TOTALW, val); in ltdc_crtc_mode_set_nofb()
999 regmap_write(ldev->regmap, LTDC_LIPCR, (accum_act_h + 1)); in ltdc_crtc_mode_set_nofb()
1002 if (ldev->caps.ycbcr_output) { in ltdc_crtc_mode_set_nofb()
1009 /* ITU-R BT.601 */ in ltdc_crtc_mode_set_nofb()
1012 /* ITU-R BT.709 */ in ltdc_crtc_mode_set_nofb()
1018 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | val); in ltdc_crtc_mode_set_nofb()
1022 regmap_write(ldev->regmap, LTDC_EDCR, EDCR_OCYEN | EDCR_OCYCO | val); in ltdc_crtc_mode_set_nofb()
1026 regmap_write(ldev->regmap, LTDC_EDCR, 0); in ltdc_crtc_mode_set_nofb()
1036 struct drm_device *ddev = crtc->dev; in ltdc_crtc_atomic_flush()
1037 struct drm_pending_vblank_event *event = crtc->state->event; in ltdc_crtc_atomic_flush()
1044 if (!ldev->caps.plane_reg_shadow) in ltdc_crtc_atomic_flush()
1045 regmap_set_bits(ldev->regmap, LTDC_SRCR, SRCR_VBR); in ltdc_crtc_atomic_flush()
1048 crtc->state->event = NULL; in ltdc_crtc_atomic_flush()
1050 spin_lock_irq(&ddev->event_lock); in ltdc_crtc_atomic_flush()
1055 spin_unlock_irq(&ddev->event_lock); in ltdc_crtc_atomic_flush()
1065 struct drm_device *ddev = crtc->dev; in ltdc_crtc_get_scanout_position()
1066 struct ltdc_device *ldev = ddev->dev_private; in ltdc_crtc_get_scanout_position()
1076 * - line < vactive_start: vpos = line - vactive_start and will be in ltdc_crtc_get_scanout_position()
1078 * - vactive_start < line < vactive_end: vpos = line - vactive_start in ltdc_crtc_get_scanout_position()
1080 * - line > vactive_end: vpos = line - vtotal - vactive_start in ltdc_crtc_get_scanout_position()
1086 if (pm_runtime_active(ddev->dev)) { in ltdc_crtc_get_scanout_position()
1087 regmap_read(ldev->regmap, LTDC_CPSR, &line); in ltdc_crtc_get_scanout_position()
1089 regmap_read(ldev->regmap, LTDC_BPCR, &vactive_start); in ltdc_crtc_get_scanout_position()
1091 regmap_read(ldev->regmap, LTDC_AWCR, &vactive_end); in ltdc_crtc_get_scanout_position()
1093 regmap_read(ldev->regmap, LTDC_TWCR, &vtotal); in ltdc_crtc_get_scanout_position()
1097 *vpos = line - vtotal - vactive_start; in ltdc_crtc_get_scanout_position()
1099 *vpos = line - vactive_start; in ltdc_crtc_get_scanout_position()
1125 struct drm_crtc_state *state = crtc->state; in ltdc_crtc_enable_vblank()
1129 if (state->enable) in ltdc_crtc_enable_vblank()
1130 regmap_set_bits(ldev->regmap, LTDC_IER, IER_LIE); in ltdc_crtc_enable_vblank()
1132 return -EPERM; in ltdc_crtc_enable_vblank()
1142 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE); in ltdc_crtc_disable_vblank()
1153 return -ENODEV; in ltdc_crtc_set_crc_source()
1158 ldev->crc_active = true; in ltdc_crtc_set_crc_source()
1159 ret = regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); in ltdc_crtc_set_crc_source()
1161 ldev->crc_active = false; in ltdc_crtc_set_crc_source()
1162 ret = regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_CRCEN); in ltdc_crtc_set_crc_source()
1164 ret = -EINVAL; in ltdc_crtc_set_crc_source()
1167 ldev->crc_skip_count = 0; in ltdc_crtc_set_crc_source()
1177 return -ENODEV; in ltdc_crtc_verify_crc_source()
1181 source, crtc->name); in ltdc_crtc_verify_crc_source()
1182 return -EINVAL; in ltdc_crtc_verify_crc_source()
1192 struct drm_crtc *crtc = state->crtc; in ltdc_crtc_atomic_print_state()
1195 drm_printf(p, "\ttransfer_error=%d\n", ldev->transfer_err); in ltdc_crtc_atomic_print_state()
1196 drm_printf(p, "\tfifo_underrun_error=%d\n", ldev->fifo_err); in ltdc_crtc_atomic_print_state()
1197 drm_printf(p, "\tfifo_underrun_warning=%d\n", ldev->fifo_warn); in ltdc_crtc_atomic_print_state()
1198 drm_printf(p, "\tfifo_underrun_threshold=%d\n", ldev->fifo_threshold); in ltdc_crtc_atomic_print_state()
1238 struct drm_framebuffer *fb = new_plane_state->fb; in ltdc_plane_atomic_check()
1247 src_w = new_plane_state->src_w >> 16; in ltdc_plane_atomic_check()
1248 src_h = new_plane_state->src_h >> 16; in ltdc_plane_atomic_check()
1251 if (src_w != new_plane_state->crtc_w || src_h != new_plane_state->crtc_h) { in ltdc_plane_atomic_check()
1254 return -EINVAL; in ltdc_plane_atomic_check()
1266 struct drm_framebuffer *fb = newstate->fb; in ltdc_plane_atomic_update()
1267 u32 lofs = plane->index * LAY_OFS; in ltdc_plane_atomic_update()
1268 u32 x0 = newstate->crtc_x; in ltdc_plane_atomic_update()
1269 u32 x1 = newstate->crtc_x + newstate->crtc_w - 1; in ltdc_plane_atomic_update()
1270 u32 y0 = newstate->crtc_y; in ltdc_plane_atomic_update()
1271 u32 y1 = newstate->crtc_y + newstate->crtc_h - 1; in ltdc_plane_atomic_update()
1277 if (!newstate->crtc || !fb) { in ltdc_plane_atomic_update()
1283 src_x = newstate->src_x >> 16; in ltdc_plane_atomic_update()
1284 src_y = newstate->src_y >> 16; in ltdc_plane_atomic_update()
1285 src_w = newstate->src_w >> 16; in ltdc_plane_atomic_update()
1286 src_h = newstate->src_h >> 16; in ltdc_plane_atomic_update()
1288 DRM_DEBUG_DRIVER("plane:%d fb:%d (%dx%d)@(%d,%d) -> (%dx%d)@(%d,%d)\n", in ltdc_plane_atomic_update()
1289 plane->base.id, fb->base.id, in ltdc_plane_atomic_update()
1291 newstate->crtc_w, newstate->crtc_h, in ltdc_plane_atomic_update()
1292 newstate->crtc_x, newstate->crtc_y); in ltdc_plane_atomic_update()
1294 regmap_read(ldev->regmap, LTDC_BPCR, &bpcr); in ltdc_plane_atomic_update()
1301 regmap_write_bits(ldev->regmap, LTDC_L1WHPCR + lofs, in ltdc_plane_atomic_update()
1306 regmap_write_bits(ldev->regmap, LTDC_L1WVPCR + lofs, in ltdc_plane_atomic_update()
1310 pf = to_ltdc_pixelformat(fb->format->format); in ltdc_plane_atomic_update()
1312 if (ldev->caps.pix_fmt_hw[val] == pf) in ltdc_plane_atomic_update()
1316 if (ldev->caps.pix_fmt_flex && val == NB_PF) in ltdc_plane_atomic_update()
1321 (char *)&fb->format->format); in ltdc_plane_atomic_update()
1324 regmap_write_bits(ldev->regmap, LTDC_L1PFCR + lofs, LXPFCR_PF, val); in ltdc_plane_atomic_update()
1327 val = newstate->alpha >> 8; in ltdc_plane_atomic_update()
1328 regmap_write_bits(ldev->regmap, LTDC_L1CACR + lofs, LXCACR_CONSTA, val); in ltdc_plane_atomic_update()
1332 if (!fb->format->has_alpha) in ltdc_plane_atomic_update()
1335 /* Manage hw-specific capabilities */ in ltdc_plane_atomic_update()
1336 if (ldev->caps.non_alpha_only_l1 && in ltdc_plane_atomic_update()
1337 plane->type != DRM_PLANE_TYPE_PRIMARY) in ltdc_plane_atomic_update()
1340 if (ldev->caps.dynamic_zorder) { in ltdc_plane_atomic_update()
1341 val |= (newstate->normalized_zpos << 16); in ltdc_plane_atomic_update()
1342 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, in ltdc_plane_atomic_update()
1345 regmap_write_bits(ldev->regmap, LTDC_L1BFCR + lofs, in ltdc_plane_atomic_update()
1352 if (newstate->rotation & DRM_MODE_REFLECT_X) in ltdc_plane_atomic_update()
1353 paddr += (fb->format->cpp[0] * (x1 - x0 + 1)) - 1; in ltdc_plane_atomic_update()
1355 if (newstate->rotation & DRM_MODE_REFLECT_Y) in ltdc_plane_atomic_update()
1356 paddr += (fb->pitches[0] * (y1 - y0)); in ltdc_plane_atomic_update()
1359 regmap_write(ldev->regmap, LTDC_L1CFBAR + lofs, paddr); in ltdc_plane_atomic_update()
1362 line_length = fb->format->cpp[0] * in ltdc_plane_atomic_update()
1363 (x1 - x0 + 1) + (ldev->caps.bus_width >> 3) - 1; in ltdc_plane_atomic_update()
1365 if (newstate->rotation & DRM_MODE_REFLECT_Y) in ltdc_plane_atomic_update()
1367 pitch_in_bytes = 0x10000 - fb->pitches[0]; in ltdc_plane_atomic_update()
1369 pitch_in_bytes = fb->pitches[0]; in ltdc_plane_atomic_update()
1372 regmap_write_bits(ldev->regmap, LTDC_L1CFBLR + lofs, LXCFBLR_CFBLL | LXCFBLR_CFBP, val); in ltdc_plane_atomic_update()
1375 line_number = y1 - y0 + 1; in ltdc_plane_atomic_update()
1376 regmap_write_bits(ldev->regmap, LTDC_L1CFBLNR + lofs, LXCFBLNR_CFBLN, line_number); in ltdc_plane_atomic_update()
1378 if (ldev->caps.ycbcr_input) { in ltdc_plane_atomic_update()
1379 if (fb->format->is_yuv) { in ltdc_plane_atomic_update()
1380 switch (fb->format->format) { in ltdc_plane_atomic_update()
1386 if (newstate->rotation & DRM_MODE_REFLECT_X) in ltdc_plane_atomic_update()
1387 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1389 if (newstate->rotation & DRM_MODE_REFLECT_Y) in ltdc_plane_atomic_update()
1390 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1392 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); in ltdc_plane_atomic_update()
1399 if (newstate->rotation & DRM_MODE_REFLECT_X) { in ltdc_plane_atomic_update()
1400 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1401 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1404 if (newstate->rotation & DRM_MODE_REFLECT_Y) { in ltdc_plane_atomic_update()
1405 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1406 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1409 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); in ltdc_plane_atomic_update()
1410 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); in ltdc_plane_atomic_update()
1417 if (newstate->rotation & DRM_MODE_REFLECT_X) { in ltdc_plane_atomic_update()
1418 paddr1 += ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1419 paddr2 += ((fb->format->cpp[2] * (x1 - x0 + 1)) >> 1) - 1; in ltdc_plane_atomic_update()
1422 if (newstate->rotation & DRM_MODE_REFLECT_Y) { in ltdc_plane_atomic_update()
1423 paddr1 += (fb->pitches[1] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1424 paddr2 += (fb->pitches[2] * (y1 - y0 - 1)) >> 1; in ltdc_plane_atomic_update()
1427 regmap_write(ldev->regmap, LTDC_L1AFBA0R + lofs, paddr1); in ltdc_plane_atomic_update()
1428 regmap_write(ldev->regmap, LTDC_L1AFBA1R + lofs, paddr2); in ltdc_plane_atomic_update()
1436 if (fb->format->num_planes > 1) { in ltdc_plane_atomic_update()
1437 if (newstate->rotation & DRM_MODE_REFLECT_Y) in ltdc_plane_atomic_update()
1442 pitch_in_bytes = 0x10000 - fb->pitches[1]; in ltdc_plane_atomic_update()
1444 pitch_in_bytes = fb->pitches[1]; in ltdc_plane_atomic_update()
1446 line_length = ((fb->format->cpp[1] * (x1 - x0 + 1)) >> 1) + in ltdc_plane_atomic_update()
1447 (ldev->caps.bus_width >> 3) - 1; in ltdc_plane_atomic_update()
1451 regmap_write(ldev->regmap, LTDC_L1AFBLR + lofs, val); in ltdc_plane_atomic_update()
1455 regmap_write(ldev->regmap, LTDC_L1AFBLNR + lofs, val); in ltdc_plane_atomic_update()
1462 ltdc_set_ycbcr_config(plane, fb->format->format); in ltdc_plane_atomic_update()
1465 regmap_write(ldev->regmap, LTDC_L1PCR + lofs, 0); in ltdc_plane_atomic_update()
1469 /* Enable layer and CLUT if needed */ in ltdc_plane_atomic_update()
1470 val = fb->format->format == DRM_FORMAT_C8 ? LXCR_CLUTEN : 0; in ltdc_plane_atomic_update()
1474 if (newstate->rotation & DRM_MODE_REFLECT_X) in ltdc_plane_atomic_update()
1477 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, val); in ltdc_plane_atomic_update()
1480 if (ldev->caps.plane_reg_shadow) in ltdc_plane_atomic_update()
1481 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, in ltdc_plane_atomic_update()
1484 ldev->plane_fpsi[plane->index].counter++; in ltdc_plane_atomic_update()
1486 mutex_lock(&ldev->err_lock); in ltdc_plane_atomic_update()
1487 if (ldev->transfer_err) { in ltdc_plane_atomic_update()
1488 DRM_WARN("ltdc transfer error: %d\n", ldev->transfer_err); in ltdc_plane_atomic_update()
1489 ldev->transfer_err = 0; in ltdc_plane_atomic_update()
1492 if (ldev->caps.fifo_threshold) { in ltdc_plane_atomic_update()
1493 if (ldev->fifo_err) { in ltdc_plane_atomic_update()
1495 ldev->fifo_err = 0; in ltdc_plane_atomic_update()
1498 if (ldev->fifo_warn >= ldev->fifo_threshold) { in ltdc_plane_atomic_update()
1500 ldev->fifo_warn = 0; in ltdc_plane_atomic_update()
1503 mutex_unlock(&ldev->err_lock); in ltdc_plane_atomic_update()
1512 u32 lofs = plane->index * LAY_OFS; in ltdc_plane_atomic_disable()
1514 /* Disable layer */ in ltdc_plane_atomic_disable()
1515 regmap_write_bits(ldev->regmap, LTDC_L1CR + lofs, LXCR_LEN | LXCR_CLUTEN | LXCR_HMEN, 0); in ltdc_plane_atomic_disable()
1518 if (ldev->caps.plane_reg_shadow) in ltdc_plane_atomic_disable()
1519 regmap_write_bits(ldev->regmap, LTDC_L1RCR + lofs, in ltdc_plane_atomic_disable()
1523 oldstate->crtc->base.id, plane->base.id); in ltdc_plane_atomic_disable()
1529 struct drm_plane *plane = state->plane; in ltdc_plane_atomic_print_state()
1531 struct fps_info *fpsi = &ldev->plane_fpsi[plane->index]; in ltdc_plane_atomic_print_state()
1536 ms_since_last = ktime_to_ms(ktime_sub(now, fpsi->last_timestamp)); in ltdc_plane_atomic_print_state()
1539 DIV_ROUND_CLOSEST(fpsi->counter * 1000, ms_since_last)); in ltdc_plane_atomic_print_state()
1541 fpsi->last_timestamp = now; in ltdc_plane_atomic_print_state()
1542 fpsi->counter = 0; in ltdc_plane_atomic_print_state()
1566 struct ltdc_device *ldev = ddev->dev_private; in ltdc_plane_create()
1567 struct device *dev = ddev->dev; in ltdc_plane_create()
1578 formats = devm_kzalloc(dev, (ldev->caps.pix_fmt_nb + in ltdc_plane_create()
1584 for (i = 0; i < ldev->caps.pix_fmt_nb; i++) { in ltdc_plane_create()
1585 drm_fmt = ldev->caps.pix_fmt_drm[i]; in ltdc_plane_create()
1587 /* Manage hw-specific capabilities */ in ltdc_plane_create()
1588 if (ldev->caps.non_alpha_only_l1) in ltdc_plane_create()
1589 /* XR24 & RX24 like formats supported only on primary layer */ in ltdc_plane_create()
1597 if (ldev->caps.ycbcr_input) { in ltdc_plane_create()
1598 regmap_read(ldev->regmap, LTDC_L1C1R + lofs, &val); in ltdc_plane_create()
1626 if (ldev->caps.ycbcr_input) { in ltdc_plane_create()
1641 DRM_DEBUG_DRIVER("plane:%d created\n", plane->base.id); in ltdc_plane_create()
1651 &ddev->mode_config.plane_list, head) in ltdc_plane_destroy_all()
1657 struct ltdc_device *ldev = ddev->dev_private; in ltdc_crtc_init()
1658 struct drm_plane *primary, *overlay; in ltdc_crtc_init() local
1663 primary = ltdc_plane_create(ddev, DRM_PLANE_TYPE_PRIMARY, 0); in ltdc_crtc_init()
1664 if (!primary) { in ltdc_crtc_init()
1665 DRM_ERROR("Can not create primary plane\n"); in ltdc_crtc_init()
1666 return -EINVAL; in ltdc_crtc_init()
1669 if (ldev->caps.dynamic_zorder) in ltdc_crtc_init()
1670 drm_plane_create_zpos_property(primary, 0, 0, ldev->caps.nb_layers - 1); in ltdc_crtc_init()
1672 drm_plane_create_zpos_immutable_property(primary, 0); in ltdc_crtc_init()
1674 if (ldev->caps.plane_rotation) in ltdc_crtc_init()
1675 drm_plane_create_rotation_property(primary, DRM_MODE_ROTATE_0, in ltdc_crtc_init()
1679 if (ldev->caps.crc) in ltdc_crtc_init()
1680 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, in ltdc_crtc_init()
1683 ret = drm_crtc_init_with_planes(ddev, crtc, primary, NULL, in ltdc_crtc_init()
1695 DRM_DEBUG_DRIVER("CRTC:%d created\n", crtc->base.id); in ltdc_crtc_init()
1697 /* Add planes. Note : the first layer is used by primary plane */ in ltdc_crtc_init()
1698 for (i = 1; i < ldev->caps.nb_layers; i++) { in ltdc_crtc_init()
1701 ret = -ENOMEM; in ltdc_crtc_init()
1705 if (ldev->caps.dynamic_zorder) in ltdc_crtc_init()
1706 drm_plane_create_zpos_property(overlay, i, 0, ldev->caps.nb_layers - 1); in ltdc_crtc_init()
1710 if (ldev->caps.plane_rotation) in ltdc_crtc_init()
1724 struct drm_device *ddev = encoder->dev; in ltdc_encoder_disable()
1725 struct ltdc_device *ldev = ddev->dev_private; in ltdc_encoder_disable()
1730 regmap_clear_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); in ltdc_encoder_disable()
1733 pinctrl_pm_select_sleep_state(ddev->dev); in ltdc_encoder_disable()
1738 struct drm_device *ddev = encoder->dev; in ltdc_encoder_enable()
1739 struct ltdc_device *ldev = ddev->dev_private; in ltdc_encoder_enable()
1744 if (ldev->caps.fifo_threshold) in ltdc_encoder_enable()
1745 regmap_write(ldev->regmap, LTDC_FUT, ldev->fifo_threshold); in ltdc_encoder_enable()
1748 regmap_set_bits(ldev->regmap, LTDC_GCR, GCR_LTDCEN); in ltdc_encoder_enable()
1755 struct drm_device *ddev = encoder->dev; in ltdc_encoder_mode_set()
1764 if (encoder->encoder_type == DRM_MODE_ENCODER_DPI) in ltdc_encoder_mode_set()
1765 pinctrl_pm_select_default_state(ddev->dev); in ltdc_encoder_mode_set()
1779 encoder = devm_kzalloc(ddev->dev, sizeof(*encoder), GFP_KERNEL); in ltdc_encoder_init()
1781 return -ENOMEM; in ltdc_encoder_init()
1783 encoder->possible_crtcs = CRTC_MASK; in ltdc_encoder_init()
1784 encoder->possible_clones = 0; /* No cloning support */ in ltdc_encoder_init()
1792 if (ret != -EPROBE_DEFER) in ltdc_encoder_init()
1797 DRM_DEBUG_DRIVER("Bridge encoder:%d created\n", encoder->base.id); in ltdc_encoder_init()
1804 struct ltdc_device *ldev = ddev->dev_private; in ltdc_get_caps()
1808 * at least 1 layer must be managed & the number of layers in ltdc_get_caps()
1811 regmap_read(ldev->regmap, LTDC_LCR, &lcr); in ltdc_get_caps()
1813 ldev->caps.nb_layers = clamp((int)lcr, 1, LTDC_MAX_LAYER); in ltdc_get_caps()
1816 regmap_read(ldev->regmap, LTDC_GC2R, &gc2r); in ltdc_get_caps()
1818 ldev->caps.bus_width = 8 << bus_width_log2; in ltdc_get_caps()
1819 regmap_read(ldev->regmap, LTDC_IDR, &ldev->caps.hw_version); in ltdc_get_caps()
1821 switch (ldev->caps.hw_version) { in ltdc_get_caps()
1824 ldev->caps.layer_ofs = LAY_OFS_0; in ltdc_get_caps()
1825 ldev->caps.layer_regs = ltdc_layer_regs_a0; in ltdc_get_caps()
1826 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a0; in ltdc_get_caps()
1827 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a0; in ltdc_get_caps()
1828 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a0); in ltdc_get_caps()
1829 ldev->caps.pix_fmt_flex = false; in ltdc_get_caps()
1831 * Hw older versions support non-alpha color formats derived in ltdc_get_caps()
1832 * from native alpha color formats only on the primary layer. in ltdc_get_caps()
1834 * on 2nd layer but XR24 (derived color format from AR24) in ltdc_get_caps()
1835 * does not work on 2nd layer. in ltdc_get_caps()
1837 ldev->caps.non_alpha_only_l1 = true; in ltdc_get_caps()
1838 ldev->caps.pad_max_freq_hz = 90000000; in ltdc_get_caps()
1839 if (ldev->caps.hw_version == HWVER_10200) in ltdc_get_caps()
1840 ldev->caps.pad_max_freq_hz = 65000000; in ltdc_get_caps()
1841 ldev->caps.nb_irq = 2; in ltdc_get_caps()
1842 ldev->caps.ycbcr_input = false; in ltdc_get_caps()
1843 ldev->caps.ycbcr_output = false; in ltdc_get_caps()
1844 ldev->caps.plane_reg_shadow = false; in ltdc_get_caps()
1845 ldev->caps.crc = false; in ltdc_get_caps()
1846 ldev->caps.dynamic_zorder = false; in ltdc_get_caps()
1847 ldev->caps.plane_rotation = false; in ltdc_get_caps()
1848 ldev->caps.fifo_threshold = false; in ltdc_get_caps()
1851 ldev->caps.layer_ofs = LAY_OFS_0; in ltdc_get_caps()
1852 ldev->caps.layer_regs = ltdc_layer_regs_a1; in ltdc_get_caps()
1853 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a1; in ltdc_get_caps()
1854 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a1; in ltdc_get_caps()
1855 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a1); in ltdc_get_caps()
1856 ldev->caps.pix_fmt_flex = false; in ltdc_get_caps()
1857 ldev->caps.non_alpha_only_l1 = false; in ltdc_get_caps()
1858 ldev->caps.pad_max_freq_hz = 150000000; in ltdc_get_caps()
1859 ldev->caps.nb_irq = 4; in ltdc_get_caps()
1860 ldev->caps.ycbcr_input = false; in ltdc_get_caps()
1861 ldev->caps.ycbcr_output = false; in ltdc_get_caps()
1862 ldev->caps.plane_reg_shadow = false; in ltdc_get_caps()
1863 ldev->caps.crc = false; in ltdc_get_caps()
1864 ldev->caps.dynamic_zorder = false; in ltdc_get_caps()
1865 ldev->caps.plane_rotation = false; in ltdc_get_caps()
1866 ldev->caps.fifo_threshold = false; in ltdc_get_caps()
1869 ldev->caps.layer_ofs = LAY_OFS_1; in ltdc_get_caps()
1870 ldev->caps.layer_regs = ltdc_layer_regs_a2; in ltdc_get_caps()
1871 ldev->caps.pix_fmt_hw = ltdc_pix_fmt_a2; in ltdc_get_caps()
1872 ldev->caps.pix_fmt_drm = ltdc_drm_fmt_a2; in ltdc_get_caps()
1873 ldev->caps.pix_fmt_nb = ARRAY_SIZE(ltdc_drm_fmt_a2); in ltdc_get_caps()
1874 ldev->caps.pix_fmt_flex = true; in ltdc_get_caps()
1875 ldev->caps.non_alpha_only_l1 = false; in ltdc_get_caps()
1876 ldev->caps.pad_max_freq_hz = 90000000; in ltdc_get_caps()
1877 ldev->caps.nb_irq = 2; in ltdc_get_caps()
1878 ldev->caps.ycbcr_input = true; in ltdc_get_caps()
1879 ldev->caps.ycbcr_output = true; in ltdc_get_caps()
1880 ldev->caps.plane_reg_shadow = true; in ltdc_get_caps()
1881 ldev->caps.crc = true; in ltdc_get_caps()
1882 ldev->caps.dynamic_zorder = true; in ltdc_get_caps()
1883 ldev->caps.plane_rotation = true; in ltdc_get_caps()
1884 ldev->caps.fifo_threshold = true; in ltdc_get_caps()
1887 return -ENODEV; in ltdc_get_caps()
1895 struct ltdc_device *ldev = ddev->dev_private; in ltdc_suspend()
1898 clk_disable_unprepare(ldev->pixel_clk); in ltdc_suspend()
1903 struct ltdc_device *ldev = ddev->dev_private; in ltdc_resume()
1908 ret = clk_prepare_enable(ldev->pixel_clk); in ltdc_resume()
1919 struct platform_device *pdev = to_platform_device(ddev->dev); in ltdc_load()
1920 struct ltdc_device *ldev = ddev->dev_private; in ltdc_load()
1921 struct device *dev = ddev->dev; in ltdc_load()
1922 struct device_node *np = dev->of_node; in ltdc_load()
1929 int ret = -ENODEV; in ltdc_load()
1936 return -ENODEV; in ltdc_load()
1938 ldev->pixel_clk = devm_clk_get(dev, "lcd"); in ltdc_load()
1939 if (IS_ERR(ldev->pixel_clk)) { in ltdc_load()
1940 if (PTR_ERR(ldev->pixel_clk) != -EPROBE_DEFER) in ltdc_load()
1942 return PTR_ERR(ldev->pixel_clk); in ltdc_load()
1945 if (clk_prepare_enable(ldev->pixel_clk)) { in ltdc_load()
1947 return -ENODEV; in ltdc_load()
1955 * If at least one endpoint is -ENODEV, continue probing, in ltdc_load()
1957 * (ie -EPROBE_DEFER) then stop probing. in ltdc_load()
1959 if (ret == -ENODEV) in ltdc_load()
1968 DRM_ERROR("panel-bridge endpoint %d\n", i); in ltdc_load()
1977 if (ret != -EPROBE_DEFER) in ltdc_load()
1986 mutex_init(&ldev->err_lock); in ltdc_load()
1995 ldev->regs = devm_ioremap_resource(dev, res); in ltdc_load()
1996 if (IS_ERR(ldev->regs)) { in ltdc_load()
1998 ret = PTR_ERR(ldev->regs); in ltdc_load()
2002 ldev->regmap = devm_regmap_init_mmio(&pdev->dev, ldev->regs, &stm32_ltdc_regmap_cfg); in ltdc_load()
2003 if (IS_ERR(ldev->regmap)) { in ltdc_load()
2005 ret = PTR_ERR(ldev->regmap); in ltdc_load()
2012 ldev->caps.hw_version); in ltdc_load()
2017 if (ldev->caps.fifo_threshold) in ltdc_load()
2018 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE | in ltdc_load()
2021 regmap_clear_bits(ldev->regmap, LTDC_IER, IER_LIE | IER_RRIE | IER_FUWIE | in ltdc_load()
2024 DRM_DEBUG_DRIVER("ltdc hw version 0x%08x\n", ldev->caps.hw_version); in ltdc_load()
2027 ldev->transfer_err = 0; in ltdc_load()
2028 ldev->fifo_err = 0; in ltdc_load()
2029 ldev->fifo_warn = 0; in ltdc_load()
2030 ldev->fifo_threshold = FUT_DFT; in ltdc_load()
2032 for (i = 0; i < ldev->caps.nb_irq; i++) { in ltdc_load()
2051 ret = -ENOMEM; in ltdc_load()
2067 clk_disable_unprepare(ldev->pixel_clk); in ltdc_load()
2069 pinctrl_pm_select_sleep_state(ddev->dev); in ltdc_load()
2071 pm_runtime_enable(ddev->dev); in ltdc_load()
2076 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); in ltdc_load()
2078 clk_disable_unprepare(ldev->pixel_clk); in ltdc_load()
2085 struct device *dev = ddev->dev; in ltdc_unload()
2090 nb_endpoints = of_graph_get_endpoint_count(dev->of_node); in ltdc_unload()
2093 drm_of_panel_bridge_remove(ddev->dev->of_node, 0, i); in ltdc_unload()
2095 pm_runtime_disable(ddev->dev); in ltdc_unload()