1 // SPDX-License-Identifier: GPL-2.0
89 	writel(val, dsi->base + reg);  in dsi_write()
94 	return readl(dsi->base + reg);  in dsi_read()
150 		return -EINVAL;  in dsi_pll_get_params()
152 	fvco_min = dsi->lane_min_kbps * 2 * ODF_MAX;  in dsi_pll_get_params()
153 	fvco_max = dsi->lane_max_kbps * 2 * ODF_MIN;  in dsi_pll_get_params()
178 			delta = dsi_pll_get_clkout_khz(clkin_khz, i, n, o) -  in dsi_pll_get_params()
181 				delta = -delta;  in dsi_pll_get_params()
205 	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_RRS,  in dw_mipi_dsi_phy_init()
212 	ret = readl_poll_timeout(dsi->base + DSI_WISR, val, val & WISR_PLLLS,  in dw_mipi_dsi_phy_init()
250 	pll_in_khz = (unsigned int)(clk_get_rate(dsi->pllref_clk) / 1000);  in dw_mipi_dsi_get_lane_mbps()
254 	pll_out_khz = mode->clock * bpp / lanes;  in dw_mipi_dsi_get_lane_mbps()
260 	if (pll_out_khz > dsi->lane_max_kbps) {  in dw_mipi_dsi_get_lane_mbps()
261 		pll_out_khz = dsi->lane_max_kbps;  in dw_mipi_dsi_get_lane_mbps()
264 	if (pll_out_khz < dsi->lane_min_kbps) {  in dw_mipi_dsi_get_lane_mbps()
265 		pll_out_khz = dsi->lane_min_kbps;  in dw_mipi_dsi_get_lane_mbps()
283 			(ndiv << 2) | (idf << 11) | ((ffs(odf) - 1) << 16));  in dw_mipi_dsi_get_lane_mbps()
285 	/* Compute uix4 & set the bit period in high-speed mode */  in dw_mipi_dsi_get_lane_mbps()
317 	timing->clk_hs2lp = DSI_PHY_DELAY(272, 136, lane_mbps);  in dw_mipi_dsi_phy_get_timing()
318 	timing->clk_lp2hs = DSI_PHY_DELAY(512, 40, lane_mbps);  in dw_mipi_dsi_phy_get_timing()
319 	timing->data_hs2lp = DSI_PHY_DELAY(192, 64, lane_mbps);  in dw_mipi_dsi_phy_get_timing()
320 	timing->data_lp2hs = DSI_PHY_DELAY(256, 32, lane_mbps);  in dw_mipi_dsi_phy_get_timing()
341 	pll_out_khz = mode->clock * bpp / lanes;  in dw_mipi_dsi_stm_mode_valid()
343 	if (pll_out_khz > dsi->lane_max_kbps)  in dw_mipi_dsi_stm_mode_valid()
350 		if (pll_out_khz < dsi->lane_min_kbps)  in dw_mipi_dsi_stm_mode_valid()
358 	pll_in_khz = clk_get_rate(dsi->pllref_clk) / 1000;  in dw_mipi_dsi_stm_mode_valid()
374 		target_px_clock_hz = mode->clock * 1000;  in dw_mipi_dsi_stm_mode_valid()
379 		if (px_clock_hz < target_px_clock_hz - CLK_TOLERANCE_HZ ||  in dw_mipi_dsi_stm_mode_valid()
386 		hfp = mode->hsync_start - mode->hdisplay;  in dw_mipi_dsi_stm_mode_valid()
387 		hsync = mode->hsync_end - mode->hsync_start;  in dw_mipi_dsi_stm_mode_valid()
388 		hbp = mode->htotal - mode->hsync_end;  in dw_mipi_dsi_stm_mode_valid()
398 			hbp -= dsi_short_packet_size_px;  in dw_mipi_dsi_stm_mode_valid()
401 			hbp += hsync - dsi_short_packet_size_px;  in dw_mipi_dsi_stm_mode_valid()
409 		 * In non-burst mode DSI has to enter in LP during HFP  in dw_mipi_dsi_stm_mode_valid()
411 		 * resync with LTDC pixel clock.  in dw_mipi_dsi_stm_mode_valid()
437 	{ .compatible = "st,stm32-dsi", .data = &dw_mipi_dsi_stm_plat_data, },
444 	struct device *dev = &pdev->dev;  in dw_mipi_dsi_stm_probe()
451 		return -ENOMEM;  in dw_mipi_dsi_stm_probe()
453 	dsi->base = devm_platform_ioremap_resource(pdev, 0);  in dw_mipi_dsi_stm_probe()
454 	if (IS_ERR(dsi->base)) {  in dw_mipi_dsi_stm_probe()
455 		ret = PTR_ERR(dsi->base);  in dw_mipi_dsi_stm_probe()
460 	dsi->vdd_supply = devm_regulator_get(dev, "phy-dsi");  in dw_mipi_dsi_stm_probe()
461 	if (IS_ERR(dsi->vdd_supply)) {  in dw_mipi_dsi_stm_probe()
462 		ret = PTR_ERR(dsi->vdd_supply);  in dw_mipi_dsi_stm_probe()
467 	ret = regulator_enable(dsi->vdd_supply);  in dw_mipi_dsi_stm_probe()
473 	dsi->pllref_clk = devm_clk_get(dev, "ref");  in dw_mipi_dsi_stm_probe()
474 	if (IS_ERR(dsi->pllref_clk)) {  in dw_mipi_dsi_stm_probe()
475 		ret = PTR_ERR(dsi->pllref_clk);  in dw_mipi_dsi_stm_probe()
480 	ret = clk_prepare_enable(dsi->pllref_clk);  in dw_mipi_dsi_stm_probe()
499 	dsi->hw_version = dsi_read(dsi, DSI_VERSION) & VERSION;  in dw_mipi_dsi_stm_probe()
502 	if (dsi->hw_version != HWVER_130 && dsi->hw_version != HWVER_131) {  in dw_mipi_dsi_stm_probe()
503 		ret = -ENODEV;  in dw_mipi_dsi_stm_probe()
509 	dsi->lane_min_kbps = LANE_MIN_KBPS;  in dw_mipi_dsi_stm_probe()
510 	dsi->lane_max_kbps = LANE_MAX_KBPS;  in dw_mipi_dsi_stm_probe()
511 	if (dsi->hw_version == HWVER_131) {  in dw_mipi_dsi_stm_probe()
512 		dsi->lane_min_kbps *= 2;  in dw_mipi_dsi_stm_probe()
513 		dsi->lane_max_kbps *= 2;  in dw_mipi_dsi_stm_probe()
516 	dw_mipi_dsi_stm_plat_data.base = dsi->base;  in dw_mipi_dsi_stm_probe()
521 	dsi->dsi = dw_mipi_dsi_probe(pdev, &dw_mipi_dsi_stm_plat_data);  in dw_mipi_dsi_stm_probe()
522 	if (IS_ERR(dsi->dsi)) {  in dw_mipi_dsi_stm_probe()
523 		ret = PTR_ERR(dsi->dsi);  in dw_mipi_dsi_stm_probe()
531 	clk_disable_unprepare(dsi->pllref_clk);  in dw_mipi_dsi_stm_probe()
533 	regulator_disable(dsi->vdd_supply);  in dw_mipi_dsi_stm_probe()
542 	dw_mipi_dsi_remove(dsi->dsi);  in dw_mipi_dsi_stm_remove()
543 	clk_disable_unprepare(dsi->pllref_clk);  in dw_mipi_dsi_stm_remove()
544 	regulator_disable(dsi->vdd_supply);  in dw_mipi_dsi_stm_remove()
553 	clk_disable_unprepare(dsi->pllref_clk);  in dw_mipi_dsi_stm_suspend()
554 	regulator_disable(dsi->vdd_supply);  in dw_mipi_dsi_stm_suspend()
566 	ret = regulator_enable(dsi->vdd_supply);  in dw_mipi_dsi_stm_resume()
572 	ret = clk_prepare_enable(dsi->pllref_clk);  in dw_mipi_dsi_stm_resume()
574 		regulator_disable(dsi->vdd_supply);  in dw_mipi_dsi_stm_resume()
592 		.name	= "stm32-display-dsi",